1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _U_SIG_EHT_TB_INFO_H_ 18 #define _U_SIG_EHT_TB_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 23 24 25 struct u_sig_eht_tb_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t phy_version : 3, // [2:0] 28 transmit_bw : 3, // [5:3] 29 dl_ul_flag : 1, // [6:6] 30 bss_color_id : 6, // [12:7] 31 txop_duration : 7, // [19:13] 32 disregard_0a : 6, // [25:20] 33 reserved_0c : 6; // [31:26] 34 uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] 35 validate_1a : 1, // [2:2] 36 spatial_reuse : 8, // [10:3] 37 disregard_1b : 5, // [15:11] 38 crc : 4, // [19:16] 39 tail : 6, // [25:20] 40 reserved_1c : 5, // [30:26] 41 rx_integrity_check_passed : 1; // [31:31] 42 #else 43 uint32_t reserved_0c : 6, // [31:26] 44 disregard_0a : 6, // [25:20] 45 txop_duration : 7, // [19:13] 46 bss_color_id : 6, // [12:7] 47 dl_ul_flag : 1, // [6:6] 48 transmit_bw : 3, // [5:3] 49 phy_version : 3; // [2:0] 50 uint32_t rx_integrity_check_passed : 1, // [31:31] 51 reserved_1c : 5, // [30:26] 52 tail : 6, // [25:20] 53 crc : 4, // [19:16] 54 disregard_1b : 5, // [15:11] 55 spatial_reuse : 8, // [10:3] 56 validate_1a : 1, // [2:2] 57 eht_ppdu_sig_cmn_type : 2; // [1:0] 58 #endif 59 }; 60 61 62 /* Description PHY_VERSION 63 64 <enum 0 U_SIG_VERSION_EHT> 65 Values 1 - 7 are reserved. 66 <legal 0> 67 */ 68 69 #define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 70 #define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 71 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 72 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 73 74 75 /* Description TRANSMIT_BW 76 77 Bandwidth of the PPDU, as indicated in the trigger frame 78 79 80 <enum 0 U_SIG_BW20> 20 MHz 81 <enum 1 U_SIG_BW40> 40 MHz 82 <enum 2 U_SIG_BW80> 80 MHz 83 <enum 3 U_SIG_BW160> 160 MHz 84 <enum 4 U_SIG_BW320> 320 MHz channelization scheme 1 85 <enum 5 U_SIG_BW320_2> 320 MHz channelization scheme 2 86 87 On RX side, field used by MAC HW 88 <legal all> 89 */ 90 91 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 92 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 93 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 94 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 95 96 97 /* Description DL_UL_FLAG 98 99 Differentiates between DL and UL transmission 100 101 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 102 <enum 1 DL_UL_FLAG_IS_UL> 103 <legal all> 104 */ 105 106 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 107 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 108 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 109 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 110 111 112 /* Description BSS_COLOR_ID 113 114 BSS color ID 115 116 Field used by MAC HW 117 <legal all> 118 */ 119 120 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 121 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 122 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 123 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 124 125 126 /* Description TXOP_DURATION 127 128 Indicates the remaining time in the current TXOP 129 130 Field used by MAC HW 131 <legal all> 132 */ 133 134 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 135 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 136 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 137 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 138 139 140 /* Description DISREGARD_0A 141 142 Set to value indicated in the trigger frame 143 <legal all> 144 */ 145 146 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 147 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 148 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 149 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 150 151 152 /* Description RESERVED_0C 153 154 <legal 0> 155 */ 156 157 #define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 158 #define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 159 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 160 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 161 162 163 /* Description EHT_PPDU_SIG_CMN_TYPE 164 165 <enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE 166 <enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both 167 EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) 168 169 <enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG 170 content channels 171 <enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG 172 content channel 173 <legal all> 174 */ 175 176 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 177 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 178 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 179 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 180 181 182 /* Description VALIDATE_1A 183 184 Set to value indicated in the trigger frame 185 <legal 1> 186 */ 187 188 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 189 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 190 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 191 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 192 193 194 /* Description SPATIAL_REUSE 195 196 TODO: Placeholder 197 <legal all> 198 */ 199 200 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 201 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 202 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 203 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 204 205 206 /* Description DISREGARD_1B 207 208 Set to value indicated in the trigger frame 209 <legal all> 210 */ 211 212 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 213 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 214 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 215 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 216 217 218 /* Description CRC 219 220 CRC for U-SIG contents 221 <legal all> 222 */ 223 224 #define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 225 #define U_SIG_EHT_TB_INFO_CRC_LSB 16 226 #define U_SIG_EHT_TB_INFO_CRC_MSB 19 227 #define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 228 229 230 /* Description TAIL 231 232 <legal 0> 233 */ 234 235 #define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 236 #define U_SIG_EHT_TB_INFO_TAIL_LSB 20 237 #define U_SIG_EHT_TB_INFO_TAIL_MSB 25 238 #define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 239 240 241 /* Description RESERVED_1C 242 243 <legal 0> 244 */ 245 246 #define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 247 #define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 248 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 249 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 250 251 252 /* Description RX_INTEGRITY_CHECK_PASSED 253 254 TX side: Set to 0 255 RX side: Set to 1 if PHY determines the U-SIG CRC check 256 has passed, else set to 0 257 258 <legal all> 259 */ 260 261 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 262 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 263 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 264 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 265 266 267 268 #endif // U_SIG_EHT_TB_INFO 269