1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 18*5113495bSYour Name #define _WBM2SW_COMPLETION_RING_RX_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #include "rx_msdu_desc_info.h" 23*5113495bSYour Name #include "rx_mpdu_desc_info.h" 24*5113495bSYour Name #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 25*5113495bSYour Name 26*5113495bSYour Name 27*5113495bSYour Name struct wbm2sw_completion_ring_rx { 28*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 30*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 31*5113495bSYour Name uint32_t release_source_module : 3, // [2:0] 32*5113495bSYour Name bm_action : 3, // [5:3] 33*5113495bSYour Name buffer_or_desc_type : 3, // [8:6] 34*5113495bSYour Name return_buffer_manager : 4, // [12:9] 35*5113495bSYour Name reserved_2a : 2, // [14:13] 36*5113495bSYour Name cache_id : 1, // [15:15] 37*5113495bSYour Name cookie_conversion_status : 1, // [16:16] 38*5113495bSYour Name rxdma_push_reason : 2, // [18:17] 39*5113495bSYour Name rxdma_error_code : 5, // [23:19] 40*5113495bSYour Name reo_push_reason : 2, // [25:24] 41*5113495bSYour Name reo_error_code : 5, // [30:26] 42*5113495bSYour Name wbm_internal_error : 1; // [31:31] 43*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 44*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 45*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 46*5113495bSYour Name uint32_t buffer_phys_addr_39_32 : 8, // [7:0] 47*5113495bSYour Name sw_buffer_cookie : 20, // [27:8] 48*5113495bSYour Name looping_count : 4; // [31:28] 49*5113495bSYour Name #else 50*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 51*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 52*5113495bSYour Name uint32_t wbm_internal_error : 1, // [31:31] 53*5113495bSYour Name reo_error_code : 5, // [30:26] 54*5113495bSYour Name reo_push_reason : 2, // [25:24] 55*5113495bSYour Name rxdma_error_code : 5, // [23:19] 56*5113495bSYour Name rxdma_push_reason : 2, // [18:17] 57*5113495bSYour Name cookie_conversion_status : 1, // [16:16] 58*5113495bSYour Name cache_id : 1, // [15:15] 59*5113495bSYour Name reserved_2a : 2, // [14:13] 60*5113495bSYour Name return_buffer_manager : 4, // [12:9] 61*5113495bSYour Name buffer_or_desc_type : 3, // [8:6] 62*5113495bSYour Name bm_action : 3, // [5:3] 63*5113495bSYour Name release_source_module : 3; // [2:0] 64*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 65*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 66*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 67*5113495bSYour Name uint32_t looping_count : 4, // [31:28] 68*5113495bSYour Name sw_buffer_cookie : 20, // [27:8] 69*5113495bSYour Name buffer_phys_addr_39_32 : 8; // [7:0] 70*5113495bSYour Name #endif 71*5113495bSYour Name }; 72*5113495bSYour Name 73*5113495bSYour Name 74*5113495bSYour Name /* Description BUFFER_VIRT_ADDR_31_0 75*5113495bSYour Name 76*5113495bSYour Name Lower 32 bits of the 64-bit virtual address corresponding 77*5113495bSYour Name to the MSDU being released 78*5113495bSYour Name <legal all> 79*5113495bSYour Name */ 80*5113495bSYour Name 81*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 82*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 83*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 84*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 85*5113495bSYour Name 86*5113495bSYour Name 87*5113495bSYour Name /* Description BUFFER_VIRT_ADDR_63_32 88*5113495bSYour Name 89*5113495bSYour Name Upper 32 bits of the 64-bit virtual address corresponding 90*5113495bSYour Name to the MSDU being released 91*5113495bSYour Name <legal all> 92*5113495bSYour Name */ 93*5113495bSYour Name 94*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 95*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 96*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 97*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name /* Description RELEASE_SOURCE_MODULE 101*5113495bSYour Name 102*5113495bSYour Name Indicates which module initiated the release of this buffer 103*5113495bSYour Name or descriptor 104*5113495bSYour Name 105*5113495bSYour Name <enum 1 release_source_RXDMA> RXDMA released this buffer 106*5113495bSYour Name or descriptor 107*5113495bSYour Name <enum 2 release_source_REO> REO released this buffer or 108*5113495bSYour Name descriptor 109*5113495bSYour Name <enum 5 release_source_FW_RX> FW released this buffer or 110*5113495bSYour Name descriptor 111*5113495bSYour Name <enum 4 release_source_SW_RX> SW released this buffer or 112*5113495bSYour Name descriptor 113*5113495bSYour Name <enum 0 release_source_TQM> DO NOT USE 114*5113495bSYour Name <enum 3 release_source_FW_TX> DO NOT USE 115*5113495bSYour Name <enum 6 release_source_SW_TX> DO NOT USE 116*5113495bSYour Name <legal 0-6> 117*5113495bSYour Name */ 118*5113495bSYour Name 119*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 120*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 121*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 122*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 123*5113495bSYour Name 124*5113495bSYour Name 125*5113495bSYour Name /* Description BM_ACTION 126*5113495bSYour Name 127*5113495bSYour Name Consumer: WBM/SW/FW 128*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 129*5113495bSYour Name 130*5113495bSYour Name Field only valid when the field return_buffer_manager in 131*5113495bSYour Name the Released_buff_or_desc_addr_info indicates: 132*5113495bSYour Name WBM_IDLE_BUF_LIST or 133*5113495bSYour Name WBM_IDLE_DESC_LIST 134*5113495bSYour Name 135*5113495bSYour Name An MSDU extension descriptor shall never be marked as WBM 136*5113495bSYour Name being the 'owner', and thus WBM will forward it to FW/SW 137*5113495bSYour Name 138*5113495bSYour Name 139*5113495bSYour Name <enum 0 Put_in_idle_list> Put the buffer or descriptor back 140*5113495bSYour Name in the idle list. In case of MSDU or MDPU link descriptor, 141*5113495bSYour Name BM does not need to check to release any individual MSDU 142*5113495bSYour Name buffers 143*5113495bSYour Name 144*5113495bSYour Name <enum 1 release_msdu_list > This BM action can only be used 145*5113495bSYour Name in combination with buffer_or_desc_type being msdu_link_descriptor. 146*5113495bSYour Name Field first_msdu_index points out which MSDU pointer in 147*5113495bSYour Name the MSDU link descriptor is the first of an MPDU that is 148*5113495bSYour Name released. 149*5113495bSYour Name BM shall release all the MSDU buffers linked to this first 150*5113495bSYour Name MSDU buffer pointer. All related MSDU buffer pointer entries 151*5113495bSYour Name shall be set to value 0, which represents the 'NULL" pointer. 152*5113495bSYour Name When all MSDU buffer pointers in the MSDU link descriptor 153*5113495bSYour Name are 'NULL', the MSDU link descriptor itself shall also 154*5113495bSYour Name be released. 155*5113495bSYour Name 156*5113495bSYour Name <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 157*5113495bSYour Name 158*5113495bSYour Name Put the buffer or descriptor back in the idle list. Only 159*5113495bSYour Name valid in combination with buffer_or_desc_type indicating 160*5113495bSYour Name MDPU_link_descriptor. 161*5113495bSYour Name BM shall release the MPDU link descriptor as well as all 162*5113495bSYour Name MSDUs that are linked to the MPDUs in this descriptor. 163*5113495bSYour Name 164*5113495bSYour Name 165*5113495bSYour Name TODO: Any restrictions? 166*5113495bSYour Name <legal 0-2> 167*5113495bSYour Name */ 168*5113495bSYour Name 169*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 170*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 171*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 172*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 173*5113495bSYour Name 174*5113495bSYour Name 175*5113495bSYour Name /* Description BUFFER_OR_DESC_TYPE 176*5113495bSYour Name 177*5113495bSYour Name Consumer: WBM/SW/FW 178*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 179*5113495bSYour Name 180*5113495bSYour Name Field only valid when WBM is marked as the return_buffer_manager 181*5113495bSYour Name in the Released_Buffer_address_info 182*5113495bSYour Name 183*5113495bSYour Name Indicates that type of buffer or descriptor is being released 184*5113495bSYour Name 185*5113495bSYour Name 186*5113495bSYour Name <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 187*5113495bSYour Name 188*5113495bSYour Name <enum 1 msdu_link_descriptor> The address points to an TX 189*5113495bSYour Name MSDU link descriptor 190*5113495bSYour Name <enum 2 mpdu_link_descriptor> The address points to an MPDU 191*5113495bSYour Name link descriptor 192*5113495bSYour Name <enum 3 msdu_ext_descriptor > The address points to an MSDU 193*5113495bSYour Name extension descriptor. 194*5113495bSYour Name In case BM finds this one in a release ring, it passes it 195*5113495bSYour Name on to FW... 196*5113495bSYour Name <enum 4 queue_ext_descriptor> The address points to an TQM 197*5113495bSYour Name queue extension descriptor. WBM should treat this is the 198*5113495bSYour Name same way as a link descriptor. That is, put the 128 byte 199*5113495bSYour Name buffer back in the link buffer idle list. 200*5113495bSYour Name 201*5113495bSYour Name TODO: Any restrictions? 202*5113495bSYour Name <legal 0-4> 203*5113495bSYour Name */ 204*5113495bSYour Name 205*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 206*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 207*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 208*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 209*5113495bSYour Name 210*5113495bSYour Name 211*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 212*5113495bSYour Name 213*5113495bSYour Name 'Return_buffer_manager' field of the MSDU's buffer address 214*5113495bSYour Name info, for debug 215*5113495bSYour Name */ 216*5113495bSYour Name 217*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 218*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 219*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 220*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 221*5113495bSYour Name 222*5113495bSYour Name 223*5113495bSYour Name /* Description RESERVED_2A 224*5113495bSYour Name 225*5113495bSYour Name <legal 0> 226*5113495bSYour Name */ 227*5113495bSYour Name 228*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 229*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 230*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 231*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 232*5113495bSYour Name 233*5113495bSYour Name 234*5113495bSYour Name /* Description CACHE_ID 235*5113495bSYour Name 236*5113495bSYour Name Indicates the WBM cache the MSDU was released from 237*5113495bSYour Name <legal all> 238*5113495bSYour Name */ 239*5113495bSYour Name 240*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 241*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 242*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 243*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 244*5113495bSYour Name 245*5113495bSYour Name 246*5113495bSYour Name /* Description COOKIE_CONVERSION_STATUS 247*5113495bSYour Name 248*5113495bSYour Name 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 249*5113495bSYour Name 250*5113495bSYour Name 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 251*5113495bSYour Name <legal 1> 252*5113495bSYour Name */ 253*5113495bSYour Name 254*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 255*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 256*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 257*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 258*5113495bSYour Name 259*5113495bSYour Name 260*5113495bSYour Name /* Description RXDMA_PUSH_REASON 261*5113495bSYour Name 262*5113495bSYour Name Field only valid when Release_source_module is set to release_source_RXDMA 263*5113495bSYour Name 264*5113495bSYour Name 265*5113495bSYour Name Indicates why rxdma pushed the frame to this ring 266*5113495bSYour Name 267*5113495bSYour Name <enum 0 rxdma_error_detected> RXDMA detected an error an 268*5113495bSYour Name pushed this frame to this queue 269*5113495bSYour Name <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 270*5113495bSYour Name to this queue per received routing instructions. No error 271*5113495bSYour Name within RXDMA was detected 272*5113495bSYour Name <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 273*5113495bSYour Name result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 274*5113495bSYour Name set, but instead WBM might just see a NULL pointer in the 275*5113495bSYour Name MSDU link descriptor. This is to be considered a normal 276*5113495bSYour Name condition for this scenario. 277*5113495bSYour Name 278*5113495bSYour Name <legal 0 - 2> 279*5113495bSYour Name */ 280*5113495bSYour Name 281*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 282*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 283*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 284*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 285*5113495bSYour Name 286*5113495bSYour Name 287*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 288*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 289*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 290*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 291*5113495bSYour Name 292*5113495bSYour Name 293*5113495bSYour Name /* Description REO_PUSH_REASON 294*5113495bSYour Name 295*5113495bSYour Name Field only valid when Release_source_module is set to release_source_REO 296*5113495bSYour Name 297*5113495bSYour Name 298*5113495bSYour Name Indicates why REO pushed the frame to this release ring 299*5113495bSYour Name 300*5113495bSYour Name <enum 0 reo_error_detected> Reo detected an error an pushed 301*5113495bSYour Name this frame to this queue 302*5113495bSYour Name <enum 1 reo_routing_instruction> Reo pushed the frame to 303*5113495bSYour Name this queue per received routing instructions. No error 304*5113495bSYour Name within REO was detected 305*5113495bSYour Name 306*5113495bSYour Name <legal 0 - 1> 307*5113495bSYour Name */ 308*5113495bSYour Name 309*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 310*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 311*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 312*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 313*5113495bSYour Name 314*5113495bSYour Name 315*5113495bSYour Name /* Description REO_ERROR_CODE 316*5113495bSYour Name 317*5113495bSYour Name Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 318*5113495bSYour Name 319*5113495bSYour Name 320*5113495bSYour Name <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 321*5113495bSYour Name in the REO_ENTRANCE ring is set to 0 322*5113495bSYour Name <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 323*5113495bSYour Name bit is NOT set 324*5113495bSYour Name <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 325*5113495bSYour Name session having been setup. 326*5113495bSYour Name <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 327*5113495bSYour Name Retry bit set: duplicate frame 328*5113495bSYour Name <enum 4 ba_duplicate> BA session, duplicate frame 329*5113495bSYour Name <enum 5 regular_frame_2k_jump> A normal (management/data 330*5113495bSYour Name frame) received with 2K jump in SN 331*5113495bSYour Name <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 332*5113495bSYour Name SSN 333*5113495bSYour Name <enum 7 regular_frame_OOR> A normal (management/data frame) 334*5113495bSYour Name received with SN falling within the OOR window 335*5113495bSYour Name <enum 8 bar_frame_OOR> A bar received with SSN falling within 336*5113495bSYour Name the OOR window 337*5113495bSYour Name <enum 9 bar_frame_no_ba_session> A bar received without 338*5113495bSYour Name a BA session 339*5113495bSYour Name <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 340*5113495bSYour Name equal to SN 341*5113495bSYour Name <enum 11 pn_check_failed> PN Check Failed packet. 342*5113495bSYour Name <enum 12 2k_error_handling_flag_set> Frame is forwarded 343*5113495bSYour Name as a result of the 'Seq_2k_error_detected_flag' been set 344*5113495bSYour Name in the REO Queue descriptor 345*5113495bSYour Name <enum 13 pn_error_handling_flag_set> Frame is forwarded 346*5113495bSYour Name as a result of the 'pn_error_detected_flag' been set in 347*5113495bSYour Name the REO Queue descriptor 348*5113495bSYour Name <enum 14 queue_descriptor_blocked_set> Frame is forwarded 349*5113495bSYour Name as a result of the queue descriptor(address) being blocked 350*5113495bSYour Name as SW/FW seems to be currently in the process of making 351*5113495bSYour Name updates to this descriptor... 352*5113495bSYour Name 353*5113495bSYour Name <legal 0-14> 354*5113495bSYour Name */ 355*5113495bSYour Name 356*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 357*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 358*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 359*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 360*5113495bSYour Name 361*5113495bSYour Name 362*5113495bSYour Name /* Description WBM_INTERNAL_ERROR 363*5113495bSYour Name 364*5113495bSYour Name Can only be set by WBM. 365*5113495bSYour Name 366*5113495bSYour Name Is set when WBM got a buffer pointer but the action was 367*5113495bSYour Name to push it to the idle link descriptor ring or do link related 368*5113495bSYour Name activity 369*5113495bSYour Name OR 370*5113495bSYour Name Is set when WBM got a link buffer pointer but the action 371*5113495bSYour Name was to push it to the buffer descriptor ring 372*5113495bSYour Name 373*5113495bSYour Name <legal all> 374*5113495bSYour Name */ 375*5113495bSYour Name 376*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 377*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 378*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 379*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 380*5113495bSYour Name 381*5113495bSYour Name 382*5113495bSYour Name /* Description RX_MPDU_DESC_INFO_DETAILS 383*5113495bSYour Name 384*5113495bSYour Name Consumer: REO/SW/FW 385*5113495bSYour Name Producer: RXDMA 386*5113495bSYour Name 387*5113495bSYour Name General information related to the MPDU whose link descriptors 388*5113495bSYour Name are being released from Rx DMA or REO 389*5113495bSYour Name */ 390*5113495bSYour Name 391*5113495bSYour Name 392*5113495bSYour Name /* Description MSDU_COUNT 393*5113495bSYour Name 394*5113495bSYour Name Consumer: REO/SW/FW 395*5113495bSYour Name Producer: RXDMA 396*5113495bSYour Name 397*5113495bSYour Name The number of MSDUs within the MPDU 398*5113495bSYour Name <legal all> 399*5113495bSYour Name */ 400*5113495bSYour Name 401*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 402*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 403*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 404*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 405*5113495bSYour Name 406*5113495bSYour Name 407*5113495bSYour Name /* Description FRAGMENT_FLAG 408*5113495bSYour Name 409*5113495bSYour Name Consumer: REO/SW/FW 410*5113495bSYour Name Producer: RXDMA 411*5113495bSYour Name 412*5113495bSYour Name When set, this MPDU is a fragment and REO should forward 413*5113495bSYour Name this fragment MPDU to the REO destination ring without 414*5113495bSYour Name any reorder checks, pn checks or bitmap update. This implies 415*5113495bSYour Name that REO is forwarding the pointer to the MSDU link descriptor. 416*5113495bSYour Name The destination ring is coming from a programmable register 417*5113495bSYour Name setting in REO 418*5113495bSYour Name 419*5113495bSYour Name <legal all> 420*5113495bSYour Name */ 421*5113495bSYour Name 422*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 423*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 424*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 425*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 426*5113495bSYour Name 427*5113495bSYour Name 428*5113495bSYour Name /* Description MPDU_RETRY_BIT 429*5113495bSYour Name 430*5113495bSYour Name Consumer: REO/SW/FW 431*5113495bSYour Name Producer: RXDMA 432*5113495bSYour Name 433*5113495bSYour Name The retry bit setting from the MPDU header of the received 434*5113495bSYour Name frame 435*5113495bSYour Name <legal all> 436*5113495bSYour Name */ 437*5113495bSYour Name 438*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 439*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 440*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 441*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 442*5113495bSYour Name 443*5113495bSYour Name 444*5113495bSYour Name /* Description AMPDU_FLAG 445*5113495bSYour Name 446*5113495bSYour Name Consumer: REO/SW/FW 447*5113495bSYour Name Producer: RXDMA 448*5113495bSYour Name 449*5113495bSYour Name When set, the MPDU was received as part of an A-MPDU. 450*5113495bSYour Name <legal all> 451*5113495bSYour Name */ 452*5113495bSYour Name 453*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 454*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 455*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 456*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 457*5113495bSYour Name 458*5113495bSYour Name 459*5113495bSYour Name /* Description BAR_FRAME 460*5113495bSYour Name 461*5113495bSYour Name Consumer: REO/SW/FW 462*5113495bSYour Name Producer: RXDMA 463*5113495bSYour Name 464*5113495bSYour Name When set, the received frame is a BAR frame. After processing, 465*5113495bSYour Name this frame shall be pushed to SW or deleted. 466*5113495bSYour Name <legal all> 467*5113495bSYour Name */ 468*5113495bSYour Name 469*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 470*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 471*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 472*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 473*5113495bSYour Name 474*5113495bSYour Name 475*5113495bSYour Name /* Description PN_FIELDS_CONTAIN_VALID_INFO 476*5113495bSYour Name 477*5113495bSYour Name Consumer: REO/SW/FW 478*5113495bSYour Name Producer: RXDMA 479*5113495bSYour Name 480*5113495bSYour Name Copied here by RXDMA from RX_MPDU_END 481*5113495bSYour Name When not set, REO will Not perform a PN sequence number 482*5113495bSYour Name check 483*5113495bSYour Name */ 484*5113495bSYour Name 485*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 486*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 487*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 488*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 489*5113495bSYour Name 490*5113495bSYour Name 491*5113495bSYour Name /* Description RAW_MPDU 492*5113495bSYour Name 493*5113495bSYour Name Field only valid when first_msdu_in_mpdu_flag is set. 494*5113495bSYour Name 495*5113495bSYour Name When set, the contents in the MSDU buffer contains a 'RAW' 496*5113495bSYour Name MPDU. This 'RAW' MPDU might be spread out over multiple 497*5113495bSYour Name MSDU buffers. 498*5113495bSYour Name <legal all> 499*5113495bSYour Name */ 500*5113495bSYour Name 501*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 502*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 503*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 504*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 505*5113495bSYour Name 506*5113495bSYour Name 507*5113495bSYour Name /* Description MORE_FRAGMENT_FLAG 508*5113495bSYour Name 509*5113495bSYour Name The More Fragment bit setting from the MPDU header of the 510*5113495bSYour Name received frame 511*5113495bSYour Name 512*5113495bSYour Name <legal all> 513*5113495bSYour Name */ 514*5113495bSYour Name 515*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 516*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 517*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 518*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 519*5113495bSYour Name 520*5113495bSYour Name 521*5113495bSYour Name /* Description SRC_INFO 522*5113495bSYour Name 523*5113495bSYour Name Source (virtual) device/interface info. associated with 524*5113495bSYour Name this peer 525*5113495bSYour Name 526*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 527*5113495bSYour Name ('REO_TO_PPE_RING'). 528*5113495bSYour Name 529*5113495bSYour Name <legal all> 530*5113495bSYour Name */ 531*5113495bSYour Name 532*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 533*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 534*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 535*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 536*5113495bSYour Name 537*5113495bSYour Name 538*5113495bSYour Name /* Description MPDU_QOS_CONTROL_VALID 539*5113495bSYour Name 540*5113495bSYour Name When set, the MPDU has a QoS control field. 541*5113495bSYour Name 542*5113495bSYour Name In case of ndp or phy_err, this field will never be set. 543*5113495bSYour Name 544*5113495bSYour Name <legal all> 545*5113495bSYour Name */ 546*5113495bSYour Name 547*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 548*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 549*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 550*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 551*5113495bSYour Name 552*5113495bSYour Name 553*5113495bSYour Name /* Description TID 554*5113495bSYour Name 555*5113495bSYour Name Field only valid when mpdu_qos_control_valid is set 556*5113495bSYour Name 557*5113495bSYour Name The TID field in the QoS control field 558*5113495bSYour Name <legal all> 559*5113495bSYour Name */ 560*5113495bSYour Name 561*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 562*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 563*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 564*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 565*5113495bSYour Name 566*5113495bSYour Name 567*5113495bSYour Name /* Description PEER_META_DATA 568*5113495bSYour Name 569*5113495bSYour Name Meta data that SW has programmed in the Peer table entry 570*5113495bSYour Name of the transmitting STA. 571*5113495bSYour Name <legal all> 572*5113495bSYour Name */ 573*5113495bSYour Name 574*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 575*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 576*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 577*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 578*5113495bSYour Name 579*5113495bSYour Name 580*5113495bSYour Name /* Description RX_MSDU_DESC_INFO_DETAILS 581*5113495bSYour Name 582*5113495bSYour Name Consumer: TQM/SW 583*5113495bSYour Name Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 584*5113495bSYour Name 585*5113495bSYour Name In case of RXDMA or REO releasing Rx MSDU link descriptors,' 586*5113495bSYour Name WBM fills this field with Rx_msdu_desc_info_details when 587*5113495bSYour Name releasing the MSDUs to SW. 588*5113495bSYour Name */ 589*5113495bSYour Name 590*5113495bSYour Name 591*5113495bSYour Name /* Description FIRST_MSDU_IN_MPDU_FLAG 592*5113495bSYour Name 593*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 594*5113495bSYour Name multiple buffers, this field will be valid in the Last 595*5113495bSYour Name buffer used by the MSDU 596*5113495bSYour Name 597*5113495bSYour Name <enum 0 Not_first_msdu> This is not the first MSDU in the 598*5113495bSYour Name MPDU. 599*5113495bSYour Name <enum 1 first_msdu> This MSDU is the first one in the MPDU. 600*5113495bSYour Name 601*5113495bSYour Name 602*5113495bSYour Name <legal all> 603*5113495bSYour Name */ 604*5113495bSYour Name 605*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 606*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 607*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 608*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 609*5113495bSYour Name 610*5113495bSYour Name 611*5113495bSYour Name /* Description LAST_MSDU_IN_MPDU_FLAG 612*5113495bSYour Name 613*5113495bSYour Name Consumer: WBM/REO/SW/FW 614*5113495bSYour Name Producer: RXDMA 615*5113495bSYour Name 616*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 617*5113495bSYour Name multiple buffers, this field will be valid in the Last 618*5113495bSYour Name buffer used by the MSDU 619*5113495bSYour Name 620*5113495bSYour Name <enum 0 Not_last_msdu> There are more MSDUs linked to this 621*5113495bSYour Name MSDU that belongs to this MPDU 622*5113495bSYour Name <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 623*5113495bSYour Name This setting is only allowed in combination with 'Msdu_continuation' 624*5113495bSYour Name set to 0. This implies that when an msdu is spread out over 625*5113495bSYour Name multiple buffers and thus msdu_continuation is set, only 626*5113495bSYour Name for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 627*5113495bSYour Name be set. 628*5113495bSYour Name 629*5113495bSYour Name When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 630*5113495bSYour Name are set, the MPDU that this MSDU belongs to only contains 631*5113495bSYour Name a single MSDU. 632*5113495bSYour Name 633*5113495bSYour Name 634*5113495bSYour Name <legal all> 635*5113495bSYour Name */ 636*5113495bSYour Name 637*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 638*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 639*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 640*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 641*5113495bSYour Name 642*5113495bSYour Name 643*5113495bSYour Name /* Description MSDU_CONTINUATION 644*5113495bSYour Name 645*5113495bSYour Name When set, this MSDU buffer was not able to hold the entire 646*5113495bSYour Name MSDU. The next buffer will therefor contain additional 647*5113495bSYour Name information related to this MSDU. 648*5113495bSYour Name 649*5113495bSYour Name <legal all> 650*5113495bSYour Name */ 651*5113495bSYour Name 652*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 653*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 654*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 655*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 656*5113495bSYour Name 657*5113495bSYour Name 658*5113495bSYour Name /* Description MSDU_LENGTH 659*5113495bSYour Name 660*5113495bSYour Name Parsed from RX_MSDU_START TLV . In the case MSDU spans over 661*5113495bSYour Name multiple buffers, this field will be valid in the First 662*5113495bSYour Name buffer used by MSDU. 663*5113495bSYour Name 664*5113495bSYour Name Full MSDU length in bytes after decapsulation. 665*5113495bSYour Name 666*5113495bSYour Name This field is still valid for MPDU frames without A-MSDU. 667*5113495bSYour Name It still represents MSDU length after decapsulation 668*5113495bSYour Name 669*5113495bSYour Name Or in case of RAW MPDUs, it indicates the length of the 670*5113495bSYour Name entire MPDU (without FCS field) 671*5113495bSYour Name <legal all> 672*5113495bSYour Name */ 673*5113495bSYour Name 674*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 675*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 676*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 677*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 678*5113495bSYour Name 679*5113495bSYour Name 680*5113495bSYour Name /* Description MSDU_DROP 681*5113495bSYour Name 682*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 683*5113495bSYour Name multiple buffers, this field will be valid in the Last 684*5113495bSYour Name buffer used by the MSDU 685*5113495bSYour Name 686*5113495bSYour Name When set, REO shall drop this MSDU and not forward it to 687*5113495bSYour Name any other ring... 688*5113495bSYour Name <legal all> 689*5113495bSYour Name */ 690*5113495bSYour Name 691*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 692*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 693*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 694*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 695*5113495bSYour Name 696*5113495bSYour Name 697*5113495bSYour Name /* Description SA_IS_VALID 698*5113495bSYour Name 699*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 700*5113495bSYour Name multiple buffers, this field will be valid in the Last 701*5113495bSYour Name buffer used by the MSDU 702*5113495bSYour Name 703*5113495bSYour Name Indicates that OLE found a valid SA entry for this MSDU 704*5113495bSYour Name <legal all> 705*5113495bSYour Name */ 706*5113495bSYour Name 707*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 708*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 709*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 710*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 711*5113495bSYour Name 712*5113495bSYour Name 713*5113495bSYour Name /* Description DA_IS_VALID 714*5113495bSYour Name 715*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 716*5113495bSYour Name multiple buffers, this field will be valid in the Last 717*5113495bSYour Name buffer used by the MSDU 718*5113495bSYour Name 719*5113495bSYour Name Indicates that OLE found a valid DA entry for this MSDU 720*5113495bSYour Name <legal all> 721*5113495bSYour Name */ 722*5113495bSYour Name 723*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 724*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 725*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 726*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 727*5113495bSYour Name 728*5113495bSYour Name 729*5113495bSYour Name /* Description DA_IS_MCBC 730*5113495bSYour Name 731*5113495bSYour Name Field Only valid if "da_is_valid" is set 732*5113495bSYour Name 733*5113495bSYour Name Indicates the DA address was a Multicast of Broadcast address 734*5113495bSYour Name for this MSDU 735*5113495bSYour Name <legal all> 736*5113495bSYour Name */ 737*5113495bSYour Name 738*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 739*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 740*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 741*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 742*5113495bSYour Name 743*5113495bSYour Name 744*5113495bSYour Name /* Description L3_HEADER_PADDING_MSB 745*5113495bSYour Name 746*5113495bSYour Name Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 747*5113495bSYour Name as the LSB is always zero) 748*5113495bSYour Name Number of bytes padded to make sure that the L3 header will 749*5113495bSYour Name always start of a Dword boundary 750*5113495bSYour Name <legal all> 751*5113495bSYour Name */ 752*5113495bSYour Name 753*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 754*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 755*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 756*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 757*5113495bSYour Name 758*5113495bSYour Name 759*5113495bSYour Name /* Description TCP_UDP_CHKSUM_FAIL 760*5113495bSYour Name 761*5113495bSYour Name Passed on from 'RX_ATTENTION' TLV 762*5113495bSYour Name Indicates that the computed checksum did not match the checksum 763*5113495bSYour Name in the TCP/UDP header. 764*5113495bSYour Name <legal all> 765*5113495bSYour Name */ 766*5113495bSYour Name 767*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 768*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 769*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 770*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 771*5113495bSYour Name 772*5113495bSYour Name 773*5113495bSYour Name /* Description IP_CHKSUM_FAIL 774*5113495bSYour Name 775*5113495bSYour Name Passed on from 'RX_ATTENTION' TLV 776*5113495bSYour Name Indicates that the computed checksum did not match the checksum 777*5113495bSYour Name in the IP header. 778*5113495bSYour Name <legal all> 779*5113495bSYour Name */ 780*5113495bSYour Name 781*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 782*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 783*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 784*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 785*5113495bSYour Name 786*5113495bSYour Name 787*5113495bSYour Name /* Description FR_DS 788*5113495bSYour Name 789*5113495bSYour Name Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 790*5113495bSYour Name TLV 791*5113495bSYour Name Set if the 'from DS' bit is set in the frame control. 792*5113495bSYour Name <legal all> 793*5113495bSYour Name */ 794*5113495bSYour Name 795*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 796*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 797*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 798*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 799*5113495bSYour Name 800*5113495bSYour Name 801*5113495bSYour Name /* Description TO_DS 802*5113495bSYour Name 803*5113495bSYour Name Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 804*5113495bSYour Name TLV 805*5113495bSYour Name Set if the 'to DS' bit is set in the frame control. 806*5113495bSYour Name <legal all> 807*5113495bSYour Name */ 808*5113495bSYour Name 809*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 810*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 811*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 812*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 813*5113495bSYour Name 814*5113495bSYour Name 815*5113495bSYour Name /* Description INTRA_BSS 816*5113495bSYour Name 817*5113495bSYour Name This packet needs intra-BSS routing by SW as the 'vdev_id' 818*5113495bSYour Name for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 819*5113495bSYour Name that this MSDU was got in. 820*5113495bSYour Name 821*5113495bSYour Name <legal all> 822*5113495bSYour Name */ 823*5113495bSYour Name 824*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 825*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 826*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 827*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 828*5113495bSYour Name 829*5113495bSYour Name 830*5113495bSYour Name /* Description DEST_CHIP_ID 831*5113495bSYour Name 832*5113495bSYour Name If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 833*5113495bSYour Name to support intra-BSS routing with multi-chip multi-link 834*5113495bSYour Name operation. 835*5113495bSYour Name 836*5113495bSYour Name This indicates into which chip's TCL the packet should be 837*5113495bSYour Name queued. 838*5113495bSYour Name 839*5113495bSYour Name <legal all> 840*5113495bSYour Name */ 841*5113495bSYour Name 842*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 843*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 844*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 845*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 846*5113495bSYour Name 847*5113495bSYour Name 848*5113495bSYour Name /* Description DECAP_FORMAT 849*5113495bSYour Name 850*5113495bSYour Name Indicates the format after decapsulation: 851*5113495bSYour Name 852*5113495bSYour Name <enum 0 RAW> No encapsulation 853*5113495bSYour Name <enum 1 Native_WiFi> 854*5113495bSYour Name <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 855*5113495bSYour Name 856*5113495bSYour Name <enum 3 802_3> Indicate Ethernet 857*5113495bSYour Name 858*5113495bSYour Name <legal all> 859*5113495bSYour Name */ 860*5113495bSYour Name 861*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 862*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 863*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 864*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 865*5113495bSYour Name 866*5113495bSYour Name 867*5113495bSYour Name /* Description DEST_CHIP_PMAC_ID 868*5113495bSYour Name 869*5113495bSYour Name If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 870*5113495bSYour Name to support intra-BSS routing with multi-chip multi-link 871*5113495bSYour Name operation. 872*5113495bSYour Name 873*5113495bSYour Name This indicates into which link/'vdev' the packet should 874*5113495bSYour Name be queued in TCL. 875*5113495bSYour Name 876*5113495bSYour Name <legal all> 877*5113495bSYour Name */ 878*5113495bSYour Name 879*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 880*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 881*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 882*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 883*5113495bSYour Name 884*5113495bSYour Name 885*5113495bSYour Name /* Description BUFFER_PHYS_ADDR_31_0 886*5113495bSYour Name 887*5113495bSYour Name LSB 32 bits of the physical address from the MSDU's buffer 888*5113495bSYour Name address info, for debug 889*5113495bSYour Name */ 890*5113495bSYour Name 891*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 892*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 893*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 894*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 895*5113495bSYour Name 896*5113495bSYour Name 897*5113495bSYour Name /* Description BUFFER_PHYS_ADDR_39_32 898*5113495bSYour Name 899*5113495bSYour Name MSB 8 bits of the physical address from the MSDU's buffer 900*5113495bSYour Name address info, for debug 901*5113495bSYour Name */ 902*5113495bSYour Name 903*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 904*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 905*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 906*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 907*5113495bSYour Name 908*5113495bSYour Name 909*5113495bSYour Name /* Description SW_BUFFER_COOKIE 910*5113495bSYour Name 911*5113495bSYour Name 'Sw_buffer_cookie' field of the MSDU's buffer address info 912*5113495bSYour Name used to fill 'Buffer_virt_addr_*,' for debug 913*5113495bSYour Name 914*5113495bSYour Name For further debugging, if enabled, WBM may fill the Rx MPDU 915*5113495bSYour Name sequence number in bits [27:16] (copying from field Reserved_7a 916*5113495bSYour Name in 'WBM_RELEASE_RING_RX'). 917*5113495bSYour Name 918*5113495bSYour Name */ 919*5113495bSYour Name 920*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 921*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 922*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 923*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 924*5113495bSYour Name 925*5113495bSYour Name 926*5113495bSYour Name /* Description LOOPING_COUNT 927*5113495bSYour Name 928*5113495bSYour Name Consumer: WBM/SW/FW 929*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 930*5113495bSYour Name 931*5113495bSYour Name If WBM_internal_error is set, this descriptor is sent to 932*5113495bSYour Name the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 933*5113495bSYour Name is used to indicate an error code. 934*5113495bSYour Name 935*5113495bSYour Name The values reported are documented further in the WBM MLD 936*5113495bSYour Name doc. 937*5113495bSYour Name 938*5113495bSYour Name If WBM_internal_error is not set, the following holds. 939*5113495bSYour Name 940*5113495bSYour Name A count value that indicates the number of times the producer 941*5113495bSYour Name of entries into the Buffer Manager Ring has looped around 942*5113495bSYour Name the ring. 943*5113495bSYour Name At initialization time, this value is set to 0. On the first 944*5113495bSYour Name loop, this value is set to 1. After the max value is reached 945*5113495bSYour Name allowed by the number of bits for this field, the count 946*5113495bSYour Name value continues with 0 again. 947*5113495bSYour Name 948*5113495bSYour Name In case SW is the consumer of the ring entries, it can use 949*5113495bSYour Name this field to figure out up to where the producer of entries 950*5113495bSYour Name has created new entries. This eliminates the need to check 951*5113495bSYour Name where the "head pointer' of the ring is located once the 952*5113495bSYour Name SW starts processing an interrupt indicating that new entries 953*5113495bSYour Name have been put into this ring... 954*5113495bSYour Name 955*5113495bSYour Name Also note that SW if it wants only needs to look at the 956*5113495bSYour Name LSB bit of this count value. 957*5113495bSYour Name <legal all> 958*5113495bSYour Name */ 959*5113495bSYour Name 960*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 961*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 962*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 963*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 964*5113495bSYour Name 965*5113495bSYour Name 966*5113495bSYour Name 967*5113495bSYour Name #endif // WBM2SW_COMPLETION_RING_RX 968