1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 18 #define _WBM2SW_COMPLETION_RING_RX_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_msdu_desc_info.h" 23 #include "rx_mpdu_desc_info.h" 24 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 25 26 27 struct wbm2sw_completion_ring_rx { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 30 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 31 uint32_t release_source_module : 3, // [2:0] 32 bm_action : 3, // [5:3] 33 buffer_or_desc_type : 3, // [8:6] 34 return_buffer_manager : 4, // [12:9] 35 reserved_2a : 2, // [14:13] 36 cache_id : 1, // [15:15] 37 cookie_conversion_status : 1, // [16:16] 38 rxdma_push_reason : 2, // [18:17] 39 rxdma_error_code : 5, // [23:19] 40 reo_push_reason : 2, // [25:24] 41 reo_error_code : 5, // [30:26] 42 wbm_internal_error : 1; // [31:31] 43 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 44 struct rx_msdu_desc_info rx_msdu_desc_info_details; 45 uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 46 uint32_t buffer_phys_addr_39_32 : 8, // [7:0] 47 sw_buffer_cookie : 20, // [27:8] 48 looping_count : 4; // [31:28] 49 #else 50 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 51 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 52 uint32_t wbm_internal_error : 1, // [31:31] 53 reo_error_code : 5, // [30:26] 54 reo_push_reason : 2, // [25:24] 55 rxdma_error_code : 5, // [23:19] 56 rxdma_push_reason : 2, // [18:17] 57 cookie_conversion_status : 1, // [16:16] 58 cache_id : 1, // [15:15] 59 reserved_2a : 2, // [14:13] 60 return_buffer_manager : 4, // [12:9] 61 buffer_or_desc_type : 3, // [8:6] 62 bm_action : 3, // [5:3] 63 release_source_module : 3; // [2:0] 64 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 65 struct rx_msdu_desc_info rx_msdu_desc_info_details; 66 uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 67 uint32_t looping_count : 4, // [31:28] 68 sw_buffer_cookie : 20, // [27:8] 69 buffer_phys_addr_39_32 : 8; // [7:0] 70 #endif 71 }; 72 73 74 /* Description BUFFER_VIRT_ADDR_31_0 75 76 Lower 32 bits of the 64-bit virtual address corresponding 77 to the MSDU being released 78 <legal all> 79 */ 80 81 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 82 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 83 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 84 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 85 86 87 /* Description BUFFER_VIRT_ADDR_63_32 88 89 Upper 32 bits of the 64-bit virtual address corresponding 90 to the MSDU being released 91 <legal all> 92 */ 93 94 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 95 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 96 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 97 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 98 99 100 /* Description RELEASE_SOURCE_MODULE 101 102 Indicates which module initiated the release of this buffer 103 or descriptor 104 105 <enum 1 release_source_RXDMA> RXDMA released this buffer 106 or descriptor 107 <enum 2 release_source_REO> REO released this buffer or 108 descriptor 109 <enum 5 release_source_FW_RX> FW released this buffer or 110 descriptor 111 <enum 4 release_source_SW_RX> SW released this buffer or 112 descriptor 113 <enum 0 release_source_TQM> DO NOT USE 114 <enum 3 release_source_FW_TX> DO NOT USE 115 <enum 6 release_source_SW_TX> DO NOT USE 116 <legal 0-6> 117 */ 118 119 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 120 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 121 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 122 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 123 124 125 /* Description BM_ACTION 126 127 Consumer: WBM/SW/FW 128 Producer: SW/TQM/RXDMA/REO/SWITCH 129 130 Field only valid when the field return_buffer_manager in 131 the Released_buff_or_desc_addr_info indicates: 132 WBM_IDLE_BUF_LIST or 133 WBM_IDLE_DESC_LIST 134 135 An MSDU extension descriptor shall never be marked as WBM 136 being the 'owner', and thus WBM will forward it to FW/SW 137 138 139 <enum 0 Put_in_idle_list> Put the buffer or descriptor back 140 in the idle list. In case of MSDU or MDPU link descriptor, 141 BM does not need to check to release any individual MSDU 142 buffers 143 144 <enum 1 release_msdu_list > This BM action can only be used 145 in combination with buffer_or_desc_type being msdu_link_descriptor. 146 Field first_msdu_index points out which MSDU pointer in 147 the MSDU link descriptor is the first of an MPDU that is 148 released. 149 BM shall release all the MSDU buffers linked to this first 150 MSDU buffer pointer. All related MSDU buffer pointer entries 151 shall be set to value 0, which represents the 'NULL" pointer. 152 When all MSDU buffer pointers in the MSDU link descriptor 153 are 'NULL', the MSDU link descriptor itself shall also 154 be released. 155 156 <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 157 158 Put the buffer or descriptor back in the idle list. Only 159 valid in combination with buffer_or_desc_type indicating 160 MDPU_link_descriptor. 161 BM shall release the MPDU link descriptor as well as all 162 MSDUs that are linked to the MPDUs in this descriptor. 163 164 165 TODO: Any restrictions? 166 <legal 0-2> 167 */ 168 169 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 170 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 171 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 172 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 173 174 175 /* Description BUFFER_OR_DESC_TYPE 176 177 Consumer: WBM/SW/FW 178 Producer: SW/TQM/RXDMA/REO/SWITCH 179 180 Field only valid when WBM is marked as the return_buffer_manager 181 in the Released_Buffer_address_info 182 183 Indicates that type of buffer or descriptor is being released 184 185 186 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 187 188 <enum 1 msdu_link_descriptor> The address points to an TX 189 MSDU link descriptor 190 <enum 2 mpdu_link_descriptor> The address points to an MPDU 191 link descriptor 192 <enum 3 msdu_ext_descriptor > The address points to an MSDU 193 extension descriptor. 194 In case BM finds this one in a release ring, it passes it 195 on to FW... 196 <enum 4 queue_ext_descriptor> The address points to an TQM 197 queue extension descriptor. WBM should treat this is the 198 same way as a link descriptor. That is, put the 128 byte 199 buffer back in the link buffer idle list. 200 201 TODO: Any restrictions? 202 <legal 0-4> 203 */ 204 205 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 206 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 207 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 208 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 209 210 211 /* Description RETURN_BUFFER_MANAGER 212 213 'Return_buffer_manager' field of the MSDU's buffer address 214 info, for debug 215 */ 216 217 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 218 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 219 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 220 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 221 222 223 /* Description RESERVED_2A 224 225 <legal 0> 226 */ 227 228 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 229 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 230 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 231 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 232 233 234 /* Description CACHE_ID 235 236 Indicates the WBM cache the MSDU was released from 237 <legal all> 238 */ 239 240 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 241 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 242 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 243 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 244 245 246 /* Description COOKIE_CONVERSION_STATUS 247 248 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 249 250 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 251 <legal 1> 252 */ 253 254 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 255 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 256 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 257 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 258 259 260 /* Description RXDMA_PUSH_REASON 261 262 Field only valid when Release_source_module is set to release_source_RXDMA 263 264 265 Indicates why rxdma pushed the frame to this ring 266 267 <enum 0 rxdma_error_detected> RXDMA detected an error an 268 pushed this frame to this queue 269 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 270 to this queue per received routing instructions. No error 271 within RXDMA was detected 272 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 273 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 274 set, but instead WBM might just see a NULL pointer in the 275 MSDU link descriptor. This is to be considered a normal 276 condition for this scenario. 277 278 <legal 0 - 2> 279 */ 280 281 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 282 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 283 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 284 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 285 286 287 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 288 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 289 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 290 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 291 292 293 /* Description REO_PUSH_REASON 294 295 Field only valid when Release_source_module is set to release_source_REO 296 297 298 Indicates why REO pushed the frame to this release ring 299 300 <enum 0 reo_error_detected> Reo detected an error an pushed 301 this frame to this queue 302 <enum 1 reo_routing_instruction> Reo pushed the frame to 303 this queue per received routing instructions. No error 304 within REO was detected 305 306 <legal 0 - 1> 307 */ 308 309 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 310 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 311 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 312 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 313 314 315 /* Description REO_ERROR_CODE 316 317 Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 318 319 320 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 321 in the REO_ENTRANCE ring is set to 0 322 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 323 bit is NOT set 324 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 325 session having been setup. 326 <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 327 Retry bit set: duplicate frame 328 <enum 4 ba_duplicate> BA session, duplicate frame 329 <enum 5 regular_frame_2k_jump> A normal (management/data 330 frame) received with 2K jump in SN 331 <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 332 SSN 333 <enum 7 regular_frame_OOR> A normal (management/data frame) 334 received with SN falling within the OOR window 335 <enum 8 bar_frame_OOR> A bar received with SSN falling within 336 the OOR window 337 <enum 9 bar_frame_no_ba_session> A bar received without 338 a BA session 339 <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 340 equal to SN 341 <enum 11 pn_check_failed> PN Check Failed packet. 342 <enum 12 2k_error_handling_flag_set> Frame is forwarded 343 as a result of the 'Seq_2k_error_detected_flag' been set 344 in the REO Queue descriptor 345 <enum 13 pn_error_handling_flag_set> Frame is forwarded 346 as a result of the 'pn_error_detected_flag' been set in 347 the REO Queue descriptor 348 <enum 14 queue_descriptor_blocked_set> Frame is forwarded 349 as a result of the queue descriptor(address) being blocked 350 as SW/FW seems to be currently in the process of making 351 updates to this descriptor... 352 353 <legal 0-14> 354 */ 355 356 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 357 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 358 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 359 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 360 361 362 /* Description WBM_INTERNAL_ERROR 363 364 Can only be set by WBM. 365 366 Is set when WBM got a buffer pointer but the action was 367 to push it to the idle link descriptor ring or do link related 368 activity 369 OR 370 Is set when WBM got a link buffer pointer but the action 371 was to push it to the buffer descriptor ring 372 373 <legal all> 374 */ 375 376 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 377 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 378 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 379 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 380 381 382 /* Description RX_MPDU_DESC_INFO_DETAILS 383 384 Consumer: REO/SW/FW 385 Producer: RXDMA 386 387 General information related to the MPDU whose link descriptors 388 are being released from Rx DMA or REO 389 */ 390 391 392 /* Description MSDU_COUNT 393 394 Consumer: REO/SW/FW 395 Producer: RXDMA 396 397 The number of MSDUs within the MPDU 398 <legal all> 399 */ 400 401 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 402 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 403 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 404 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 405 406 407 /* Description FRAGMENT_FLAG 408 409 Consumer: REO/SW/FW 410 Producer: RXDMA 411 412 When set, this MPDU is a fragment and REO should forward 413 this fragment MPDU to the REO destination ring without 414 any reorder checks, pn checks or bitmap update. This implies 415 that REO is forwarding the pointer to the MSDU link descriptor. 416 The destination ring is coming from a programmable register 417 setting in REO 418 419 <legal all> 420 */ 421 422 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 423 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 424 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 425 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 426 427 428 /* Description MPDU_RETRY_BIT 429 430 Consumer: REO/SW/FW 431 Producer: RXDMA 432 433 The retry bit setting from the MPDU header of the received 434 frame 435 <legal all> 436 */ 437 438 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 439 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 440 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 441 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 442 443 444 /* Description AMPDU_FLAG 445 446 Consumer: REO/SW/FW 447 Producer: RXDMA 448 449 When set, the MPDU was received as part of an A-MPDU. 450 <legal all> 451 */ 452 453 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 454 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 455 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 456 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 457 458 459 /* Description BAR_FRAME 460 461 Consumer: REO/SW/FW 462 Producer: RXDMA 463 464 When set, the received frame is a BAR frame. After processing, 465 this frame shall be pushed to SW or deleted. 466 <legal all> 467 */ 468 469 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 470 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 471 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 472 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 473 474 475 /* Description PN_FIELDS_CONTAIN_VALID_INFO 476 477 Consumer: REO/SW/FW 478 Producer: RXDMA 479 480 Copied here by RXDMA from RX_MPDU_END 481 When not set, REO will Not perform a PN sequence number 482 check 483 */ 484 485 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 486 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 487 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 488 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 489 490 491 /* Description RAW_MPDU 492 493 Field only valid when first_msdu_in_mpdu_flag is set. 494 495 When set, the contents in the MSDU buffer contains a 'RAW' 496 MPDU. This 'RAW' MPDU might be spread out over multiple 497 MSDU buffers. 498 <legal all> 499 */ 500 501 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 502 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 503 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 504 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 505 506 507 /* Description MORE_FRAGMENT_FLAG 508 509 The More Fragment bit setting from the MPDU header of the 510 received frame 511 512 <legal all> 513 */ 514 515 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 516 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 517 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 518 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 519 520 521 /* Description SRC_INFO 522 523 Source (virtual) device/interface info. associated with 524 this peer 525 526 This field gets passed on by REO to PPE in the EDMA descriptor 527 ('REO_TO_PPE_RING'). 528 529 <legal all> 530 */ 531 532 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 533 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 534 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 535 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 536 537 538 /* Description MPDU_QOS_CONTROL_VALID 539 540 When set, the MPDU has a QoS control field. 541 542 In case of ndp or phy_err, this field will never be set. 543 544 <legal all> 545 */ 546 547 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 548 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 549 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 550 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 551 552 553 /* Description TID 554 555 Field only valid when mpdu_qos_control_valid is set 556 557 The TID field in the QoS control field 558 <legal all> 559 */ 560 561 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 562 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 563 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 564 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 565 566 567 /* Description PEER_META_DATA 568 569 Meta data that SW has programmed in the Peer table entry 570 of the transmitting STA. 571 <legal all> 572 */ 573 574 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 575 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 576 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 577 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 578 579 580 /* Description RX_MSDU_DESC_INFO_DETAILS 581 582 Consumer: TQM/SW 583 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 584 585 In case of RXDMA or REO releasing Rx MSDU link descriptors,' 586 WBM fills this field with Rx_msdu_desc_info_details when 587 releasing the MSDUs to SW. 588 */ 589 590 591 /* Description FIRST_MSDU_IN_MPDU_FLAG 592 593 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 594 multiple buffers, this field will be valid in the Last 595 buffer used by the MSDU 596 597 <enum 0 Not_first_msdu> This is not the first MSDU in the 598 MPDU. 599 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 600 601 602 <legal all> 603 */ 604 605 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 606 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 607 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 608 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 609 610 611 /* Description LAST_MSDU_IN_MPDU_FLAG 612 613 Consumer: WBM/REO/SW/FW 614 Producer: RXDMA 615 616 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 617 multiple buffers, this field will be valid in the Last 618 buffer used by the MSDU 619 620 <enum 0 Not_last_msdu> There are more MSDUs linked to this 621 MSDU that belongs to this MPDU 622 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 623 This setting is only allowed in combination with 'Msdu_continuation' 624 set to 0. This implies that when an msdu is spread out over 625 multiple buffers and thus msdu_continuation is set, only 626 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 627 be set. 628 629 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 630 are set, the MPDU that this MSDU belongs to only contains 631 a single MSDU. 632 633 634 <legal all> 635 */ 636 637 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 638 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 639 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 640 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 641 642 643 /* Description MSDU_CONTINUATION 644 645 When set, this MSDU buffer was not able to hold the entire 646 MSDU. The next buffer will therefor contain additional 647 information related to this MSDU. 648 649 <legal all> 650 */ 651 652 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 653 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 654 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 655 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 656 657 658 /* Description MSDU_LENGTH 659 660 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 661 multiple buffers, this field will be valid in the First 662 buffer used by MSDU. 663 664 Full MSDU length in bytes after decapsulation. 665 666 This field is still valid for MPDU frames without A-MSDU. 667 It still represents MSDU length after decapsulation 668 669 Or in case of RAW MPDUs, it indicates the length of the 670 entire MPDU (without FCS field) 671 <legal all> 672 */ 673 674 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 675 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 676 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 677 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 678 679 680 /* Description MSDU_DROP 681 682 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 683 multiple buffers, this field will be valid in the Last 684 buffer used by the MSDU 685 686 When set, REO shall drop this MSDU and not forward it to 687 any other ring... 688 <legal all> 689 */ 690 691 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 692 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 693 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 694 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 695 696 697 /* Description SA_IS_VALID 698 699 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 700 multiple buffers, this field will be valid in the Last 701 buffer used by the MSDU 702 703 Indicates that OLE found a valid SA entry for this MSDU 704 <legal all> 705 */ 706 707 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 708 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 709 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 710 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 711 712 713 /* Description DA_IS_VALID 714 715 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 716 multiple buffers, this field will be valid in the Last 717 buffer used by the MSDU 718 719 Indicates that OLE found a valid DA entry for this MSDU 720 <legal all> 721 */ 722 723 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 724 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 725 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 726 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 727 728 729 /* Description DA_IS_MCBC 730 731 Field Only valid if "da_is_valid" is set 732 733 Indicates the DA address was a Multicast of Broadcast address 734 for this MSDU 735 <legal all> 736 */ 737 738 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 739 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 740 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 741 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 742 743 744 /* Description L3_HEADER_PADDING_MSB 745 746 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 747 as the LSB is always zero) 748 Number of bytes padded to make sure that the L3 header will 749 always start of a Dword boundary 750 <legal all> 751 */ 752 753 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 754 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 755 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 756 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 757 758 759 /* Description TCP_UDP_CHKSUM_FAIL 760 761 Passed on from 'RX_ATTENTION' TLV 762 Indicates that the computed checksum did not match the checksum 763 in the TCP/UDP header. 764 <legal all> 765 */ 766 767 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 768 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 769 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 770 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 771 772 773 /* Description IP_CHKSUM_FAIL 774 775 Passed on from 'RX_ATTENTION' TLV 776 Indicates that the computed checksum did not match the checksum 777 in the IP header. 778 <legal all> 779 */ 780 781 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 782 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 783 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 784 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 785 786 787 /* Description FR_DS 788 789 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 790 TLV 791 Set if the 'from DS' bit is set in the frame control. 792 <legal all> 793 */ 794 795 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 796 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 797 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 798 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 799 800 801 /* Description TO_DS 802 803 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 804 TLV 805 Set if the 'to DS' bit is set in the frame control. 806 <legal all> 807 */ 808 809 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 810 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 811 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 812 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 813 814 815 /* Description INTRA_BSS 816 817 This packet needs intra-BSS routing by SW as the 'vdev_id' 818 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 819 that this MSDU was got in. 820 821 <legal all> 822 */ 823 824 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 825 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 826 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 827 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 828 829 830 /* Description DEST_CHIP_ID 831 832 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 833 to support intra-BSS routing with multi-chip multi-link 834 operation. 835 836 This indicates into which chip's TCL the packet should be 837 queued. 838 839 <legal all> 840 */ 841 842 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 843 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 844 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 845 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 846 847 848 /* Description DECAP_FORMAT 849 850 Indicates the format after decapsulation: 851 852 <enum 0 RAW> No encapsulation 853 <enum 1 Native_WiFi> 854 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 855 856 <enum 3 802_3> Indicate Ethernet 857 858 <legal all> 859 */ 860 861 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 862 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 863 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 864 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 865 866 867 /* Description DEST_CHIP_PMAC_ID 868 869 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 870 to support intra-BSS routing with multi-chip multi-link 871 operation. 872 873 This indicates into which link/'vdev' the packet should 874 be queued in TCL. 875 876 <legal all> 877 */ 878 879 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 880 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 881 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 882 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 883 884 885 /* Description BUFFER_PHYS_ADDR_31_0 886 887 LSB 32 bits of the physical address from the MSDU's buffer 888 address info, for debug 889 */ 890 891 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 892 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 893 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 894 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 895 896 897 /* Description BUFFER_PHYS_ADDR_39_32 898 899 MSB 8 bits of the physical address from the MSDU's buffer 900 address info, for debug 901 */ 902 903 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 904 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 905 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 906 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 907 908 909 /* Description SW_BUFFER_COOKIE 910 911 'Sw_buffer_cookie' field of the MSDU's buffer address info 912 used to fill 'Buffer_virt_addr_*,' for debug 913 914 For further debugging, if enabled, WBM may fill the Rx MPDU 915 sequence number in bits [27:16] (copying from field Reserved_7a 916 in 'WBM_RELEASE_RING_RX'). 917 918 */ 919 920 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 921 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 922 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 923 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 924 925 926 /* Description LOOPING_COUNT 927 928 Consumer: WBM/SW/FW 929 Producer: SW/TQM/RXDMA/REO/SWITCH 930 931 If WBM_internal_error is set, this descriptor is sent to 932 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 933 is used to indicate an error code. 934 935 The values reported are documented further in the WBM MLD 936 doc. 937 938 If WBM_internal_error is not set, the following holds. 939 940 A count value that indicates the number of times the producer 941 of entries into the Buffer Manager Ring has looped around 942 the ring. 943 At initialization time, this value is set to 0. On the first 944 loop, this value is set to 1. After the max value is reached 945 allowed by the number of bits for this field, the count 946 value continues with 0 again. 947 948 In case SW is the consumer of the ring entries, it can use 949 this field to figure out up to where the producer of entries 950 has created new entries. This eliminates the need to check 951 where the "head pointer' of the ring is located once the 952 SW starts processing an interrupt indicating that new entries 953 have been put into this ring... 954 955 Also note that SW if it wants only needs to look at the 956 LSB bit of this count value. 957 <legal all> 958 */ 959 960 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 961 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 962 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 963 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 964 965 966 967 #endif // WBM2SW_COMPLETION_RING_RX 968