1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 18 #define _WBM2SW_COMPLETION_RING_TX_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "tx_rate_stats_info.h" 23 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 24 25 26 struct wbm2sw_completion_ring_tx { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 29 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 30 uint32_t release_source_module : 3, // [2:0] 31 cache_id : 1, // [3:3] 32 reserved_2a : 2, // [5:4] 33 buffer_or_desc_type : 3, // [8:6] 34 return_buffer_manager : 4, // [12:9] 35 tqm_release_reason : 4, // [16:13] 36 rbm_override_valid : 1, // [17:17] 37 sw_buffer_cookie_11_0 : 12, // [29:18] 38 cookie_conversion_status : 1, // [30:30] 39 wbm_internal_error : 1; // [31:31] 40 uint32_t tqm_status_number : 24, // [23:0] 41 transmit_count : 7, // [30:24] 42 sw_release_details_valid : 1; // [31:31] 43 uint32_t ack_frame_rssi : 8, // [7:0] 44 first_msdu : 1, // [8:8] 45 last_msdu : 1, // [9:9] 46 fw_tx_notify_frame : 3, // [12:10] 47 buffer_timestamp : 19; // [31:13] 48 struct tx_rate_stats_info tx_rate_stats; 49 uint32_t sw_peer_id : 16, // [15:0] 50 tid : 4, // [19:16] 51 sw_buffer_cookie_19_12 : 8, // [27:20] 52 looping_count : 4; // [31:28] 53 #else 54 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 55 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 56 uint32_t wbm_internal_error : 1, // [31:31] 57 cookie_conversion_status : 1, // [30:30] 58 sw_buffer_cookie_11_0 : 12, // [29:18] 59 rbm_override_valid : 1, // [17:17] 60 tqm_release_reason : 4, // [16:13] 61 return_buffer_manager : 4, // [12:9] 62 buffer_or_desc_type : 3, // [8:6] 63 reserved_2a : 2, // [5:4] 64 cache_id : 1, // [3:3] 65 release_source_module : 3; // [2:0] 66 uint32_t sw_release_details_valid : 1, // [31:31] 67 transmit_count : 7, // [30:24] 68 tqm_status_number : 24; // [23:0] 69 uint32_t buffer_timestamp : 19, // [31:13] 70 fw_tx_notify_frame : 3, // [12:10] 71 last_msdu : 1, // [9:9] 72 first_msdu : 1, // [8:8] 73 ack_frame_rssi : 8; // [7:0] 74 struct tx_rate_stats_info tx_rate_stats; 75 uint32_t looping_count : 4, // [31:28] 76 sw_buffer_cookie_19_12 : 8, // [27:20] 77 tid : 4, // [19:16] 78 sw_peer_id : 16; // [15:0] 79 #endif 80 }; 81 82 83 /* Description BUFFER_VIRT_ADDR_31_0 84 85 Lower 32 bits of the 64-bit virtual address corresponding 86 to the MSDU being released 87 <legal all> 88 */ 89 90 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 91 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 92 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 93 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 94 95 96 /* Description BUFFER_VIRT_ADDR_63_32 97 98 Upper 32 bits of the 64-bit virtual address corresponding 99 to the MSDU being released 100 <legal all> 101 */ 102 103 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 104 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 105 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 106 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 107 108 109 /* Description RELEASE_SOURCE_MODULE 110 111 Indicates which module initiated the release of this buffer 112 or descriptor 113 114 <enum 1 release_source_RXDMA> DO NOT USE 115 <enum 2 release_source_REO> DO NOT USE 116 <enum 5 release_source_FW_RX> DO NOT USE 117 <enum 4 release_source_SW_RX> DO NOT USE 118 <enum 0 release_source_TQM> TQM released this buffer or 119 descriptor 120 <enum 3 release_source_FW_TX> FW released this buffer or 121 descriptor 122 <enum 6 release_source_SW_TX> SW released this buffer or 123 descriptor 124 <legal 0-6> 125 */ 126 127 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 128 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 129 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 130 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 131 132 133 /* Description CACHE_ID 134 135 To improve WBM performance, out-of-order completions may 136 be allowed to process multiple MPDUs in parallel. 137 138 The MSDUs released from each cache would be in order so 'First_msdu' 139 and this field together can be used by SW to reorder the 140 completions back to the original order by keeping all MSDUs 141 of an MPDU from one cache together before switching to 142 the next MPDU (from either cache). 143 <legal all> 144 */ 145 146 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 147 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 148 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 149 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 150 151 152 /* Description RESERVED_2A 153 154 <legal 0> 155 */ 156 157 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 158 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 159 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 160 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 161 162 163 /* Description BUFFER_OR_DESC_TYPE 164 165 Consumer: WBM/SW/FW 166 Producer: SW/TQM/RXDMA/REO/SWITCH 167 168 Field only valid when WBM is marked as the return_buffer_manager 169 in the Released_Buffer_address_info 170 171 Indicates that type of buffer or descriptor is being released 172 173 174 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 175 176 <enum 1 msdu_link_descriptor> The address points to an TX 177 MSDU link descriptor 178 <enum 2 mpdu_link_descriptor> The address points to an MPDU 179 link descriptor 180 <enum 3 msdu_ext_descriptor > The address points to an MSDU 181 extension descriptor. 182 In case BM finds this one in a release ring, it passes it 183 on to FW... 184 <enum 4 queue_ext_descriptor> The address points to an TQM 185 queue extension descriptor. WBM should treat this is the 186 same way as a link descriptor. That is, put the 128 byte 187 buffer back in the link buffer idle list. 188 189 <legal 0-4> 190 */ 191 192 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 193 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 194 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 195 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 196 197 198 /* Description RETURN_BUFFER_MANAGER 199 200 'Return_buffer_manager' field of the MSDU's buffer address 201 info, for debug 202 */ 203 204 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 205 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 206 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 207 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 208 209 210 /* Description TQM_RELEASE_REASON 211 212 Consumer: WBM/SW/FW 213 Producer: TQM 214 215 Field only valid when Release_source_module is set to release_source_TQM 216 217 218 (rr = Release Reason) 219 <enum 0 tqm_rr_frame_acked> frame is removed because an 220 ACK of BA for it was received 221 <enum 1 tqm_rr_rem_cmd_rem> frame is removed because a remove 222 command of type "Remove_mpdus" initiated by SW 223 <enum 2 tqm_rr_rem_cmd_tx> frame is removed because a remove 224 command of type "Remove_transmitted_mpdus" initiated by 225 SW 226 <enum 3 tqm_rr_rem_cmd_notx> frame is removed because a 227 remove command of type "Remove_untransmitted_mpdus" initiated 228 by SW 229 <enum 4 tqm_rr_rem_cmd_aged> frame is removed because a 230 remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" 231 initiated by SW 232 <enum 5 tqm_fw_reason1> frame is removed because a remove 233 command where fw indicated that remove reason is fw_reason1 234 235 <enum 6 tqm_fw_reason2> frame is removed because a remove 236 command where fw indicated that remove reason is fw_reason1 237 238 <enum 7 tqm_fw_reason3> frame is removed because a remove 239 command where fw indicated that remove reason is fw_reason1 240 241 <enum 8 tqm_rr_rem_cmd_disable_queue> frame is removed because 242 a remove command of type "remove_mpdus_and_disable_queue" 243 or "remove_msdus_and_disable_flow" initiated by SW 244 <enum 9 tqm_rr_rem_cmd_till_nonmatching> frame is removed 245 because remove command of type "remove_till_nonmatching_mpdu" 246 initiated by SW 247 <enum 10 tqm_rr_drop_threshold> frame is dropped at TQM 248 entrance due to one of slow/medium/hard drop threshold criteria 249 250 <enum 11 tqm_rr_link_desc_unavailable> frame is dropped 251 at TQM entrance due to the WBM2TQM_LINK_RING having fewer 252 descriptors than a threshold programmed in TQM 253 <enum 12 tqm_rr_drop_or_invalid_msdu> frame is dropped at 254 TQM entrance due to 'TQM_Drop_frame' being set or "null" 255 MSDU flow pointer or MSDU flow pointer 'Flow_valid' being 256 zero or MSDU_length being zero 257 <enum 13 tqm_rr_multicast_drop> frame is dropped at TQM 258 entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 259 set to TCL_multicast_drop_for_vdev. 260 <enum 14 tqm_rr_vdev_mismatch_drop> frame is dropped at 261 TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 262 set to TCL_vdev_id_mismatch_drop. 263 264 <legal 0-14> 265 */ 266 267 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 268 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 269 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 270 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 271 272 273 /* Description RBM_OVERRIDE_VALID 274 275 This is set to 0 for Tx cases not involving reinjection, 276 and set to 1 for TQM release cases requiring FW reinjection 277 278 When set to 1, WBM releases the MSDU buffers to FW and overrides 279 the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' 280 structure, for FW reinjection of these MSDUs 281 282 When releasing to host SW, this will be 0 if there is no 283 misprogramming. 284 <legal 0> 285 */ 286 287 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 288 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 289 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 290 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 291 292 293 /* Description SW_BUFFER_COOKIE_11_0 294 295 LSB 12 bits of the 'Sw_buffer_cookie' field of the MSDU's 296 buffer address info used to fill 'Buffer_virt_addr_*,' 297 for debug 298 */ 299 300 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 301 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 302 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 303 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 304 305 306 /* Description COOKIE_CONVERSION_STATUS 307 308 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 309 310 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 311 <legal 1> 312 */ 313 314 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 315 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 316 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 317 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 318 319 320 /* Description WBM_INTERNAL_ERROR 321 322 Can only be set by WBM. 323 324 Is set when WBM got a buffer pointer but the action was 325 to push it to the idle link descriptor ring or do link related 326 activity 327 OR 328 Is set when WBM got a link buffer pointer but the action 329 was to push it to the buffer descriptor ring 330 331 <legal all> 332 */ 333 334 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 335 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 336 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 337 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 338 339 340 /* Description TQM_STATUS_NUMBER 341 342 Field only valid when Release_source_module is set to release_source_TQM 343 344 345 The value in this field is equal to value of the 'TQM_CMD_Number' 346 field from the TQM command or the 'TQM_add_cmd_Number' field 347 from the TQM entrance ring descriptor LSB 24-bits. 348 349 This field helps to correlate the statuses with the TQM 350 commands. 351 352 NOTE that SW could program this number to be equal to the 353 PPDU_ID number in case direct correlation with the PPDU 354 ID is desired 355 356 <legal all> 357 */ 358 359 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 360 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 361 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 362 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 363 364 365 /* Description TRANSMIT_COUNT 366 367 Field only valid when Release_source_module is set to release_source_TQM 368 369 370 The number of times this frame has been transmitted 371 */ 372 373 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 374 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 375 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 376 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 377 378 379 /* Description SW_RELEASE_DETAILS_VALID 380 381 Consumer: SW 382 Producer: WBM 383 384 When set, some WBM specific release info for SW is valid. 385 386 This is set when WMB got a 'release_msdu_list' command from 387 TQM and the return buffer manager is not WMB. WBM will 388 then de-aggregate all the MSDUs and pass them one at a time 389 on to the 'buffer owner' 390 391 <legal all> 392 */ 393 394 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 395 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 396 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 397 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 398 399 400 /* Description ACK_FRAME_RSSI 401 402 This field is only valid when the source is TQM. 403 404 If this frame is removed as the result of the reception 405 of an ACK or BA, this field indicates the RSSI of the received 406 ACK or BA frame. 407 408 When the frame is removed as result of a direct remove command 409 from the SW, this field is set to 0x0 (which is never 410 a valid value when real RSSI is available) 411 412 <legal all> 413 */ 414 415 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 416 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 417 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 418 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 419 420 421 /* Description FIRST_MSDU 422 423 Field only valid when SW_release_details_valid is set. 424 425 Consumer: SW 426 Producer: WBM 427 428 When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' 429 command. 430 <legal all> 431 */ 432 433 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 434 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 435 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 436 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 437 438 439 /* Description LAST_MSDU 440 441 Field only valid when SW_release_details_valid is set. 442 443 Consumer: SW 444 Producer: WBM 445 446 When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' 447 command. 448 <legal all> 449 */ 450 451 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 452 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 453 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 454 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 455 456 457 /* Description FW_TX_NOTIFY_FRAME 458 459 Field only valid when SW_release_details_valid is set. 460 461 Consumer: SW 462 Producer: WBM 463 464 This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS 465 for this frame from the MSDU link descriptor 466 <legal all> 467 */ 468 469 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 470 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 471 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 472 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 473 474 475 /* Description BUFFER_TIMESTAMP 476 477 Field only valid when SW_release_details_valid is set. 478 479 Consumer: SW 480 Producer: WBM 481 482 This is the Buffer_timestamp field from the TX_MSDU_DETAILS 483 for this frame from the MSDU link descriptor. 484 485 Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' 486 register 487 488 <legal all> 489 */ 490 491 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 492 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 493 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 494 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 495 496 497 /* Description TX_RATE_STATS 498 499 Consumer: TQM/SW 500 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 501 502 Details for command execution tracking purposes. 503 */ 504 505 506 /* Description TX_RATE_STATS_INFO_VALID 507 508 When set all other fields in this STRUCT contain valid info. 509 510 511 When clear, none of the other fields contain valid info. 512 513 <legal all> 514 */ 515 516 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 517 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 518 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 519 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 520 521 522 /* Description TRANSMIT_BW 523 524 Field only valid when Tx_rate_stats_info_valid is set 525 526 Indicates the BW of the upcoming transmission that shall 527 likely start in about 3 -4 us on the medium 528 529 <enum_type BW_ENUM> 530 */ 531 532 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 533 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 534 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 535 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 536 537 538 /* Description TRANSMIT_PKT_TYPE 539 540 Field only valid when Tx_rate_stats_info_valid is set 541 542 Field filled in by PDG. 543 Not valid when in SW transmit mode 544 545 The packet type 546 <enum_type PKT_TYPE_ENUM> 547 */ 548 549 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 550 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 551 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 552 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 553 554 555 /* Description TRANSMIT_STBC 556 557 Field only valid when Tx_rate_stats_info_valid is set 558 559 Field filled in by PDG. 560 Not valid when in SW transmit mode 561 562 When set, STBC transmission rate was used. 563 */ 564 565 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 566 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 567 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 568 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 569 570 571 /* Description TRANSMIT_LDPC 572 573 Field only valid when Tx_rate_stats_info_valid is set 574 575 Field filled in by PDG. 576 Not valid when in SW transmit mode 577 578 When set, use LDPC transmission rates 579 */ 580 581 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 582 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 583 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 584 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 585 586 587 /* Description TRANSMIT_SGI 588 589 Field only valid when Tx_rate_stats_info_valid is set 590 591 Field filled in by PDG. 592 Not valid when in SW transmit mode 593 594 Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. 595 596 597 <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used 598 for HE 599 <enum 1 0_4_us_sgi > Legacy short GI. Can also be used 600 for HE 601 <enum 2 1_6_us_sgi > HE related GI 602 <enum 3 3_2_us_sgi > HE related GI 603 <legal 0 - 3> 604 */ 605 606 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 607 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 608 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 609 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 610 611 612 /* Description TRANSMIT_MCS 613 614 Field only valid when Tx_rate_stats_info_valid is set 615 616 Field filled in by PDG. 617 Not valid when in SW transmit mode 618 619 For details, refer to MCS_TYPE description 620 <legal all> 621 */ 622 623 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 624 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 625 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 626 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 627 628 629 /* Description OFDMA_TRANSMISSION 630 631 Field only valid when Tx_rate_stats_info_valid is set 632 633 Field filled in by PDG. 634 635 Set when the transmission was an OFDMA transmission (DL 636 or UL). 637 <legal all> 638 */ 639 640 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 641 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 642 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 643 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 644 645 646 /* Description TONES_IN_RU 647 648 Field only valid when Tx_rate_stats_info_valid is set 649 650 Field filled in by PDG. 651 Not valid when in SW transmit mode 652 653 The number of tones in the RU used. 654 <legal all> 655 */ 656 657 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 658 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 659 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 660 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 661 662 663 /* Description TRANSMIT_NSS 664 665 Field only valid when Tx_rate_stats_info_valid is set 666 667 Field filled in by PDG 668 Not valid when in SW transmit mode 669 670 The number of spatial streams used in the transmission 671 672 <enum_type SS_COUNT_ENUM> 673 */ 674 675 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 676 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 677 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 678 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 679 680 681 /* Description PPDU_TRANSMISSION_TSF 682 683 Field only valid when Tx_rate_stats_info_valid is set 684 685 Based on a HWSCH configuration register setting, this field 686 either contains: 687 688 Lower 32 bits of the TSF, snapshot of this value when transmission 689 of the PPDU containing the frame finished. 690 OR 691 Lower 32 bits of the TSF, snapshot of this value when transmission 692 of the PPDU containing the frame started 693 694 <legal all> 695 */ 696 697 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 698 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 699 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 700 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 701 702 703 /* Description SW_PEER_ID 704 705 Field only valid when Release_source_module is set to release_source_TQM 706 707 708 1) Release of msdu buffer due to drop_frame = 1. Flow is 709 not fetched and hence sw_peer_id and tid = 0 710 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 711 = e_num 1 tqm_rr_rem_cmd_rem 712 713 714 2) Release of msdu buffer due to Flow is not fetched and 715 hence sw_peer_id and tid = 0 716 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 717 = e_num 1 tqm_rr_rem_cmd_rem 718 719 720 3) Release of msdu link due to remove_mpdu or acked_mpdu 721 command. 722 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 723 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 724 725 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 726 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 727 728 Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE 729 descriptor 730 <legal all> 731 */ 732 733 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 734 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 735 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 736 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 737 738 739 /* Description TID 740 741 Field only valid when Release_source_module is set to release_source_TQM 742 743 744 1) Release of msdu buffer due to drop_frame = 1. Flow is 745 not fetched and hence sw_peer_id and tid = 0 746 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 747 = e_num 1 tqm_rr_rem_cmd_rem 748 749 750 2) Release of msdu buffer due to Flow is not fetched and 751 hence sw_peer_id and tid = 0 752 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 753 = e_num 1 tqm_rr_rem_cmd_rem 754 755 756 3) Release of msdu link due to remove_mpdu or acked_mpdu 757 command. 758 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 759 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 760 761 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 762 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 763 764 765 This field represents the TID from the TX_MSDU_FLOW descriptor 766 or TX_MPDU_QUEUE descriptor 767 768 <legal all> 769 */ 770 771 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 772 #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 773 #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 774 #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 775 776 777 /* Description SW_BUFFER_COOKIE_19_12 778 779 MSB 8 bits of the 'Sw_buffer_cookie' field of the MSDU's 780 buffer address info used to fill 'Buffer_virt_addr_*,' 781 for debug. 782 WBM shall have configuration to copy 'TQM_Status_Number_31_24' 783 from the WBM input descriptor here instead. 784 */ 785 786 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 787 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 788 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 789 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 790 791 792 /* Description LOOPING_COUNT 793 794 Consumer: WBM/SW/FW 795 Producer: SW/TQM/RXDMA/REO/SWITCH 796 797 If WBM_internal_error is set, this descriptor is sent to 798 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 799 is used to indicate an error code. 800 801 The values reported are documented further in the WBM MLD 802 doc. 803 804 If WBM_internal_error is not set, the following holds. 805 806 A count value that indicates the number of times the producer 807 of entries into the Buffer Manager Ring has looped around 808 the ring. 809 At initialization time, this value is set to 0. On the first 810 loop, this value is set to 1. After the max value is reached 811 allowed by the number of bits for this field, the count 812 value continues with 0 again. 813 814 In case SW is the consumer of the ring entries, it can use 815 this field to figure out up to where the producer of entries 816 has created new entries. This eliminates the need to check 817 where the "head pointer' of the ring is located once the 818 SW starts processing an interrupt indicating that new entries 819 have been put into this ring... 820 821 Also note that SW if it wants only needs to look at the 822 LSB bit of this count value. 823 <legal all> 824 */ 825 826 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 827 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 828 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 829 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 830 831 832 833 #endif // WBM2SW_COMPLETION_RING_TX 834