1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _WBM_RELEASE_RING_H_ 18 #define _WBM_RELEASE_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 24 25 26 struct wbm_release_ring { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct buffer_addr_info released_buff_or_desc_addr_info; 29 uint32_t release_source_module : 3, // [2:0] 30 reserved_2a : 3, // [5:3] 31 buffer_or_desc_type : 3, // [8:6] 32 reserved_2b : 22, // [30:9] 33 wbm_internal_error : 1; // [31:31] 34 uint32_t reserved_3a : 32; // [31:0] 35 uint32_t reserved_4a : 32; // [31:0] 36 uint32_t reserved_5a : 32; // [31:0] 37 uint32_t reserved_6a : 32; // [31:0] 38 uint32_t reserved_7a : 28, // [27:0] 39 looping_count : 4; // [31:28] 40 #else 41 struct buffer_addr_info released_buff_or_desc_addr_info; 42 uint32_t wbm_internal_error : 1, // [31:31] 43 reserved_2b : 22, // [30:9] 44 buffer_or_desc_type : 3, // [8:6] 45 reserved_2a : 3, // [5:3] 46 release_source_module : 3; // [2:0] 47 uint32_t reserved_3a : 32; // [31:0] 48 uint32_t reserved_4a : 32; // [31:0] 49 uint32_t reserved_5a : 32; // [31:0] 50 uint32_t reserved_6a : 32; // [31:0] 51 uint32_t looping_count : 4, // [31:28] 52 reserved_7a : 28; // [27:0] 53 #endif 54 }; 55 56 57 /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO 58 59 DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or 60 a 64-bit virtual address. 61 */ 62 63 64 /* Description BUFFER_ADDR_31_0 65 66 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 67 descriptor OR Link Descriptor 68 69 In case of 'NULL' pointer, this field is set to 0 70 <legal all> 71 */ 72 73 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 74 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 75 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 76 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 77 78 79 /* Description BUFFER_ADDR_39_32 80 81 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 82 descriptor OR Link Descriptor 83 84 In case of 'NULL' pointer, this field is set to 0 85 <legal all> 86 */ 87 88 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 89 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 90 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 91 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 92 93 94 /* Description RETURN_BUFFER_MANAGER 95 96 Consumer: WBM 97 Producer: SW/FW 98 99 In case of 'NULL' pointer, this field is set to 0 100 101 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 102 descriptor OR link descriptor that is being pointed to 103 shall be returned after the frame has been processed. It 104 is used by WBM for routing purposes. 105 106 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 107 to the WMB buffer idle list 108 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 109 to the WBM idle link descriptor idle list, where the chip 110 0 WBM is chosen in case of a multi-chip config 111 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 112 to the chip 1 WBM idle link descriptor idle list 113 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 114 to the chip 2 WBM idle link descriptor idle list 115 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 116 returned to chip 3 WBM idle link descriptor idle list 117 <enum 4 FW_BM> This buffer shall be returned to the FW 118 <enum 5 SW0_BM> This buffer shall be returned to the SW, 119 ring 0 120 <enum 6 SW1_BM> This buffer shall be returned to the SW, 121 ring 1 122 <enum 7 SW2_BM> This buffer shall be returned to the SW, 123 ring 2 124 <enum 8 SW3_BM> This buffer shall be returned to the SW, 125 ring 3 126 <enum 9 SW4_BM> This buffer shall be returned to the SW, 127 ring 4 128 <enum 10 SW5_BM> This buffer shall be returned to the SW, 129 ring 5 130 <enum 11 SW6_BM> This buffer shall be returned to the SW, 131 ring 6 132 133 <legal 0-12> 134 */ 135 136 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 137 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 138 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 139 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 140 141 142 /* Description SW_BUFFER_COOKIE 143 144 Cookie field exclusively used by SW. 145 146 In case of 'NULL' pointer, this field is set to 0 147 148 HW ignores the contents, accept that it passes the programmed 149 value on to other descriptors together with the physical 150 address 151 152 Field can be used by SW to for example associate the buffers 153 physical address with the virtual address 154 The bit definitions as used by SW are within SW HLD specification 155 156 157 NOTE1: 158 The three most significant bits can have a special meaning 159 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 160 and field transmit_bw_restriction is set 161 162 In case of NON punctured transmission: 163 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 164 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 165 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 166 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 167 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 168 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 169 Sw_buffer_cookie[19:18] = 2'b11: reserved 170 171 In case of punctured transmission: 172 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 173 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 174 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 175 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 176 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 177 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 178 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 179 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 180 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 181 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 182 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 183 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 184 Sw_buffer_cookie[19:18] = 2'b11: reserved 185 186 Note: a punctured transmission is indicated by the presence 187 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 188 189 <legal all> 190 */ 191 192 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 193 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 194 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 195 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 196 197 198 /* Description RELEASE_SOURCE_MODULE 199 200 Indicates which module initiated the release of this buffer 201 or descriptor 202 203 <enum 1 release_source_RXDMA> RXDMA released this buffer 204 or descriptor 205 <enum 2 release_source_REO> REO released this buffer or 206 descriptor 207 <enum 5 release_source_FW_RX> FW released this buffer or 208 descriptor 209 <enum 4 release_source_SW_RX> SW released this buffer or 210 descriptor 211 <enum 0 release_source_TQM> DO NOT USE 212 <enum 3 release_source_FW_TX> DO NOT USE 213 <enum 6 release_source_SW_TX> DO NOT USE 214 <legal 0-6> 215 */ 216 217 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 218 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 219 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 220 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 221 222 223 /* Description RESERVED_2A 224 225 This could be different fields depending on the structure. 226 227 <legal all> 228 */ 229 230 #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 231 #define WBM_RELEASE_RING_RESERVED_2A_LSB 3 232 #define WBM_RELEASE_RING_RESERVED_2A_MSB 5 233 #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 234 235 236 /* Description BUFFER_OR_DESC_TYPE 237 238 Consumer: WBM/SW/FW 239 Producer: SW/TQM/RXDMA/REO/SWITCH 240 241 Field only valid when WBM is marked as the return_buffer_manager 242 in the Released_Buffer_address_info 243 244 Indicates that type of buffer or descriptor is being released 245 246 247 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 248 249 <enum 1 msdu_link_descriptor> The address points to an TX 250 MSDU link descriptor 251 <enum 2 mpdu_link_descriptor> The address points to an MPDU 252 link descriptor 253 <enum 3 msdu_ext_descriptor > The address points to an MSDU 254 extension descriptor. 255 In case BM finds this one in a release ring, it passes it 256 on to FW... 257 <enum 4 queue_ext_descriptor> The address points to an TQM 258 queue extension descriptor. WBM should treat this is the 259 same way as a link descriptor. That is, put the 128 byte 260 buffer back in the link buffer idle list. 261 262 TODO: Any restrictions? 263 <legal 0-4> 264 */ 265 266 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 267 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 268 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 269 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 270 271 272 /* Description RESERVED_2B 273 274 This could be different fields depending on the structure. 275 276 <legal all> 277 */ 278 279 #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 280 #define WBM_RELEASE_RING_RESERVED_2B_LSB 9 281 #define WBM_RELEASE_RING_RESERVED_2B_MSB 30 282 #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 283 284 285 /* Description WBM_INTERNAL_ERROR 286 287 Can only be set by WBM. 288 289 Is set when WBM got a buffer pointer but the action was 290 to push it to the idle link descriptor ring or do link related 291 activity 292 OR 293 Is set when WBM got a link buffer pointer but the action 294 was to push it to the buffer descriptor ring 295 296 <legal all> 297 */ 298 299 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 300 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 301 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 302 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 303 304 305 /* Description RESERVED_3A 306 307 This could be different fields depending on the structure. 308 309 <legal all> 310 */ 311 312 #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c 313 #define WBM_RELEASE_RING_RESERVED_3A_LSB 0 314 #define WBM_RELEASE_RING_RESERVED_3A_MSB 31 315 #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff 316 317 318 /* Description RESERVED_4A 319 320 This could be different fields depending on the structure. 321 322 <legal all> 323 */ 324 325 #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 326 #define WBM_RELEASE_RING_RESERVED_4A_LSB 0 327 #define WBM_RELEASE_RING_RESERVED_4A_MSB 31 328 #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff 329 330 331 /* Description RESERVED_5A 332 333 This could be different fields depending on the structure. 334 335 <legal all> 336 */ 337 338 #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 339 #define WBM_RELEASE_RING_RESERVED_5A_LSB 0 340 #define WBM_RELEASE_RING_RESERVED_5A_MSB 31 341 #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff 342 343 344 /* Description RESERVED_6A 345 346 This could be different fields depending on the structure. 347 348 <legal all> 349 */ 350 351 #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 352 #define WBM_RELEASE_RING_RESERVED_6A_LSB 0 353 #define WBM_RELEASE_RING_RESERVED_6A_MSB 31 354 #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff 355 356 357 /* Description RESERVED_7A 358 359 This could be different fields depending on the structure. 360 361 <legal all> 362 */ 363 364 #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c 365 #define WBM_RELEASE_RING_RESERVED_7A_LSB 0 366 #define WBM_RELEASE_RING_RESERVED_7A_MSB 27 367 #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff 368 369 370 /* Description LOOPING_COUNT 371 372 Consumer: WBM/SW/FW 373 Producer: SW/TQM/RXDMA/REO/SWITCH 374 375 If WBM_internal_error is set, this descriptor is sent to 376 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 377 is used to indicate an error code. 378 379 The values reported are documented further in the WBM MLD 380 doc. 381 382 If WBM_internal_error is not set, the following holds. 383 384 A count value that indicates the number of times the producer 385 of entries into the Buffer Manager Ring has looped around 386 the ring. 387 At initialization time, this value is set to 0. On the first 388 loop, this value is set to 1. After the max value is reached 389 allowed by the number of bits for this field, the count 390 value continues with 0 again. 391 392 In case SW is the consumer of the ring entries, it can use 393 this field to figure out up to where the producer of entries 394 has created new entries. This eliminates the need to check 395 where the "head pointer' of the ring is located once the 396 SW starts processing an interrupt indicating that new entries 397 have been put into this ring... 398 399 Also note that SW if it wants only needs to look at the 400 LSB bit of this count value. 401 <legal all> 402 */ 403 404 #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c 405 #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 406 #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 407 #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 408 409 410 411 #endif // WBM_RELEASE_RING 412