1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _WBM_RELEASE_RING_RX_H_ 18 #define _WBM_RELEASE_RING_RX_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_msdu_desc_info.h" 23 #include "rx_mpdu_desc_info.h" 24 #include "buffer_addr_info.h" 25 #define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 26 27 28 struct wbm_release_ring_rx { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info released_buff_or_desc_addr_info; 31 uint32_t release_source_module : 3, // [2:0] 32 bm_action : 3, // [5:3] 33 buffer_or_desc_type : 3, // [8:6] 34 first_msdu_index : 4, // [12:9] 35 reserved_2a : 2, // [14:13] 36 cache_id : 1, // [15:15] 37 cookie_conversion_status : 1, // [16:16] 38 rxdma_push_reason : 2, // [18:17] 39 rxdma_error_code : 5, // [23:19] 40 reo_push_reason : 2, // [25:24] 41 reo_error_code : 5, // [30:26] 42 wbm_internal_error : 1; // [31:31] 43 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 44 struct rx_msdu_desc_info rx_msdu_desc_info_details; 45 uint32_t reserved_6a : 32; // [31:0] 46 uint32_t reserved_7a : 20, // [19:0] 47 ring_id : 8, // [27:20] 48 looping_count : 4; // [31:28] 49 #else 50 struct buffer_addr_info released_buff_or_desc_addr_info; 51 uint32_t wbm_internal_error : 1, // [31:31] 52 reo_error_code : 5, // [30:26] 53 reo_push_reason : 2, // [25:24] 54 rxdma_error_code : 5, // [23:19] 55 rxdma_push_reason : 2, // [18:17] 56 cookie_conversion_status : 1, // [16:16] 57 cache_id : 1, // [15:15] 58 reserved_2a : 2, // [14:13] 59 first_msdu_index : 4, // [12:9] 60 buffer_or_desc_type : 3, // [8:6] 61 bm_action : 3, // [5:3] 62 release_source_module : 3; // [2:0] 63 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 64 struct rx_msdu_desc_info rx_msdu_desc_info_details; 65 uint32_t reserved_6a : 32; // [31:0] 66 uint32_t looping_count : 4, // [31:28] 67 ring_id : 8, // [27:20] 68 reserved_7a : 20; // [19:0] 69 #endif 70 }; 71 72 73 /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO 74 75 Consumer: WBM/SW/FW 76 Producer: SW/TQM/RXDMA/REO/SWITCH 77 78 Details of the physical address of the buffer or link descriptor 79 that is being released. Note that within this descriptor, 80 WBM will look at the 'owner' of the released buffer/descriptor 81 and forward it to SW/FW is WBM is not the owner. 82 */ 83 84 85 /* Description BUFFER_ADDR_31_0 86 87 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 88 descriptor OR Link Descriptor 89 90 In case of 'NULL' pointer, this field is set to 0 91 <legal all> 92 */ 93 94 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 95 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 96 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 97 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 98 99 100 /* Description BUFFER_ADDR_39_32 101 102 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 103 descriptor OR Link Descriptor 104 105 In case of 'NULL' pointer, this field is set to 0 106 <legal all> 107 */ 108 109 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 110 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 111 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 112 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 113 114 115 /* Description RETURN_BUFFER_MANAGER 116 117 Consumer: WBM 118 Producer: SW/FW 119 120 In case of 'NULL' pointer, this field is set to 0 121 122 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 123 descriptor OR link descriptor that is being pointed to 124 shall be returned after the frame has been processed. It 125 is used by WBM for routing purposes. 126 127 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 128 to the WMB buffer idle list 129 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 130 to the WBM idle link descriptor idle list, where the chip 131 0 WBM is chosen in case of a multi-chip config 132 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 133 to the chip 1 WBM idle link descriptor idle list 134 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 135 to the chip 2 WBM idle link descriptor idle list 136 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 137 returned to chip 3 WBM idle link descriptor idle list 138 <enum 4 FW_BM> This buffer shall be returned to the FW 139 <enum 5 SW0_BM> This buffer shall be returned to the SW, 140 ring 0 141 <enum 6 SW1_BM> This buffer shall be returned to the SW, 142 ring 1 143 <enum 7 SW2_BM> This buffer shall be returned to the SW, 144 ring 2 145 <enum 8 SW3_BM> This buffer shall be returned to the SW, 146 ring 3 147 <enum 9 SW4_BM> This buffer shall be returned to the SW, 148 ring 4 149 <enum 10 SW5_BM> This buffer shall be returned to the SW, 150 ring 5 151 <enum 11 SW6_BM> This buffer shall be returned to the SW, 152 ring 6 153 154 <legal 0-12> 155 */ 156 157 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 158 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 159 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 160 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 161 162 163 /* Description SW_BUFFER_COOKIE 164 165 Cookie field exclusively used by SW. 166 167 In case of 'NULL' pointer, this field is set to 0 168 169 HW ignores the contents, accept that it passes the programmed 170 value on to other descriptors together with the physical 171 address 172 173 Field can be used by SW to for example associate the buffers 174 physical address with the virtual address 175 The bit definitions as used by SW are within SW HLD specification 176 177 178 NOTE1: 179 The three most significant bits can have a special meaning 180 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 181 and field transmit_bw_restriction is set 182 183 In case of NON punctured transmission: 184 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 185 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 186 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 187 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 188 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 189 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 190 Sw_buffer_cookie[19:18] = 2'b11: reserved 191 192 In case of punctured transmission: 193 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 194 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 195 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 196 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 197 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 198 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 199 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 200 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 201 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 202 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 203 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 204 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 205 Sw_buffer_cookie[19:18] = 2'b11: reserved 206 207 Note: a punctured transmission is indicated by the presence 208 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 209 210 <legal all> 211 */ 212 213 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 214 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 215 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 216 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 217 218 219 /* Description RELEASE_SOURCE_MODULE 220 221 Indicates which module initiated the release of this buffer 222 or descriptor 223 224 <enum 1 release_source_RXDMA> RXDMA released this buffer 225 or descriptor 226 <enum 2 release_source_REO> REO released this buffer or 227 descriptor 228 <enum 5 release_source_FW_RX> FW released this buffer or 229 descriptor 230 <enum 4 release_source_SW_RX> SW released this buffer or 231 descriptor 232 <enum 0 release_source_TQM> DO NOT USE 233 <enum 3 release_source_FW_TX> DO NOT USE 234 <enum 6 release_source_SW_TX> DO NOT USE 235 <legal 0-6> 236 */ 237 238 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 239 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 240 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 241 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 242 243 244 /* Description BM_ACTION 245 246 Consumer: WBM/SW/FW 247 Producer: SW/TQM/RXDMA/REO/SWITCH 248 249 Field only valid when the field return_buffer_manager in 250 the Released_buff_or_desc_addr_info indicates: 251 WBM_IDLE_BUF_LIST or 252 WBM_IDLE_DESC_LIST 253 254 An MSDU extension descriptor shall never be marked as WBM 255 being the 'owner', and thus WBM will forward it to FW/SW 256 257 258 <enum 0 Put_in_idle_list> Put the buffer or descriptor back 259 in the idle list. In case of MSDU or MDPU link descriptor, 260 BM does not need to check to release any individual MSDU 261 buffers 262 263 <enum 1 release_msdu_list > This BM action can only be used 264 in combination with buffer_or_desc_type being msdu_link_descriptor. 265 Field first_msdu_index points out which MSDU pointer in 266 the MSDU link descriptor is the first of an MPDU that is 267 released. 268 BM shall release all the MSDU buffers linked to this first 269 MSDU buffer pointer. All related MSDU buffer pointer entries 270 shall be set to value 0, which represents the 'NULL" pointer. 271 When all MSDU buffer pointers in the MSDU link descriptor 272 are 'NULL', the MSDU link descriptor itself shall also 273 be released. 274 275 <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 276 277 Put the buffer or descriptor back in the idle list. Only 278 valid in combination with buffer_or_desc_type indicating 279 MDPU_link_descriptor. 280 BM shall release the MPDU link descriptor as well as all 281 MSDUs that are linked to the MPDUs in this descriptor. 282 283 284 TODO: Any restrictions? 285 <legal 0-2> 286 */ 287 288 #define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 289 #define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 290 #define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 291 #define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 292 293 294 /* Description BUFFER_OR_DESC_TYPE 295 296 Consumer: WBM/SW/FW 297 Producer: SW/TQM/RXDMA/REO/SWITCH 298 299 Field only valid when WBM is marked as the return_buffer_manager 300 in the Released_Buffer_address_info 301 302 Indicates that type of buffer or descriptor is being released 303 304 305 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 306 307 <enum 1 msdu_link_descriptor> The address points to an TX 308 MSDU link descriptor 309 <enum 2 mpdu_link_descriptor> The address points to an MPDU 310 link descriptor 311 <enum 3 msdu_ext_descriptor > The address points to an MSDU 312 extension descriptor. 313 In case BM finds this one in a release ring, it passes it 314 on to FW... 315 <enum 4 queue_ext_descriptor> The address points to an TQM 316 queue extension descriptor. WBM should treat this is the 317 same way as a link descriptor. That is, put the 128 byte 318 buffer back in the link buffer idle list. 319 320 TODO: Any restrictions? 321 <legal 0-4> 322 */ 323 324 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 325 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 326 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 327 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 328 329 330 /* Description FIRST_MSDU_INDEX 331 332 Consumer: WBM/SW/FW 333 Producer: SW/TQM/RXDMA/REO/SWITCH 334 335 Field only valid for the bm_action release_msdu_list. 336 337 The index of the first MSDU in an MSDU link descriptor all 338 belonging to the same MPDU. 339 340 TODO: Any restrictions? 341 <legal 0-6> 342 */ 343 344 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 345 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 346 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 347 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 348 349 350 /* Description RESERVED_2A 351 352 <legal 0> 353 */ 354 355 #define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 356 #define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 357 #define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 358 #define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 359 360 361 /* Description CACHE_ID 362 363 Indicates the WBM cache the MSDU was released from 364 <legal all> 365 */ 366 367 #define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 368 #define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 369 #define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 370 #define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 371 372 373 /* Description COOKIE_CONVERSION_STATUS 374 375 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 376 377 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 378 <legal 0> 379 */ 380 381 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 382 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 383 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 384 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 385 386 387 /* Description RXDMA_PUSH_REASON 388 389 Field only valid when Release_source_module is set to release_source_RXDMA 390 391 392 Indicates why rxdma pushed the frame to this ring 393 394 <enum 0 rxdma_error_detected> RXDMA detected an error an 395 pushed this frame to this queue 396 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 397 to this queue per received routing instructions. No error 398 within RXDMA was detected 399 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 400 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 401 set, but instead WBM might just see a NULL pointer in the 402 MSDU link descriptor. This is to be considered a normal 403 condition for this scenario. 404 405 <legal 0 - 2> 406 */ 407 408 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 409 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 410 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 411 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 412 413 414 415 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 416 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 417 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 418 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 419 420 421 /* Description REO_PUSH_REASON 422 423 Field only valid when Release_source_module is set to release_source_REO 424 425 426 Indicates why REO pushed the frame to this release ring 427 428 <enum 0 reo_error_detected> Reo detected an error an pushed 429 this frame to this queue 430 <enum 1 reo_routing_instruction> Reo pushed the frame to 431 this queue per received routing instructions. No error 432 within REO was detected 433 434 <legal 0 - 1> 435 */ 436 437 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 438 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 439 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 440 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 441 442 443 /* Description REO_ERROR_CODE 444 445 Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 446 447 448 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 449 in the REO_ENTRANCE ring is set to 0 450 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 451 bit is NOT set 452 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 453 session having been setup. 454 <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 455 Retry bit set: duplicate frame 456 <enum 4 ba_duplicate> BA session, duplicate frame 457 <enum 5 regular_frame_2k_jump> A normal (management/data 458 frame) received with 2K jump in SN 459 <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 460 SSN 461 <enum 7 regular_frame_OOR> A normal (management/data frame) 462 received with SN falling within the OOR window 463 <enum 8 bar_frame_OOR> A bar received with SSN falling within 464 the OOR window 465 <enum 9 bar_frame_no_ba_session> A bar received without 466 a BA session 467 <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 468 equal to SN 469 <enum 11 pn_check_failed> PN Check Failed packet. 470 <enum 12 2k_error_handling_flag_set> Frame is forwarded 471 as a result of the 'Seq_2k_error_detected_flag' been set 472 in the REO Queue descriptor 473 <enum 13 pn_error_handling_flag_set> Frame is forwarded 474 as a result of the 'pn_error_detected_flag' been set in 475 the REO Queue descriptor 476 <enum 14 queue_descriptor_blocked_set> Frame is forwarded 477 as a result of the queue descriptor(address) being blocked 478 as SW/FW seems to be currently in the process of making 479 updates to this descriptor... 480 481 <legal 0-14> 482 */ 483 484 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 485 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 486 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 487 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 488 489 490 /* Description WBM_INTERNAL_ERROR 491 492 Can only be set by WBM. 493 494 Is set when WBM got a buffer pointer but the action was 495 to push it to the idle link descriptor ring or do link related 496 activity 497 OR 498 Is set when WBM got a link buffer pointer but the action 499 was to push it to the buffer descriptor ring 500 501 <legal all> 502 */ 503 504 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 505 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 506 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 507 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 508 509 510 /* Description RX_MPDU_DESC_INFO_DETAILS 511 512 Consumer: REO/SW/FW 513 Producer: RXDMA 514 515 General information related to the MPDU whose link descriptors 516 are being released from Rx DMA or REO 517 518 When enabled in REO, REO will overwrite this structure to 519 have only the 'Msdu_count' field and 56 bits of the previous 520 PN from 'RX_REO_QUEUE' 521 */ 522 523 524 /* Description MSDU_COUNT 525 526 Consumer: REO/SW/FW 527 Producer: RXDMA 528 529 The number of MSDUs within the MPDU 530 <legal all> 531 */ 532 533 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 534 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 535 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 536 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 537 538 539 /* Description FRAGMENT_FLAG 540 541 Consumer: REO/SW/FW 542 Producer: RXDMA 543 544 When set, this MPDU is a fragment and REO should forward 545 this fragment MPDU to the REO destination ring without 546 any reorder checks, pn checks or bitmap update. This implies 547 that REO is forwarding the pointer to the MSDU link descriptor. 548 The destination ring is coming from a programmable register 549 setting in REO 550 551 <legal all> 552 */ 553 554 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 555 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 556 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 557 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 558 559 560 /* Description MPDU_RETRY_BIT 561 562 Consumer: REO/SW/FW 563 Producer: RXDMA 564 565 The retry bit setting from the MPDU header of the received 566 frame 567 <legal all> 568 */ 569 570 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 571 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 572 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 573 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 574 575 576 /* Description AMPDU_FLAG 577 578 Consumer: REO/SW/FW 579 Producer: RXDMA 580 581 When set, the MPDU was received as part of an A-MPDU. 582 <legal all> 583 */ 584 585 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 586 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 587 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 588 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 589 590 591 /* Description BAR_FRAME 592 593 Consumer: REO/SW/FW 594 Producer: RXDMA 595 596 When set, the received frame is a BAR frame. After processing, 597 this frame shall be pushed to SW or deleted. 598 <legal all> 599 */ 600 601 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 602 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 603 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 604 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 605 606 607 /* Description PN_FIELDS_CONTAIN_VALID_INFO 608 609 Consumer: REO/SW/FW 610 Producer: RXDMA 611 612 Copied here by RXDMA from RX_MPDU_END 613 When not set, REO will Not perform a PN sequence number 614 check 615 */ 616 617 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 618 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 619 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 620 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 621 622 623 /* Description RAW_MPDU 624 625 Field only valid when first_msdu_in_mpdu_flag is set. 626 627 When set, the contents in the MSDU buffer contains a 'RAW' 628 MPDU. This 'RAW' MPDU might be spread out over multiple 629 MSDU buffers. 630 <legal all> 631 */ 632 633 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 634 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 635 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 636 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 637 638 639 /* Description MORE_FRAGMENT_FLAG 640 641 The More Fragment bit setting from the MPDU header of the 642 received frame 643 644 <legal all> 645 */ 646 647 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 648 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 649 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 650 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 651 652 653 /* Description SRC_INFO 654 655 Source (virtual) device/interface info. associated with 656 this peer 657 658 This field gets passed on by REO to PPE in the EDMA descriptor 659 ('REO_TO_PPE_RING'). 660 661 <legal all> 662 */ 663 664 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 665 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 666 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 667 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 668 669 670 /* Description MPDU_QOS_CONTROL_VALID 671 672 When set, the MPDU has a QoS control field. 673 674 In case of ndp or phy_err, this field will never be set. 675 676 <legal all> 677 */ 678 679 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 680 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 681 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 682 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 683 684 685 /* Description TID 686 687 Field only valid when mpdu_qos_control_valid is set 688 689 The TID field in the QoS control field 690 <legal all> 691 */ 692 693 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 694 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 695 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 696 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 697 698 699 /* Description PEER_META_DATA 700 701 Meta data that SW has programmed in the Peer table entry 702 of the transmitting STA. 703 <legal all> 704 */ 705 706 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 707 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 708 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 709 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 710 711 712 /* Description RX_MSDU_DESC_INFO_DETAILS 713 714 Consumer: TQM/SW 715 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 716 717 In case of RXDMA or REO releasing Rx MSDU link descriptors,' 718 WBM fills this field with Rx_msdu_desc_info_details when 719 releasing the MSDUs to SW. 720 */ 721 722 723 /* Description FIRST_MSDU_IN_MPDU_FLAG 724 725 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 726 multiple buffers, this field will be valid in the Last 727 buffer used by the MSDU 728 729 <enum 0 Not_first_msdu> This is not the first MSDU in the 730 MPDU. 731 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 732 733 734 <legal all> 735 */ 736 737 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 738 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 739 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 740 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 741 742 743 /* Description LAST_MSDU_IN_MPDU_FLAG 744 745 Consumer: WBM/REO/SW/FW 746 Producer: RXDMA 747 748 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 749 multiple buffers, this field will be valid in the Last 750 buffer used by the MSDU 751 752 <enum 0 Not_last_msdu> There are more MSDUs linked to this 753 MSDU that belongs to this MPDU 754 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 755 This setting is only allowed in combination with 'Msdu_continuation' 756 set to 0. This implies that when an msdu is spread out over 757 multiple buffers and thus msdu_continuation is set, only 758 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 759 be set. 760 761 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 762 are set, the MPDU that this MSDU belongs to only contains 763 a single MSDU. 764 765 766 <legal all> 767 */ 768 769 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 770 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 771 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 772 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 773 774 775 /* Description MSDU_CONTINUATION 776 777 When set, this MSDU buffer was not able to hold the entire 778 MSDU. The next buffer will therefor contain additional 779 information related to this MSDU. 780 781 <legal all> 782 */ 783 784 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 785 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 786 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 787 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 788 789 790 /* Description MSDU_LENGTH 791 792 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 793 multiple buffers, this field will be valid in the First 794 buffer used by MSDU. 795 796 Full MSDU length in bytes after decapsulation. 797 798 This field is still valid for MPDU frames without A-MSDU. 799 It still represents MSDU length after decapsulation 800 801 Or in case of RAW MPDUs, it indicates the length of the 802 entire MPDU (without FCS field) 803 <legal all> 804 */ 805 806 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 807 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 808 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 809 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 810 811 812 /* Description MSDU_DROP 813 814 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 815 multiple buffers, this field will be valid in the Last 816 buffer used by the MSDU 817 818 When set, REO shall drop this MSDU and not forward it to 819 any other ring... 820 <legal all> 821 */ 822 823 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 824 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 825 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 826 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 827 828 829 /* Description SA_IS_VALID 830 831 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 832 multiple buffers, this field will be valid in the Last 833 buffer used by the MSDU 834 835 Indicates that OLE found a valid SA entry for this MSDU 836 <legal all> 837 */ 838 839 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 840 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 841 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 842 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 843 844 845 /* Description DA_IS_VALID 846 847 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 848 multiple buffers, this field will be valid in the Last 849 buffer used by the MSDU 850 851 Indicates that OLE found a valid DA entry for this MSDU 852 <legal all> 853 */ 854 855 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 856 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 857 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 858 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 859 860 861 /* Description DA_IS_MCBC 862 863 Field Only valid if "da_is_valid" is set 864 865 Indicates the DA address was a Multicast of Broadcast address 866 for this MSDU 867 <legal all> 868 */ 869 870 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 871 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 872 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 873 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 874 875 876 /* Description L3_HEADER_PADDING_MSB 877 878 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 879 as the LSB is always zero) 880 Number of bytes padded to make sure that the L3 header will 881 always start of a Dword boundary 882 <legal all> 883 */ 884 885 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 886 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 887 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 888 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 889 890 891 /* Description TCP_UDP_CHKSUM_FAIL 892 893 Passed on from 'RX_ATTENTION' TLV 894 Indicates that the computed checksum did not match the checksum 895 in the TCP/UDP header. 896 <legal all> 897 */ 898 899 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 900 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 901 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 902 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 903 904 905 /* Description IP_CHKSUM_FAIL 906 907 Passed on from 'RX_ATTENTION' TLV 908 Indicates that the computed checksum did not match the checksum 909 in the IP header. 910 <legal all> 911 */ 912 913 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 914 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 915 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 916 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 917 918 919 /* Description FR_DS 920 921 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 922 TLV 923 Set if the 'from DS' bit is set in the frame control. 924 <legal all> 925 */ 926 927 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 928 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 929 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 930 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 931 932 933 /* Description TO_DS 934 935 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 936 TLV 937 Set if the 'to DS' bit is set in the frame control. 938 <legal all> 939 */ 940 941 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 942 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 943 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 944 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 945 946 947 /* Description INTRA_BSS 948 949 This packet needs intra-BSS routing by SW as the 'vdev_id' 950 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 951 that this MSDU was got in. 952 953 <legal all> 954 */ 955 956 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 957 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 958 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 959 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 960 961 962 /* Description DEST_CHIP_ID 963 964 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 965 to support intra-BSS routing with multi-chip multi-link 966 operation. 967 968 This indicates into which chip's TCL the packet should be 969 queued. 970 971 <legal all> 972 */ 973 974 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 975 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 976 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 977 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 978 979 980 /* Description DECAP_FORMAT 981 982 Indicates the format after decapsulation: 983 984 <enum 0 RAW> No encapsulation 985 <enum 1 Native_WiFi> 986 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 987 988 <enum 3 802_3> Indicate Ethernet 989 990 <legal all> 991 */ 992 993 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 994 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 995 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 996 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 997 998 999 /* Description DEST_CHIP_PMAC_ID 1000 1001 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 1002 to support intra-BSS routing with multi-chip multi-link 1003 operation. 1004 1005 This indicates into which link/'vdev' the packet should 1006 be queued in TCL. 1007 1008 <legal all> 1009 */ 1010 1011 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 1012 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 1013 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 1014 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 1015 1016 1017 /* Description RESERVED_6A 1018 1019 <legal 0> 1020 */ 1021 1022 #define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 1023 #define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 1024 #define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 1025 #define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff 1026 1027 1028 /* Description RESERVED_7A 1029 1030 For debugging, RXDMA and REO may fill the Rx MPDU sequence 1031 number in bits [11:0] and WBM may copy over when it releases 1032 Rx MSDUs. 1033 1034 <legal 0-4095> 1035 */ 1036 1037 #define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c 1038 #define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 1039 #define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 1040 #define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff 1041 1042 1043 /* Description RING_ID 1044 1045 Consumer: TQM/REO/RXDMA/SW 1046 Producer: SRNG (of RXDMA) 1047 1048 For debugging. 1049 This field is filled in by the SRNG module. 1050 It help to identify the ring that is being looked <legal 1051 all> 1052 */ 1053 1054 #define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c 1055 #define WBM_RELEASE_RING_RX_RING_ID_LSB 20 1056 #define WBM_RELEASE_RING_RX_RING_ID_MSB 27 1057 #define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 1058 1059 1060 /* Description LOOPING_COUNT 1061 1062 Consumer: WBM/SW/FW 1063 Producer: SW/TQM/RXDMA/REO/SWITCH 1064 1065 If WBM_internal_error is set, this descriptor is sent to 1066 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 1067 is used to indicate an error code. 1068 1069 The values reported are documented further in the WBM MLD 1070 doc. 1071 1072 If WBM_internal_error is not set, the following holds. 1073 1074 A count value that indicates the number of times the producer 1075 of entries into the Buffer Manager Ring has looped around 1076 the ring. 1077 At initialization time, this value is set to 0. On the first 1078 loop, this value is set to 1. After the max value is reached 1079 allowed by the number of bits for this field, the count 1080 value continues with 0 again. 1081 1082 In case SW is the consumer of the ring entries, it can use 1083 this field to figure out up to where the producer of entries 1084 has created new entries. This eliminates the need to check 1085 where the "head pointer' of the ring is located once the 1086 SW starts processing an interrupt indicating that new entries 1087 have been put into this ring... 1088 1089 Also note that SW if it wants only needs to look at the 1090 LSB bit of this count value. 1091 <legal all> 1092 */ 1093 1094 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 1095 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 1096 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 1097 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 1098 1099 1100 1101 #endif // WBM_RELEASE_RING_RX 1102