xref: /wlan-driver/fw-api/hw/qcn9000/buffer_addr_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _BUFFER_ADDR_INFO_H_
18 #define _BUFFER_ADDR_INFO_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 
23 // ################ START SUMMARY #################
24 //
25 //	Dword	Fields
26 //	0	buffer_addr_31_0[31:0]
27 //	1	buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
28 //
29 // ################ END SUMMARY #################
30 
31 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
32 
33 struct buffer_addr_info {
34              uint32_t buffer_addr_31_0                : 32; //[31:0]
35              uint32_t buffer_addr_39_32               :  8, //[7:0]
36                       return_buffer_manager           :  3, //[10:8]
37                       sw_buffer_cookie                : 21; //[31:11]
38 };
39 
40 /*
41 
42 buffer_addr_31_0
43 
44 			Address (lower 32 bits) of the MSDU buffer OR
45 			MSDU_EXTENSION descriptor OR Link Descriptor
46 
47 
48 
49 			In case of 'NULL' pointer, this field is set to 0
50 
51 			<legal all>
52 
53 buffer_addr_39_32
54 
55 			Address (upper 8 bits) of the MSDU buffer OR
56 			MSDU_EXTENSION descriptor OR Link Descriptor
57 
58 
59 
60 			In case of 'NULL' pointer, this field is set to 0
61 
62 			<legal all>
63 
64 return_buffer_manager
65 
66 			Consumer: WBM
67 
68 			Producer: SW/FW
69 
70 
71 
72 			In case of 'NULL' pointer, this field is set to 0
73 
74 
75 
76 			Indicates to which buffer manager the buffer OR
77 			MSDU_EXTENSION descriptor OR link descriptor that is being
78 			pointed to shall be returned after the frame has been
79 			processed. It is used by WBM for routing purposes.
80 
81 
82 
83 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
84 			to the WMB buffer idle list
85 
86 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
87 			returned to the WMB idle link descriptor idle list
88 
89 			<enum 2 FW_BM> This buffer shall be returned to the FW
90 
91 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
92 			ring 0
93 
94 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
95 			ring 1
96 
97 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
98 			ring 2
99 
100 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
101 			ring 3
102 
103 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
104 			ring 4
105 
106 
107 
108 			<legal all>
109 
110 sw_buffer_cookie
111 
112 			Cookie field exclusively used by SW.
113 
114 
115 
116 			In case of 'NULL' pointer, this field is set to 0
117 
118 
119 
120 			HW ignores the contents, accept that it passes the
121 			programmed value on to other descriptors together with the
122 			physical address
123 
124 
125 
126 			Field can be used by SW to for example associate the
127 			buffers physical address with the virtual address
128 
129 			The bit definitions as used by SW are within SW HLD
130 			specification
131 
132 
133 
134 			NOTE:
135 
136 			The three most significant bits can have a special
137 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
138 			STRUCT, and field transmit_bw_restriction is set
139 
140 
141 
142 			In case of NON punctured transmission:
143 
144 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
145 
146 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
147 
148 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
149 
150 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
151 
152 
153 
154 			In case of punctured transmission:
155 
156 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
157 
158 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
159 
160 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
161 
162 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
163 
164 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
165 
166 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
167 
168 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
169 
170 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
171 
172 
173 
174 			Note: a punctured transmission is indicated by the
175 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
176 			TLV
177 
178 
179 
180 			<legal all>
181 */
182 
183 
184 /* Description		BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
185 
186 			Address (lower 32 bits) of the MSDU buffer OR
187 			MSDU_EXTENSION descriptor OR Link Descriptor
188 
189 
190 
191 			In case of 'NULL' pointer, this field is set to 0
192 
193 			<legal all>
194 */
195 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET                   0x00000000
196 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB                      0
197 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK                     0xffffffff
198 
199 /* Description		BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
200 
201 			Address (upper 8 bits) of the MSDU buffer OR
202 			MSDU_EXTENSION descriptor OR Link Descriptor
203 
204 
205 
206 			In case of 'NULL' pointer, this field is set to 0
207 
208 			<legal all>
209 */
210 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET                  0x00000004
211 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB                     0
212 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK                    0x000000ff
213 
214 /* Description		BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
215 
216 			Consumer: WBM
217 
218 			Producer: SW/FW
219 
220 
221 
222 			In case of 'NULL' pointer, this field is set to 0
223 
224 
225 
226 			Indicates to which buffer manager the buffer OR
227 			MSDU_EXTENSION descriptor OR link descriptor that is being
228 			pointed to shall be returned after the frame has been
229 			processed. It is used by WBM for routing purposes.
230 
231 
232 
233 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
234 			to the WMB buffer idle list
235 
236 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
237 			returned to the WMB idle link descriptor idle list
238 
239 			<enum 2 FW_BM> This buffer shall be returned to the FW
240 
241 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
242 			ring 0
243 
244 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
245 			ring 1
246 
247 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
248 			ring 2
249 
250 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
251 			ring 3
252 
253 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
254 			ring 4
255 
256 
257 
258 			<legal all>
259 */
260 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET              0x00000004
261 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB                 8
262 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK                0x00000700
263 
264 /* Description		BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
265 
266 			Cookie field exclusively used by SW.
267 
268 
269 
270 			In case of 'NULL' pointer, this field is set to 0
271 
272 
273 
274 			HW ignores the contents, accept that it passes the
275 			programmed value on to other descriptors together with the
276 			physical address
277 
278 
279 
280 			Field can be used by SW to for example associate the
281 			buffers physical address with the virtual address
282 
283 			The bit definitions as used by SW are within SW HLD
284 			specification
285 
286 
287 
288 			NOTE:
289 
290 			The three most significant bits can have a special
291 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
292 			STRUCT, and field transmit_bw_restriction is set
293 
294 
295 
296 			In case of NON punctured transmission:
297 
298 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
299 
300 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
301 
302 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
303 
304 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
305 
306 
307 
308 			In case of punctured transmission:
309 
310 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
311 
312 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
313 
314 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
315 
316 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
317 
318 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
319 
320 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
321 
322 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
323 
324 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
325 
326 
327 
328 			Note: a punctured transmission is indicated by the
329 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
330 			TLV
331 
332 
333 
334 			<legal all>
335 */
336 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET                   0x00000004
337 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB                      11
338 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK                     0xfffff800
339 
340 
341 #endif // _BUFFER_ADDR_INFO_H_
342