1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 /////////////////////////////////////////////////////////////////////////////////////////////// 17 // 18 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 7/1/2019 19 // User Name:pbechana 20 // 21 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 22 // 23 /////////////////////////////////////////////////////////////////////////////////////////////// 24 25 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 26 #define __MAC_TCL_REG_SEQ_REG_H__ 27 28 #include "seq_hwio.h" 29 #include "mac_tcl_reg_seq_hwiobase.h" 30 #ifdef SCALE_INCLUDES 31 #include "HALhwio.h" 32 #else 33 #include "msmhwio.h" 34 #endif 35 36 37 /////////////////////////////////////////////////////////////////////////////////////////////// 38 // Register Data for Block MAC_TCL_REG 39 /////////////////////////////////////////////////////////////////////////////////////////////// 40 41 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 42 43 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 44 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 45 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 48 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 49 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 50 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 51 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 52 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 53 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 54 do {\ 55 HWIO_INTLOCK(); \ 56 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 57 HWIO_INTFREE();\ 58 } while (0) 59 60 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 61 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 65 66 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 67 68 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 69 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 70 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 73 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 74 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 75 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 76 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 77 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 78 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 79 do {\ 80 HWIO_INTLOCK(); \ 81 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 82 HWIO_INTFREE();\ 83 } while (0) 84 85 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 86 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 87 88 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 90 91 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 92 93 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 94 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 95 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 98 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 99 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 100 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 101 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 102 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 103 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 104 do {\ 105 HWIO_INTLOCK(); \ 106 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 107 HWIO_INTFREE();\ 108 } while (0) 109 110 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 111 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 112 113 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 115 116 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 117 118 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 119 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 120 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 123 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 124 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 125 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 126 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 127 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 128 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 129 do {\ 130 HWIO_INTLOCK(); \ 131 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 132 HWIO_INTFREE();\ 133 } while (0) 134 135 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 136 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 137 138 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 140 141 //// Register TCL_R0_SW2TCL_CREDIT_RING_CTRL //// 142 143 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) (x+0x00000010) 144 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) (x+0x00000010) 145 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x0003ffe0 146 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_SHFT 5 147 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ 148 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK) 149 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, mask) \ 150 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask) 151 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, val) \ 152 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), val) 153 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x, mask, val) \ 154 do {\ 155 HWIO_INTLOCK(); \ 156 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)); \ 157 HWIO_INTFREE();\ 158 } while (0) 159 160 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 161 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 162 163 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x00000020 164 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 0x5 165 166 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 167 168 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 169 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 170 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x001fffff 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 173 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 174 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 175 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 176 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 177 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 178 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 179 do {\ 180 HWIO_INTLOCK(); \ 181 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 182 HWIO_INTFREE();\ 183 } while (0) 184 185 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x00100000 186 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 0x14 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x00001000 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 0xc 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x00000080 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 0x7 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 226 227 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 229 230 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 232 233 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 234 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 235 236 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 237 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 238 239 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 240 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 241 242 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 243 244 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 245 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 246 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x0000ffff 247 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 248 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 249 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 250 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 251 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 252 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 253 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 254 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 255 do {\ 256 HWIO_INTLOCK(); \ 257 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 258 HWIO_INTFREE();\ 259 } while (0) 260 261 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0x0000c000 262 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 0xe 263 264 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 265 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd 266 267 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 268 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc 269 270 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 271 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 272 273 //// Register TCL_R0_TCL2FW_RING_CTRL //// 274 275 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 276 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 277 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 278 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 279 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 280 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 281 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 282 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 283 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 284 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 285 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 286 do {\ 287 HWIO_INTLOCK(); \ 288 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 289 HWIO_INTFREE();\ 290 } while (0) 291 292 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 293 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 294 295 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 296 297 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 298 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 299 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 300 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 301 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 302 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 303 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 304 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 305 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 306 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 307 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 308 do {\ 309 HWIO_INTLOCK(); \ 310 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 311 HWIO_INTFREE();\ 312 } while (0) 313 314 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 315 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 316 317 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 318 319 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 320 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 321 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 322 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 323 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 324 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 325 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 326 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 327 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 328 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 329 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 330 do {\ 331 HWIO_INTLOCK(); \ 332 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 333 HWIO_INTFREE();\ 334 } while (0) 335 336 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 337 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 338 339 //// Register TCL_R0_GEN_CTRL //// 340 341 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 342 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 343 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb 344 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 345 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 346 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 347 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 348 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 349 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 350 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 351 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 352 do {\ 353 HWIO_INTLOCK(); \ 354 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 355 HWIO_INTFREE();\ 356 } while (0) 357 358 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 359 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 360 361 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 362 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 363 364 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 365 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 366 367 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 368 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 369 370 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 371 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 372 373 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 374 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 375 376 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 377 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 378 379 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 380 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 381 382 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 383 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 384 385 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 386 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 387 388 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 389 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 390 391 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 392 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 393 394 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 395 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 396 397 //// Register TCL_R0_DSCP_TID_MAP_n //// 398 399 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) 400 #define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) 401 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 402 #define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 403 #define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 404 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ 405 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) 406 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ 407 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) 408 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ 409 out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) 410 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ 411 do {\ 412 HWIO_INTLOCK(); \ 413 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ 414 HWIO_INTFREE();\ 415 } while (0) 416 417 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff 418 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 419 420 //// Register TCL_R0_PCP_TID_MAP //// 421 422 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) 423 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) 424 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 425 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 426 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 427 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 428 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 429 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 430 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 431 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 432 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 433 do {\ 434 HWIO_INTLOCK(); \ 435 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 436 HWIO_INTFREE();\ 437 } while (0) 438 439 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 440 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 441 442 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 443 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 444 445 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 446 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 447 448 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 449 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 450 451 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 452 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 453 454 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 455 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 456 457 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 458 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 459 460 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 461 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 462 463 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 464 465 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) 466 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) 467 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 468 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 469 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 470 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 471 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 472 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 473 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 474 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 475 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 476 do {\ 477 HWIO_INTLOCK(); \ 478 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 479 HWIO_INTFREE();\ 480 } while (0) 481 482 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 483 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 484 485 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 486 487 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) 488 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) 489 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 490 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 491 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 492 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 493 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 494 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 495 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 496 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 497 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 498 do {\ 499 HWIO_INTLOCK(); \ 500 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 501 HWIO_INTFREE();\ 502 } while (0) 503 504 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 505 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 506 507 //// Register TCL_R0_ASE_HASH_KEY_64 //// 508 509 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) 510 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) 511 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 512 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 513 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 514 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 515 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 516 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 517 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 518 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 519 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 520 do {\ 521 HWIO_INTLOCK(); \ 522 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 523 HWIO_INTFREE();\ 524 } while (0) 525 526 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 527 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 528 529 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 530 531 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004bc) 532 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004bc) 533 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc 534 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 535 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 536 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 537 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 538 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 539 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 540 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 541 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 542 do {\ 543 HWIO_INTLOCK(); \ 544 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 545 HWIO_INTFREE();\ 546 } while (0) 547 548 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000 549 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17 550 551 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 552 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 553 554 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 555 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 556 557 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 558 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe 559 560 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 561 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 562 563 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 564 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 565 566 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 567 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 568 569 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 570 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 571 572 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 573 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 574 575 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 576 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 577 578 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 579 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 580 581 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 582 583 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c0) 584 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c0) 585 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 586 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 587 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 588 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 589 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 590 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 591 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 592 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 593 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 594 do {\ 595 HWIO_INTLOCK(); \ 596 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 597 HWIO_INTFREE();\ 598 } while (0) 599 600 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 601 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 602 603 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 604 605 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004c4) 606 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004c4) 607 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 608 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 609 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 610 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 611 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 612 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 613 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 614 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 615 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 616 do {\ 617 HWIO_INTLOCK(); \ 618 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 619 HWIO_INTFREE();\ 620 } while (0) 621 622 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 623 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 624 625 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 626 627 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c8) 628 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c8) 629 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 630 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 631 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 632 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 633 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 634 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 635 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 636 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 637 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 638 do {\ 639 HWIO_INTLOCK(); \ 640 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 641 HWIO_INTFREE();\ 642 } while (0) 643 644 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 645 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 646 647 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 648 649 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004cc) 650 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004cc) 651 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 652 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 653 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 654 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 655 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 656 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 657 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 658 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 659 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 660 do {\ 661 HWIO_INTLOCK(); \ 662 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 663 HWIO_INTFREE();\ 664 } while (0) 665 666 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 667 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 668 669 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 670 671 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004d0) 672 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004d0) 673 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 674 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 675 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 676 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 677 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 678 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 679 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 680 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 681 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 682 do {\ 683 HWIO_INTLOCK(); \ 684 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 685 HWIO_INTFREE();\ 686 } while (0) 687 688 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 689 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 690 691 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 692 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 693 694 //// Register TCL_R0_TID_MAP_PRTY //// 695 696 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004d4) 697 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004d4) 698 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 699 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 700 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 701 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 702 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 703 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 704 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 705 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 706 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 707 do {\ 708 HWIO_INTLOCK(); \ 709 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 710 HWIO_INTFREE();\ 711 } while (0) 712 713 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 714 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 715 716 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 717 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 718 719 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 720 721 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000004d8) 722 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000004d8) 723 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 724 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 725 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 726 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 727 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 728 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 729 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 730 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 731 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 732 do {\ 733 HWIO_INTLOCK(); \ 734 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 735 HWIO_INTFREE();\ 736 } while (0) 737 738 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 739 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 740 741 //// Register TCL_R0_WATCHDOG //// 742 743 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000004dc) 744 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000004dc) 745 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 746 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 747 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 748 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 749 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 750 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 751 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 752 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 753 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 754 do {\ 755 HWIO_INTLOCK(); \ 756 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 757 HWIO_INTFREE();\ 758 } while (0) 759 760 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 761 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 762 763 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 764 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 765 766 //// Register TCL_R0_CLKGATE_DISABLE //// 767 768 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x000004e0) 769 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x000004e0) 770 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 771 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 772 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 773 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 774 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 775 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 776 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 777 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 778 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 779 do {\ 780 HWIO_INTLOCK(); \ 781 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 782 HWIO_INTFREE();\ 783 } while (0) 784 785 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 786 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 787 788 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 789 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 790 791 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 792 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 793 794 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 795 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 796 797 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 798 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 799 800 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 801 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 802 803 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 804 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 805 806 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 807 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 808 809 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 810 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 811 812 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 813 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 814 815 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 816 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 817 818 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 819 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 820 821 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 822 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 823 824 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 825 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 826 827 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 828 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 829 830 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 831 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 832 833 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 834 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 835 836 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 837 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 838 839 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 840 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 841 842 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 843 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 844 845 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 846 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 847 848 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 849 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 850 851 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 852 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 853 854 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 855 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 856 857 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 858 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 859 860 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 861 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 862 863 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 864 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 865 866 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 867 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 868 869 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 870 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 871 872 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 873 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 874 875 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_BMSK 0x00000002 876 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_SHFT 0x1 877 878 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 879 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 880 881 //// Register TCL_R0_CREDIT_COUNT //// 882 883 #define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) (x+0x000004e4) 884 #define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) (x+0x000004e4) 885 #define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x0001ffff 886 #define HWIO_TCL_R0_CREDIT_COUNT_SHFT 0 887 #define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \ 888 in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CREDIT_COUNT_RMSK) 889 #define HWIO_TCL_R0_CREDIT_COUNT_INM(x, mask) \ 890 in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask) 891 #define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, val) \ 892 out_dword( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), val) 893 #define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x, mask, val) \ 894 do {\ 895 HWIO_INTLOCK(); \ 896 out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CREDIT_COUNT_IN(x)); \ 897 HWIO_INTFREE();\ 898 } while (0) 899 900 #define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x00010000 901 #define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 0x10 902 903 #define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0x0000ffff 904 #define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0x0 905 906 //// Register TCL_R0_CURRENT_CREDIT_COUNT //// 907 908 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) (x+0x000004e8) 909 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) (x+0x000004e8) 910 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0x0000ffff 911 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_SHFT 0 912 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \ 913 in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK) 914 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, mask) \ 915 in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask) 916 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUT(x, val) \ 917 out_dword( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), val) 918 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUTM(x, mask, val) \ 919 do {\ 920 HWIO_INTLOCK(); \ 921 out_dword_masked_ns(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x)); \ 922 HWIO_INTFREE();\ 923 } while (0) 924 925 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0x0000ffff 926 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0x0 927 928 //// Register TCL_R0_S_PARE_REGISTER //// 929 930 #define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) (x+0x000004ec) 931 #define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) (x+0x000004ec) 932 #define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff 933 #define HWIO_TCL_R0_S_PARE_REGISTER_SHFT 0 934 #define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ 935 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), HWIO_TCL_R0_S_PARE_REGISTER_RMSK) 936 #define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, mask) \ 937 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask) 938 #define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, val) \ 939 out_dword( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), val) 940 #define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x, mask, val) \ 941 do {\ 942 HWIO_INTLOCK(); \ 943 out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R0_S_PARE_REGISTER_IN(x)); \ 944 HWIO_INTFREE();\ 945 } while (0) 946 947 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff 948 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0 949 950 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 951 952 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000004f0) 953 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000004f0) 954 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 955 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 956 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 957 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 958 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 959 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 960 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 961 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 962 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 963 do {\ 964 HWIO_INTLOCK(); \ 965 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 966 HWIO_INTFREE();\ 967 } while (0) 968 969 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 970 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 971 972 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 973 974 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000004f4) 975 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000004f4) 976 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff 977 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 978 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 979 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 980 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 981 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 982 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 983 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 984 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 985 do {\ 986 HWIO_INTLOCK(); \ 987 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 988 HWIO_INTFREE();\ 989 } while (0) 990 991 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 992 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 993 994 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 995 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 996 997 //// Register TCL_R0_SW2TCL1_RING_ID //// 998 999 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000004f8) 1000 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000004f8) 1001 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1002 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1003 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1004 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1005 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1006 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1007 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1008 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1009 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1010 do {\ 1011 HWIO_INTLOCK(); \ 1012 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1013 HWIO_INTFREE();\ 1014 } while (0) 1015 1016 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1017 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1018 1019 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1020 1021 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000004fc) 1022 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000004fc) 1023 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1024 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1025 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1026 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1027 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1028 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1029 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1030 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1031 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1032 do {\ 1033 HWIO_INTLOCK(); \ 1034 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1035 HWIO_INTFREE();\ 1036 } while (0) 1037 1038 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1039 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1040 1041 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1042 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1043 1044 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1045 1046 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x00000500) 1047 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x00000500) 1048 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1049 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1050 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1051 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1052 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1053 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1054 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1055 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1056 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1057 do {\ 1058 HWIO_INTLOCK(); \ 1059 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1060 HWIO_INTFREE();\ 1061 } while (0) 1062 1063 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1064 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1065 1066 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1067 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1068 1069 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1070 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1071 1072 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1073 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1074 1075 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1076 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1077 1078 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1079 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1080 1081 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1082 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1083 1084 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1085 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1086 1087 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1088 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1089 1090 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1091 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1092 1093 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1094 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1095 1096 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1097 1098 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000050c) 1099 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000050c) 1100 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1101 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1102 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1103 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1104 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1105 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1106 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1107 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1108 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1109 do {\ 1110 HWIO_INTLOCK(); \ 1111 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1112 HWIO_INTFREE();\ 1113 } while (0) 1114 1115 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1116 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1117 1118 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1119 1120 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000510) 1121 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000510) 1122 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1123 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1124 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1125 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1126 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1127 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1128 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1129 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1130 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1131 do {\ 1132 HWIO_INTLOCK(); \ 1133 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1134 HWIO_INTFREE();\ 1135 } while (0) 1136 1137 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1138 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1139 1140 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1141 1142 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000520) 1143 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000520) 1144 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1145 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1146 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1147 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1148 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1149 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1150 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1151 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1152 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1153 do {\ 1154 HWIO_INTLOCK(); \ 1155 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1156 HWIO_INTFREE();\ 1157 } while (0) 1158 1159 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1160 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1161 1162 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1163 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1164 1165 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1166 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1167 1168 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1169 1170 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000524) 1171 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000524) 1172 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1173 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1174 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1175 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1176 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1177 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1178 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1179 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1180 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1181 do {\ 1182 HWIO_INTLOCK(); \ 1183 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1184 HWIO_INTFREE();\ 1185 } while (0) 1186 1187 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1188 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1189 1190 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1191 1192 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000528) 1193 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000528) 1194 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1195 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1196 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1197 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1198 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1199 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1200 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1201 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1202 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1203 do {\ 1204 HWIO_INTLOCK(); \ 1205 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1206 HWIO_INTFREE();\ 1207 } while (0) 1208 1209 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1210 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1211 1212 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1213 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1214 1215 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1216 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1217 1218 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1219 1220 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000052c) 1221 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000052c) 1222 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1223 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1224 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1225 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1226 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1227 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1228 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1229 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1230 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1231 do {\ 1232 HWIO_INTLOCK(); \ 1233 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1234 HWIO_INTFREE();\ 1235 } while (0) 1236 1237 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1238 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1239 1240 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1241 1242 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000530) 1243 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000530) 1244 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1245 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1246 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1247 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1248 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1249 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1250 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1251 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1252 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1253 do {\ 1254 HWIO_INTLOCK(); \ 1255 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1256 HWIO_INTFREE();\ 1257 } while (0) 1258 1259 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1260 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1261 1262 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1263 1264 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000534) 1265 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000534) 1266 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1267 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1268 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1269 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1270 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1271 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1272 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1273 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1274 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1275 do {\ 1276 HWIO_INTLOCK(); \ 1277 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1278 HWIO_INTFREE();\ 1279 } while (0) 1280 1281 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1282 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1283 1284 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1285 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1286 1287 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1288 1289 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000538) 1290 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000538) 1291 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1292 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1293 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1294 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1295 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1296 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1297 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1298 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1299 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1300 do {\ 1301 HWIO_INTLOCK(); \ 1302 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1303 HWIO_INTFREE();\ 1304 } while (0) 1305 1306 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1307 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1308 1309 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1310 1311 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000053c) 1312 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000053c) 1313 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1314 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1315 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1316 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1317 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1318 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1319 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1320 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1321 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1322 do {\ 1323 HWIO_INTLOCK(); \ 1324 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1325 HWIO_INTFREE();\ 1326 } while (0) 1327 1328 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1329 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1330 1331 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1332 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1333 1334 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1335 1336 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000540) 1337 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000540) 1338 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1339 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1340 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1341 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1342 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1343 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1344 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1345 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1346 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1347 do {\ 1348 HWIO_INTLOCK(); \ 1349 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1350 HWIO_INTFREE();\ 1351 } while (0) 1352 1353 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1354 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1355 1356 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1357 1358 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000544) 1359 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000544) 1360 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1361 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1362 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1363 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1364 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1365 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1366 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1367 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1368 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1369 do {\ 1370 HWIO_INTLOCK(); \ 1371 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1372 HWIO_INTFREE();\ 1373 } while (0) 1374 1375 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1376 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1377 1378 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 1379 1380 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x00000548) 1381 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x00000548) 1382 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 1383 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 1384 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 1385 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 1386 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 1387 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 1388 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 1389 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 1390 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 1391 do {\ 1392 HWIO_INTLOCK(); \ 1393 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 1394 HWIO_INTFREE();\ 1395 } while (0) 1396 1397 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1398 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1399 1400 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 1401 1402 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x0000054c) 1403 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x0000054c) 1404 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff 1405 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 1406 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 1407 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 1408 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 1409 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 1410 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 1411 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 1412 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 1413 do {\ 1414 HWIO_INTLOCK(); \ 1415 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 1416 HWIO_INTFREE();\ 1417 } while (0) 1418 1419 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1420 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1421 1422 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1423 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1424 1425 //// Register TCL_R0_SW2TCL2_RING_ID //// 1426 1427 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000550) 1428 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000550) 1429 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 1430 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 1431 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 1432 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 1433 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 1434 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 1435 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 1436 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 1437 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 1438 do {\ 1439 HWIO_INTLOCK(); \ 1440 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 1441 HWIO_INTFREE();\ 1442 } while (0) 1443 1444 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1445 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 1446 1447 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 1448 1449 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000554) 1450 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000554) 1451 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 1452 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 1453 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 1454 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 1455 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 1456 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 1457 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 1458 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 1459 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 1460 do {\ 1461 HWIO_INTLOCK(); \ 1462 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 1463 HWIO_INTFREE();\ 1464 } while (0) 1465 1466 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1467 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1468 1469 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1470 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1471 1472 //// Register TCL_R0_SW2TCL2_RING_MISC //// 1473 1474 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x00000558) 1475 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x00000558) 1476 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 1477 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 1478 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 1479 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 1480 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 1481 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 1482 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 1483 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 1484 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 1485 do {\ 1486 HWIO_INTLOCK(); \ 1487 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 1488 HWIO_INTFREE();\ 1489 } while (0) 1490 1491 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1492 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1493 1494 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1495 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1496 1497 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1498 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1499 1500 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1501 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1502 1503 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1504 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1505 1506 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1507 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1508 1509 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1510 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1511 1512 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1513 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1514 1515 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1516 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 1517 1518 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1519 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1520 1521 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1522 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1523 1524 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 1525 1526 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000564) 1527 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000564) 1528 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1529 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 1530 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 1531 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 1532 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 1533 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 1534 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 1535 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 1536 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1537 do {\ 1538 HWIO_INTLOCK(); \ 1539 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 1540 HWIO_INTFREE();\ 1541 } while (0) 1542 1543 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1544 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1545 1546 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 1547 1548 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000568) 1549 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000568) 1550 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1551 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 1552 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 1553 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 1554 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 1555 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 1556 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 1557 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 1558 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1559 do {\ 1560 HWIO_INTLOCK(); \ 1561 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 1562 HWIO_INTFREE();\ 1563 } while (0) 1564 1565 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1566 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1567 1568 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 1569 1570 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000578) 1571 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000578) 1572 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1573 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1574 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1575 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1576 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1577 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1578 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1579 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1580 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1581 do {\ 1582 HWIO_INTLOCK(); \ 1583 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1584 HWIO_INTFREE();\ 1585 } while (0) 1586 1587 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1588 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1589 1590 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1591 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1592 1593 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1594 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1595 1596 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 1597 1598 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000057c) 1599 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000057c) 1600 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1601 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1602 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1603 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1604 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1605 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1606 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1607 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1608 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1609 do {\ 1610 HWIO_INTLOCK(); \ 1611 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1612 HWIO_INTFREE();\ 1613 } while (0) 1614 1615 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1616 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1617 1618 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 1619 1620 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000580) 1621 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000580) 1622 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1623 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 1624 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 1625 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 1626 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1627 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1628 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1629 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1630 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1631 do {\ 1632 HWIO_INTLOCK(); \ 1633 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1634 HWIO_INTFREE();\ 1635 } while (0) 1636 1637 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1638 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1639 1640 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1641 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1642 1643 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1644 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1645 1646 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 1647 1648 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000584) 1649 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000584) 1650 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1651 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1652 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1653 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1654 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1655 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1656 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1657 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1658 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1659 do {\ 1660 HWIO_INTLOCK(); \ 1661 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1662 HWIO_INTFREE();\ 1663 } while (0) 1664 1665 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1666 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1667 1668 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 1669 1670 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000588) 1671 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000588) 1672 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1673 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1674 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1675 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1676 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1677 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1678 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1679 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1680 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1681 do {\ 1682 HWIO_INTLOCK(); \ 1683 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1684 HWIO_INTFREE();\ 1685 } while (0) 1686 1687 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1688 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1689 1690 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 1691 1692 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000058c) 1693 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000058c) 1694 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1695 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1696 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1697 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1698 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1699 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1700 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1701 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1702 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1703 do {\ 1704 HWIO_INTLOCK(); \ 1705 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1706 HWIO_INTFREE();\ 1707 } while (0) 1708 1709 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1710 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1711 1712 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1713 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1714 1715 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 1716 1717 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000590) 1718 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000590) 1719 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1720 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 1721 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 1722 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 1723 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1724 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1725 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1726 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 1727 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1728 do {\ 1729 HWIO_INTLOCK(); \ 1730 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 1731 HWIO_INTFREE();\ 1732 } while (0) 1733 1734 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1735 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1736 1737 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 1738 1739 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000594) 1740 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000594) 1741 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1742 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 1743 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 1744 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 1745 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1746 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1747 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1748 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 1749 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1750 do {\ 1751 HWIO_INTLOCK(); \ 1752 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 1753 HWIO_INTFREE();\ 1754 } while (0) 1755 1756 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1757 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1758 1759 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1760 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1761 1762 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 1763 1764 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x00000598) 1765 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x00000598) 1766 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 1767 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 1768 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 1769 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 1770 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 1771 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 1772 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 1773 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 1774 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1775 do {\ 1776 HWIO_INTLOCK(); \ 1777 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 1778 HWIO_INTFREE();\ 1779 } while (0) 1780 1781 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1782 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 1783 1784 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 1785 1786 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000059c) 1787 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000059c) 1788 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1789 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 1790 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 1791 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 1792 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1793 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1794 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1795 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1796 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1797 do {\ 1798 HWIO_INTLOCK(); \ 1799 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1800 HWIO_INTFREE();\ 1801 } while (0) 1802 1803 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1804 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1805 1806 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 1807 1808 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x000005a0) 1809 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x000005a0) 1810 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 1811 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 1812 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 1813 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 1814 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 1815 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 1816 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 1817 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 1818 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 1819 do {\ 1820 HWIO_INTLOCK(); \ 1821 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 1822 HWIO_INTFREE();\ 1823 } while (0) 1824 1825 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1826 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1827 1828 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 1829 1830 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x000005a4) 1831 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x000005a4) 1832 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff 1833 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 1834 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 1835 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 1836 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 1837 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 1838 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 1839 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 1840 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 1841 do {\ 1842 HWIO_INTLOCK(); \ 1843 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 1844 HWIO_INTFREE();\ 1845 } while (0) 1846 1847 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1848 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1849 1850 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1851 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1852 1853 //// Register TCL_R0_SW2TCL3_RING_ID //// 1854 1855 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x000005a8) 1856 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x000005a8) 1857 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 1858 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 1859 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 1860 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 1861 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 1862 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 1863 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 1864 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 1865 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 1866 do {\ 1867 HWIO_INTLOCK(); \ 1868 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 1869 HWIO_INTFREE();\ 1870 } while (0) 1871 1872 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1873 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 1874 1875 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 1876 1877 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x000005ac) 1878 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x000005ac) 1879 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 1880 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 1881 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 1882 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 1883 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 1884 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 1885 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 1886 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 1887 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 1888 do {\ 1889 HWIO_INTLOCK(); \ 1890 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 1891 HWIO_INTFREE();\ 1892 } while (0) 1893 1894 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1895 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1896 1897 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1898 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1899 1900 //// Register TCL_R0_SW2TCL3_RING_MISC //// 1901 1902 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x000005b0) 1903 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x000005b0) 1904 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 1905 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 1906 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 1907 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 1908 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 1909 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 1910 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 1911 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 1912 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 1913 do {\ 1914 HWIO_INTLOCK(); \ 1915 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 1916 HWIO_INTFREE();\ 1917 } while (0) 1918 1919 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1920 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 1921 1922 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1923 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1924 1925 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1926 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1927 1928 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1929 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1930 1931 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1932 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 1933 1934 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1935 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1936 1937 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1938 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1939 1940 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1941 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1942 1943 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1944 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 1945 1946 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1947 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1948 1949 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1950 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1951 1952 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 1953 1954 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x000005bc) 1955 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x000005bc) 1956 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 1957 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 1958 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 1959 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 1960 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 1961 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 1962 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 1963 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 1964 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1965 do {\ 1966 HWIO_INTLOCK(); \ 1967 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 1968 HWIO_INTFREE();\ 1969 } while (0) 1970 1971 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1972 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1973 1974 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 1975 1976 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x000005c0) 1977 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x000005c0) 1978 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 1979 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 1980 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 1981 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 1982 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 1983 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 1984 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 1985 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 1986 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1987 do {\ 1988 HWIO_INTLOCK(); \ 1989 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 1990 HWIO_INTFREE();\ 1991 } while (0) 1992 1993 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1994 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1995 1996 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 1997 1998 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000005d0) 1999 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000005d0) 2000 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2001 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2002 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2003 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2004 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2005 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2006 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2007 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2008 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2009 do {\ 2010 HWIO_INTLOCK(); \ 2011 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2012 HWIO_INTFREE();\ 2013 } while (0) 2014 2015 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2016 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2017 2018 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2019 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2020 2021 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2022 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2023 2024 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2025 2026 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000005d4) 2027 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000005d4) 2028 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2029 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2030 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2031 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2032 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2033 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2034 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2035 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2036 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2037 do {\ 2038 HWIO_INTLOCK(); \ 2039 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2040 HWIO_INTFREE();\ 2041 } while (0) 2042 2043 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2044 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2045 2046 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2047 2048 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000005d8) 2049 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000005d8) 2050 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2051 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2052 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2053 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2054 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2055 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2056 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2057 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2058 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2059 do {\ 2060 HWIO_INTLOCK(); \ 2061 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2062 HWIO_INTFREE();\ 2063 } while (0) 2064 2065 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2066 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2067 2068 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2069 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2070 2071 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2072 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2073 2074 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2075 2076 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000005dc) 2077 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000005dc) 2078 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2079 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2080 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2081 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2082 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2083 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2084 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2085 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2086 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2087 do {\ 2088 HWIO_INTLOCK(); \ 2089 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2090 HWIO_INTFREE();\ 2091 } while (0) 2092 2093 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2094 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2095 2096 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2097 2098 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000005e0) 2099 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000005e0) 2100 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2101 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2102 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2103 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2104 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2105 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2106 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2107 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2108 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2109 do {\ 2110 HWIO_INTLOCK(); \ 2111 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2112 HWIO_INTFREE();\ 2113 } while (0) 2114 2115 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2116 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2117 2118 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2119 2120 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000005e4) 2121 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000005e4) 2122 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2123 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2124 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2125 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2126 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2127 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2128 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2129 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2130 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2131 do {\ 2132 HWIO_INTLOCK(); \ 2133 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2134 HWIO_INTFREE();\ 2135 } while (0) 2136 2137 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2138 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2139 2140 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2141 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2142 2143 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2144 2145 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000005e8) 2146 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000005e8) 2147 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2148 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2149 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2150 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2151 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2152 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2153 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2154 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2155 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2156 do {\ 2157 HWIO_INTLOCK(); \ 2158 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2159 HWIO_INTFREE();\ 2160 } while (0) 2161 2162 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2163 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2164 2165 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2166 2167 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000005ec) 2168 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000005ec) 2169 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2170 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2171 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2172 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2173 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2174 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2175 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2176 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2177 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2178 do {\ 2179 HWIO_INTLOCK(); \ 2180 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2181 HWIO_INTFREE();\ 2182 } while (0) 2183 2184 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2185 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2186 2187 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2188 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2189 2190 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2191 2192 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x000005f0) 2193 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x000005f0) 2194 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2195 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2196 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2197 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2198 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2199 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2200 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2201 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2202 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2203 do {\ 2204 HWIO_INTLOCK(); \ 2205 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2206 HWIO_INTFREE();\ 2207 } while (0) 2208 2209 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2210 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2211 2212 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2213 2214 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005f4) 2215 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005f4) 2216 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2217 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2218 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2219 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2220 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2221 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2222 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2223 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2224 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2225 do {\ 2226 HWIO_INTLOCK(); \ 2227 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2228 HWIO_INTFREE();\ 2229 } while (0) 2230 2231 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2232 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2233 2234 //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB //// 2235 2236 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x000005f8) 2237 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x000005f8) 2238 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff 2239 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_SHFT 0 2240 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ 2241 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK) 2242 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, mask) \ 2243 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask) 2244 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, val) \ 2245 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), val) 2246 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x, mask, val) \ 2247 do {\ 2248 HWIO_INTLOCK(); \ 2249 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)); \ 2250 HWIO_INTFREE();\ 2251 } while (0) 2252 2253 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2254 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2255 2256 //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB //// 2257 2258 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x000005fc) 2259 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x000005fc) 2260 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0x0fffffff 2261 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_SHFT 0 2262 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ 2263 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK) 2264 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, mask) \ 2265 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask) 2266 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, val) \ 2267 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), val) 2268 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x, mask, val) \ 2269 do {\ 2270 HWIO_INTLOCK(); \ 2271 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)); \ 2272 HWIO_INTFREE();\ 2273 } while (0) 2274 2275 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2276 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2277 2278 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2279 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2280 2281 //// Register TCL_R0_SW2TCL_CREDIT_RING_ID //// 2282 2283 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x00000600) 2284 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x00000600) 2285 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0x000000ff 2286 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_SHFT 0 2287 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ 2288 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK) 2289 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, mask) \ 2290 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask) 2291 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, val) \ 2292 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), val) 2293 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x, mask, val) \ 2294 do {\ 2295 HWIO_INTLOCK(); \ 2296 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)); \ 2297 HWIO_INTFREE();\ 2298 } while (0) 2299 2300 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2301 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0x0 2302 2303 //// Register TCL_R0_SW2TCL_CREDIT_RING_STATUS //// 2304 2305 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x00000604) 2306 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x00000604) 2307 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff 2308 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_SHFT 0 2309 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ 2310 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK) 2311 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, mask) \ 2312 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask) 2313 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUT(x, val) \ 2314 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), val) 2315 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUTM(x, mask, val) \ 2316 do {\ 2317 HWIO_INTLOCK(); \ 2318 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x)); \ 2319 HWIO_INTFREE();\ 2320 } while (0) 2321 2322 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2323 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2324 2325 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2326 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2327 2328 //// Register TCL_R0_SW2TCL_CREDIT_RING_MISC //// 2329 2330 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x00000608) 2331 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x00000608) 2332 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x003fffff 2333 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SHFT 0 2334 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ 2335 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK) 2336 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, mask) \ 2337 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask) 2338 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, val) \ 2339 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), val) 2340 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x, mask, val) \ 2341 do {\ 2342 HWIO_INTLOCK(); \ 2343 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)); \ 2344 HWIO_INTFREE();\ 2345 } while (0) 2346 2347 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2348 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 0xe 2349 2350 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2351 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2352 2353 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2354 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2355 2356 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2357 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2358 2359 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2360 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 0x6 2361 2362 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2363 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2364 2365 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2366 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2367 2368 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2369 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2370 2371 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2372 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 0x2 2373 2374 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2375 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2376 2377 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2378 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2379 2380 //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB //// 2381 2382 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000614) 2383 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000614) 2384 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff 2385 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_SHFT 0 2386 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ 2387 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK) 2388 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, mask) \ 2389 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask) 2390 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, val) \ 2391 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), val) 2392 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2393 do {\ 2394 HWIO_INTLOCK(); \ 2395 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)); \ 2396 HWIO_INTFREE();\ 2397 } while (0) 2398 2399 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2400 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2401 2402 //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB //// 2403 2404 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000618) 2405 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000618) 2406 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0x000000ff 2407 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_SHFT 0 2408 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ 2409 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK) 2410 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, mask) \ 2411 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask) 2412 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, val) \ 2413 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), val) 2414 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2415 do {\ 2416 HWIO_INTLOCK(); \ 2417 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)); \ 2418 HWIO_INTFREE();\ 2419 } while (0) 2420 2421 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2422 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2423 2424 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 //// 2425 2426 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000628) 2427 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000628) 2428 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2429 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2430 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2431 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2432 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2433 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2434 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2435 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2436 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2437 do {\ 2438 HWIO_INTLOCK(); \ 2439 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2440 HWIO_INTFREE();\ 2441 } while (0) 2442 2443 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2444 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2445 2446 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2447 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2448 2449 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2450 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2451 2452 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 //// 2453 2454 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000062c) 2455 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000062c) 2456 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2457 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2458 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2459 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2460 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2461 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2462 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2463 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2464 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2465 do {\ 2466 HWIO_INTLOCK(); \ 2467 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2468 HWIO_INTFREE();\ 2469 } while (0) 2470 2471 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2472 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2473 2474 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS //// 2475 2476 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000630) 2477 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000630) 2478 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2479 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_SHFT 0 2480 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ 2481 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK) 2482 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2483 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2484 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2485 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2486 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2487 do {\ 2488 HWIO_INTLOCK(); \ 2489 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x)); \ 2490 HWIO_INTFREE();\ 2491 } while (0) 2492 2493 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2494 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2495 2496 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2497 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2498 2499 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2500 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2501 2502 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER //// 2503 2504 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000634) 2505 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000634) 2506 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2507 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2508 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2509 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2510 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2511 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2512 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2513 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2514 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2515 do {\ 2516 HWIO_INTLOCK(); \ 2517 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2518 HWIO_INTFREE();\ 2519 } while (0) 2520 2521 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2522 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2523 2524 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER //// 2525 2526 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000638) 2527 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000638) 2528 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2529 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2530 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2531 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2532 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2533 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2534 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2535 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2536 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2537 do {\ 2538 HWIO_INTLOCK(); \ 2539 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2540 HWIO_INTFREE();\ 2541 } while (0) 2542 2543 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2544 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2545 2546 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS //// 2547 2548 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000063c) 2549 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000063c) 2550 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2551 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2552 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2553 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2554 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2555 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2556 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2557 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2558 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2559 do {\ 2560 HWIO_INTLOCK(); \ 2561 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2562 HWIO_INTFREE();\ 2563 } while (0) 2564 2565 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2566 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2567 2568 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2569 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2570 2571 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB //// 2572 2573 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000640) 2574 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000640) 2575 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2576 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_SHFT 0 2577 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ 2578 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK) 2579 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, mask) \ 2580 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask) 2581 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, val) \ 2582 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), val) 2583 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2584 do {\ 2585 HWIO_INTLOCK(); \ 2586 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)); \ 2587 HWIO_INTFREE();\ 2588 } while (0) 2589 2590 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2591 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2592 2593 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB //// 2594 2595 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000644) 2596 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000644) 2597 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2598 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_SHFT 0 2599 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ 2600 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK) 2601 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, mask) \ 2602 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask) 2603 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, val) \ 2604 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), val) 2605 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2606 do {\ 2607 HWIO_INTLOCK(); \ 2608 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)); \ 2609 HWIO_INTFREE();\ 2610 } while (0) 2611 2612 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2613 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2614 2615 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2616 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2617 2618 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA //// 2619 2620 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x00000648) 2621 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x00000648) 2622 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff 2623 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_SHFT 0 2624 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ 2625 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK) 2626 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, mask) \ 2627 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask) 2628 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, val) \ 2629 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), val) 2630 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x, mask, val) \ 2631 do {\ 2632 HWIO_INTLOCK(); \ 2633 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)); \ 2634 HWIO_INTFREE();\ 2635 } while (0) 2636 2637 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2638 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0x0 2639 2640 //// Register TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET //// 2641 2642 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000064c) 2643 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000064c) 2644 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2645 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_SHFT 0 2646 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ 2647 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK) 2648 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2649 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2650 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2651 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2652 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2653 do {\ 2654 HWIO_INTLOCK(); \ 2655 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)); \ 2656 HWIO_INTFREE();\ 2657 } while (0) 2658 2659 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2660 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2661 2662 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 2663 2664 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000650) 2665 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000650) 2666 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 2667 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 2668 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 2669 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 2670 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 2671 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 2672 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 2673 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 2674 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 2675 do {\ 2676 HWIO_INTLOCK(); \ 2677 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 2678 HWIO_INTFREE();\ 2679 } while (0) 2680 2681 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2682 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2683 2684 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 2685 2686 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000654) 2687 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000654) 2688 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 2689 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 2690 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 2691 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 2692 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 2693 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 2694 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 2695 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 2696 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 2697 do {\ 2698 HWIO_INTLOCK(); \ 2699 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 2700 HWIO_INTFREE();\ 2701 } while (0) 2702 2703 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2704 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2705 2706 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2707 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2708 2709 //// Register TCL_R0_FW2TCL1_RING_ID //// 2710 2711 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x00000658) 2712 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x00000658) 2713 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 2714 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 2715 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 2716 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 2717 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 2718 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 2719 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 2720 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 2721 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 2722 do {\ 2723 HWIO_INTLOCK(); \ 2724 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 2725 HWIO_INTFREE();\ 2726 } while (0) 2727 2728 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2729 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 2730 2731 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 2732 2733 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x0000065c) 2734 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x0000065c) 2735 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 2736 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 2737 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 2738 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 2739 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 2740 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 2741 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 2742 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 2743 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 2744 do {\ 2745 HWIO_INTLOCK(); \ 2746 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 2747 HWIO_INTFREE();\ 2748 } while (0) 2749 2750 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2751 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2752 2753 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2754 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2755 2756 //// Register TCL_R0_FW2TCL1_RING_MISC //// 2757 2758 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000660) 2759 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000660) 2760 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 2761 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 2762 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 2763 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 2764 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 2765 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 2766 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 2767 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 2768 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 2769 do {\ 2770 HWIO_INTLOCK(); \ 2771 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 2772 HWIO_INTFREE();\ 2773 } while (0) 2774 2775 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2776 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2777 2778 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2779 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2780 2781 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2782 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2783 2784 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2785 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2786 2787 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2788 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2789 2790 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2791 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2792 2793 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2794 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2795 2796 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2797 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2798 2799 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2800 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 2801 2802 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2803 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2804 2805 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2806 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2807 2808 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 2809 2810 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000066c) 2811 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000066c) 2812 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2813 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 2814 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 2815 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 2816 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 2817 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 2818 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 2819 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 2820 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2821 do {\ 2822 HWIO_INTLOCK(); \ 2823 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 2824 HWIO_INTFREE();\ 2825 } while (0) 2826 2827 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2828 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2829 2830 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 2831 2832 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000670) 2833 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000670) 2834 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2835 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 2836 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 2837 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 2838 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 2839 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 2840 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 2841 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 2842 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2843 do {\ 2844 HWIO_INTLOCK(); \ 2845 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 2846 HWIO_INTFREE();\ 2847 } while (0) 2848 2849 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2850 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2851 2852 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 2853 2854 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000680) 2855 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000680) 2856 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2857 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2858 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2859 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2860 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2861 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2862 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2863 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2864 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2865 do {\ 2866 HWIO_INTLOCK(); \ 2867 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2868 HWIO_INTFREE();\ 2869 } while (0) 2870 2871 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2872 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2873 2874 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2875 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2876 2877 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2878 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2879 2880 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 2881 2882 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000684) 2883 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000684) 2884 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2885 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2886 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2887 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2888 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2889 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2890 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2891 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2892 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2893 do {\ 2894 HWIO_INTLOCK(); \ 2895 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2896 HWIO_INTFREE();\ 2897 } while (0) 2898 2899 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2900 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2901 2902 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 2903 2904 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000688) 2905 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000688) 2906 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2907 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 2908 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 2909 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 2910 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2911 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2912 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2913 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2914 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2915 do {\ 2916 HWIO_INTLOCK(); \ 2917 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 2918 HWIO_INTFREE();\ 2919 } while (0) 2920 2921 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2922 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2923 2924 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2925 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2926 2927 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2928 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2929 2930 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 2931 2932 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000068c) 2933 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000068c) 2934 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2935 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2936 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2937 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2938 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2939 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2940 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2941 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2942 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2943 do {\ 2944 HWIO_INTLOCK(); \ 2945 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2946 HWIO_INTFREE();\ 2947 } while (0) 2948 2949 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2950 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2951 2952 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 2953 2954 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000690) 2955 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000690) 2956 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2957 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2958 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2959 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2960 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2961 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2962 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2963 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2964 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2965 do {\ 2966 HWIO_INTLOCK(); \ 2967 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2968 HWIO_INTFREE();\ 2969 } while (0) 2970 2971 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2972 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2973 2974 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 2975 2976 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000694) 2977 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000694) 2978 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2979 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2980 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2981 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2982 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2983 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2984 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2985 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2986 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2987 do {\ 2988 HWIO_INTLOCK(); \ 2989 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2990 HWIO_INTFREE();\ 2991 } while (0) 2992 2993 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2994 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2995 2996 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2997 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2998 2999 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3000 3001 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000698) 3002 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000698) 3003 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3004 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3005 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3006 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3007 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3008 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3009 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3010 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3011 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3012 do {\ 3013 HWIO_INTLOCK(); \ 3014 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3015 HWIO_INTFREE();\ 3016 } while (0) 3017 3018 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3019 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3020 3021 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3022 3023 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000069c) 3024 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000069c) 3025 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3026 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3027 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3028 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3029 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3030 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3031 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3032 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3033 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3034 do {\ 3035 HWIO_INTLOCK(); \ 3036 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3037 HWIO_INTFREE();\ 3038 } while (0) 3039 3040 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3041 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3042 3043 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3044 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3045 3046 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3047 3048 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006a0) 3049 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006a0) 3050 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3051 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3052 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3053 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3054 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3055 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3056 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3057 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3058 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3059 do {\ 3060 HWIO_INTLOCK(); \ 3061 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3062 HWIO_INTFREE();\ 3063 } while (0) 3064 3065 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3066 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3067 3068 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3069 3070 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006a4) 3071 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006a4) 3072 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3073 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3074 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3075 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3076 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3077 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3078 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3079 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3080 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3081 do {\ 3082 HWIO_INTLOCK(); \ 3083 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3084 HWIO_INTFREE();\ 3085 } while (0) 3086 3087 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3088 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3089 3090 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3091 3092 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x000006a8) 3093 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x000006a8) 3094 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3095 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3096 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3097 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3098 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3099 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3100 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3101 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3102 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3103 do {\ 3104 HWIO_INTLOCK(); \ 3105 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3106 HWIO_INTFREE();\ 3107 } while (0) 3108 3109 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3110 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3111 3112 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3113 3114 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x000006ac) 3115 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x000006ac) 3116 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3117 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3118 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3119 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3120 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3121 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3122 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3123 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3124 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3125 do {\ 3126 HWIO_INTLOCK(); \ 3127 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3128 HWIO_INTFREE();\ 3129 } while (0) 3130 3131 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3132 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3133 3134 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3135 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3136 3137 //// Register TCL_R0_TCL2TQM_RING_ID //// 3138 3139 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x000006b0) 3140 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x000006b0) 3141 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3142 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3143 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3144 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3145 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3146 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3147 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3148 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3149 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3150 do {\ 3151 HWIO_INTLOCK(); \ 3152 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3153 HWIO_INTFREE();\ 3154 } while (0) 3155 3156 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3157 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3158 3159 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3160 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3161 3162 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3163 3164 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x000006b4) 3165 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x000006b4) 3166 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3167 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3168 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3169 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3170 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3171 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3172 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3173 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3174 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3175 do {\ 3176 HWIO_INTLOCK(); \ 3177 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3178 HWIO_INTFREE();\ 3179 } while (0) 3180 3181 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3182 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3183 3184 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3185 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3186 3187 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3188 3189 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x000006b8) 3190 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x000006b8) 3191 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3192 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3193 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3194 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3195 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3196 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3197 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3198 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3199 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3200 do {\ 3201 HWIO_INTLOCK(); \ 3202 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3203 HWIO_INTFREE();\ 3204 } while (0) 3205 3206 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3207 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3208 3209 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3210 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3211 3212 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3213 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3214 3215 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3216 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3217 3218 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3219 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3220 3221 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3222 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3223 3224 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3225 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3226 3227 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3228 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3229 3230 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3231 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3232 3233 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3234 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3235 3236 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3237 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3238 3239 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3240 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3241 3242 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3243 3244 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006bc) 3245 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006bc) 3246 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3247 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3248 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3249 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3250 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3251 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3252 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3253 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3254 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3255 do {\ 3256 HWIO_INTLOCK(); \ 3257 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3258 HWIO_INTFREE();\ 3259 } while (0) 3260 3261 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3262 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3263 3264 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3265 3266 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006c0) 3267 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006c0) 3268 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3269 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3270 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3271 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3272 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3273 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3274 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3275 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3276 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3277 do {\ 3278 HWIO_INTLOCK(); \ 3279 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3280 HWIO_INTFREE();\ 3281 } while (0) 3282 3283 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3284 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3285 3286 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3287 3288 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006cc) 3289 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006cc) 3290 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3291 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3292 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3293 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3294 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3295 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3296 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3297 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3298 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3299 do {\ 3300 HWIO_INTLOCK(); \ 3301 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3302 HWIO_INTFREE();\ 3303 } while (0) 3304 3305 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3306 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3307 3308 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3309 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3310 3311 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3312 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3313 3314 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3315 3316 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006d0) 3317 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006d0) 3318 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3319 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3320 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3321 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3322 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3323 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3324 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3325 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3326 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3327 do {\ 3328 HWIO_INTLOCK(); \ 3329 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3330 HWIO_INTFREE();\ 3331 } while (0) 3332 3333 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3334 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3335 3336 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3337 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3338 3339 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3340 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3341 3342 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3343 3344 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006d4) 3345 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006d4) 3346 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3347 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3348 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3349 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3350 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3351 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3352 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3353 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3354 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3355 do {\ 3356 HWIO_INTLOCK(); \ 3357 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3358 HWIO_INTFREE();\ 3359 } while (0) 3360 3361 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3362 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3363 3364 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3365 3366 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006fc) 3367 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006fc) 3368 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3369 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3370 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3371 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3372 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3373 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3374 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3375 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3376 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3377 do {\ 3378 HWIO_INTLOCK(); \ 3379 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3380 HWIO_INTFREE();\ 3381 } while (0) 3382 3383 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3384 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3385 3386 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3387 3388 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x00000700) 3389 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x00000700) 3390 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3391 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3392 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3393 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3394 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3395 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3396 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3397 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3398 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3399 do {\ 3400 HWIO_INTLOCK(); \ 3401 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3402 HWIO_INTFREE();\ 3403 } while (0) 3404 3405 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3406 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3407 3408 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3409 3410 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x00000704) 3411 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x00000704) 3412 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3413 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3414 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3415 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3416 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3417 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3418 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3419 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3420 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3421 do {\ 3422 HWIO_INTLOCK(); \ 3423 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3424 HWIO_INTFREE();\ 3425 } while (0) 3426 3427 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3428 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3429 3430 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3431 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3432 3433 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3434 3435 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x00000708) 3436 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x00000708) 3437 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3438 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3439 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3440 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3441 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3442 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3443 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 3444 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 3445 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 3446 do {\ 3447 HWIO_INTLOCK(); \ 3448 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 3449 HWIO_INTFREE();\ 3450 } while (0) 3451 3452 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 3453 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 3454 3455 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3456 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 3457 3458 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 3459 3460 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x0000070c) 3461 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x0000070c) 3462 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 3463 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 3464 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 3465 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 3466 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 3467 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 3468 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 3469 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 3470 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 3471 do {\ 3472 HWIO_INTLOCK(); \ 3473 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 3474 HWIO_INTFREE();\ 3475 } while (0) 3476 3477 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3478 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3479 3480 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3481 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3482 3483 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 3484 3485 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x00000710) 3486 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x00000710) 3487 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 3488 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 3489 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 3490 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 3491 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 3492 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 3493 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 3494 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 3495 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 3496 do {\ 3497 HWIO_INTLOCK(); \ 3498 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 3499 HWIO_INTFREE();\ 3500 } while (0) 3501 3502 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3503 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 3504 3505 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3506 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3507 3508 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3509 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3510 3511 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3512 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3513 3514 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3515 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3516 3517 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3518 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3519 3520 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3521 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3522 3523 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3524 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3525 3526 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3527 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3528 3529 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3530 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 3531 3532 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3533 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3534 3535 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3536 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3537 3538 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 3539 3540 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000714) 3541 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000714) 3542 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3543 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 3544 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 3545 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 3546 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 3547 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 3548 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 3549 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 3550 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3551 do {\ 3552 HWIO_INTLOCK(); \ 3553 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 3554 HWIO_INTFREE();\ 3555 } while (0) 3556 3557 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3558 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3559 3560 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 3561 3562 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000718) 3563 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000718) 3564 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3565 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 3566 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 3567 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 3568 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 3569 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 3570 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 3571 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 3572 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3573 do {\ 3574 HWIO_INTLOCK(); \ 3575 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 3576 HWIO_INTFREE();\ 3577 } while (0) 3578 3579 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3580 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3581 3582 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 3583 3584 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000724) 3585 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000724) 3586 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3587 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 3588 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 3589 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 3590 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3591 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3592 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3593 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3594 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3595 do {\ 3596 HWIO_INTLOCK(); \ 3597 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3598 HWIO_INTFREE();\ 3599 } while (0) 3600 3601 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3602 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3603 3604 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3605 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3606 3607 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3608 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3609 3610 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 3611 3612 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000728) 3613 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000728) 3614 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3615 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 3616 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 3617 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 3618 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3619 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3620 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3621 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3622 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3623 do {\ 3624 HWIO_INTLOCK(); \ 3625 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3626 HWIO_INTFREE();\ 3627 } while (0) 3628 3629 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3630 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3631 3632 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3633 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3634 3635 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3636 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3637 3638 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 3639 3640 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000072c) 3641 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000072c) 3642 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3643 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3644 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3645 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 3646 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3647 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3648 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3649 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3650 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3651 do {\ 3652 HWIO_INTLOCK(); \ 3653 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3654 HWIO_INTFREE();\ 3655 } while (0) 3656 3657 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3658 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3659 3660 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 3661 3662 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000748) 3663 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000748) 3664 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3665 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 3666 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 3667 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 3668 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3669 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3670 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3671 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 3672 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3673 do {\ 3674 HWIO_INTLOCK(); \ 3675 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 3676 HWIO_INTFREE();\ 3677 } while (0) 3678 3679 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3680 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3681 3682 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 3683 3684 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000074c) 3685 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000074c) 3686 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3687 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 3688 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 3689 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 3690 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3691 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3692 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3693 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 3694 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3695 do {\ 3696 HWIO_INTLOCK(); \ 3697 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 3698 HWIO_INTFREE();\ 3699 } while (0) 3700 3701 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3702 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3703 3704 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3705 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3706 3707 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 3708 3709 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000750) 3710 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000750) 3711 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 3712 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 3713 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 3714 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 3715 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 3716 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 3717 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 3718 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 3719 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3720 do {\ 3721 HWIO_INTLOCK(); \ 3722 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 3723 HWIO_INTFREE();\ 3724 } while (0) 3725 3726 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3727 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 3728 3729 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 3730 3731 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000754) 3732 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000754) 3733 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3734 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 3735 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 3736 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 3737 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3738 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3739 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3740 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3741 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3742 do {\ 3743 HWIO_INTLOCK(); \ 3744 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3745 HWIO_INTFREE();\ 3746 } while (0) 3747 3748 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3749 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3750 3751 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 3752 3753 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x00000758) 3754 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x00000758) 3755 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 3756 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 3757 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 3758 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 3759 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 3760 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 3761 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 3762 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 3763 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 3764 do {\ 3765 HWIO_INTLOCK(); \ 3766 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 3767 HWIO_INTFREE();\ 3768 } while (0) 3769 3770 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3771 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3772 3773 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 3774 3775 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x0000075c) 3776 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x0000075c) 3777 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 3778 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 3779 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 3780 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 3781 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 3782 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 3783 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 3784 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 3785 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 3786 do {\ 3787 HWIO_INTLOCK(); \ 3788 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 3789 HWIO_INTFREE();\ 3790 } while (0) 3791 3792 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3793 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3794 3795 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3796 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3797 3798 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 3799 3800 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000760) 3801 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000760) 3802 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 3803 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 3804 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 3805 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 3806 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 3807 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 3808 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 3809 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 3810 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 3811 do {\ 3812 HWIO_INTLOCK(); \ 3813 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 3814 HWIO_INTFREE();\ 3815 } while (0) 3816 3817 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 3818 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 3819 3820 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3821 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 3822 3823 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 3824 3825 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000764) 3826 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000764) 3827 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 3828 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 3829 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 3830 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 3831 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 3832 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 3833 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 3834 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 3835 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 3836 do {\ 3837 HWIO_INTLOCK(); \ 3838 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 3839 HWIO_INTFREE();\ 3840 } while (0) 3841 3842 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3843 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3844 3845 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3846 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3847 3848 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 3849 3850 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x00000768) 3851 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x00000768) 3852 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 3853 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 3854 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 3855 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 3856 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 3857 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 3858 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 3859 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 3860 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 3861 do {\ 3862 HWIO_INTLOCK(); \ 3863 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 3864 HWIO_INTFREE();\ 3865 } while (0) 3866 3867 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3868 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 3869 3870 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3871 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3872 3873 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3874 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3875 3876 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3877 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3878 3879 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3880 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3881 3882 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3883 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3884 3885 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3886 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3887 3888 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3889 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3890 3891 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3892 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3893 3894 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3895 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 3896 3897 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3898 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3899 3900 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3901 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3902 3903 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 3904 3905 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000076c) 3906 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000076c) 3907 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3908 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 3909 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 3910 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 3911 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 3912 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 3913 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 3914 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 3915 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3916 do {\ 3917 HWIO_INTLOCK(); \ 3918 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 3919 HWIO_INTFREE();\ 3920 } while (0) 3921 3922 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3923 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3924 3925 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 3926 3927 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000770) 3928 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000770) 3929 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3930 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 3931 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 3932 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 3933 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 3934 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 3935 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 3936 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 3937 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3938 do {\ 3939 HWIO_INTLOCK(); \ 3940 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 3941 HWIO_INTFREE();\ 3942 } while (0) 3943 3944 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3945 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3946 3947 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 3948 3949 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000077c) 3950 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000077c) 3951 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3952 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 3953 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 3954 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 3955 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3956 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3957 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3958 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3959 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3960 do {\ 3961 HWIO_INTLOCK(); \ 3962 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3963 HWIO_INTFREE();\ 3964 } while (0) 3965 3966 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3967 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3968 3969 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3970 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3971 3972 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3973 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3974 3975 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 3976 3977 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000780) 3978 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000780) 3979 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3980 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 3981 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 3982 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 3983 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3984 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3985 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3986 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3987 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3988 do {\ 3989 HWIO_INTLOCK(); \ 3990 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3991 HWIO_INTFREE();\ 3992 } while (0) 3993 3994 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3995 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3996 3997 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3998 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3999 4000 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4001 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4002 4003 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4004 4005 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000784) 4006 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000784) 4007 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4008 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4009 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4010 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4011 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4012 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4013 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4014 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4015 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4016 do {\ 4017 HWIO_INTLOCK(); \ 4018 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4019 HWIO_INTFREE();\ 4020 } while (0) 4021 4022 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4023 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4024 4025 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4026 4027 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007a0) 4028 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007a0) 4029 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4030 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4031 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4032 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4033 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4034 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4035 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4036 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4037 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4038 do {\ 4039 HWIO_INTLOCK(); \ 4040 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4041 HWIO_INTFREE();\ 4042 } while (0) 4043 4044 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4045 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4046 4047 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4048 4049 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007a4) 4050 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007a4) 4051 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4052 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4053 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4054 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4055 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4056 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4057 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4058 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4059 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4060 do {\ 4061 HWIO_INTLOCK(); \ 4062 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4063 HWIO_INTFREE();\ 4064 } while (0) 4065 4066 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4067 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4068 4069 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4070 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4071 4072 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4073 4074 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x000007a8) 4075 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x000007a8) 4076 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4077 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4078 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4079 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4080 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4081 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4082 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4083 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4084 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4085 do {\ 4086 HWIO_INTLOCK(); \ 4087 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4088 HWIO_INTFREE();\ 4089 } while (0) 4090 4091 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4092 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4093 4094 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4095 4096 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007ac) 4097 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007ac) 4098 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4099 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4100 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4101 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4102 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4103 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4104 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4105 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4106 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4107 do {\ 4108 HWIO_INTLOCK(); \ 4109 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4110 HWIO_INTFREE();\ 4111 } while (0) 4112 4113 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4114 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4115 4116 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4117 4118 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x000007b0) 4119 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x000007b0) 4120 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4121 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4122 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4123 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4124 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4125 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4126 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4127 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4128 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4129 do {\ 4130 HWIO_INTLOCK(); \ 4131 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4132 HWIO_INTFREE();\ 4133 } while (0) 4134 4135 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4136 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4137 4138 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4139 4140 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x000007b4) 4141 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x000007b4) 4142 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4143 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4144 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4145 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4146 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4147 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4148 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4149 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4150 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4151 do {\ 4152 HWIO_INTLOCK(); \ 4153 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4154 HWIO_INTFREE();\ 4155 } while (0) 4156 4157 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4158 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4159 4160 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4161 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4162 4163 //// Register TCL_R0_TCL2FW_RING_ID //// 4164 4165 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x000007b8) 4166 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x000007b8) 4167 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4168 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4169 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4170 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4171 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4172 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4173 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4174 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4175 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4176 do {\ 4177 HWIO_INTLOCK(); \ 4178 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4179 HWIO_INTFREE();\ 4180 } while (0) 4181 4182 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4183 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4184 4185 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4186 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4187 4188 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4189 4190 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x000007bc) 4191 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x000007bc) 4192 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4193 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4194 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4195 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4196 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4197 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4198 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4199 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4200 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4201 do {\ 4202 HWIO_INTLOCK(); \ 4203 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4204 HWIO_INTFREE();\ 4205 } while (0) 4206 4207 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4208 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4209 4210 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4211 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4212 4213 //// Register TCL_R0_TCL2FW_RING_MISC //// 4214 4215 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x000007c0) 4216 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x000007c0) 4217 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4218 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4219 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4220 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4221 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4222 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4223 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4224 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4225 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4226 do {\ 4227 HWIO_INTLOCK(); \ 4228 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4229 HWIO_INTFREE();\ 4230 } while (0) 4231 4232 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4233 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4234 4235 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4236 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4237 4238 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4239 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4240 4241 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4242 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4243 4244 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4245 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4246 4247 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4248 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4249 4250 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4251 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4252 4253 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4254 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4255 4256 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4257 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4258 4259 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4260 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4261 4262 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4263 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4264 4265 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4266 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4267 4268 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4269 4270 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007c4) 4271 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007c4) 4272 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4273 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4274 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4275 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4276 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4277 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4278 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4279 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4280 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4281 do {\ 4282 HWIO_INTLOCK(); \ 4283 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4284 HWIO_INTFREE();\ 4285 } while (0) 4286 4287 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4288 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4289 4290 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4291 4292 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007c8) 4293 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007c8) 4294 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4295 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4296 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4297 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4298 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4299 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4300 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4301 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4302 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4303 do {\ 4304 HWIO_INTLOCK(); \ 4305 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4306 HWIO_INTFREE();\ 4307 } while (0) 4308 4309 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4310 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4311 4312 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4313 4314 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007d4) 4315 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007d4) 4316 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4317 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4318 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4319 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4320 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4321 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4322 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4323 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4324 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4325 do {\ 4326 HWIO_INTLOCK(); \ 4327 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4328 HWIO_INTFREE();\ 4329 } while (0) 4330 4331 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4332 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4333 4334 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4335 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4336 4337 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4338 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4339 4340 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4341 4342 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007d8) 4343 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007d8) 4344 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4345 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4346 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4347 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4348 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4349 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4350 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4351 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4352 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4353 do {\ 4354 HWIO_INTLOCK(); \ 4355 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4356 HWIO_INTFREE();\ 4357 } while (0) 4358 4359 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4360 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4361 4362 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4363 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4364 4365 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4366 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4367 4368 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4369 4370 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007dc) 4371 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007dc) 4372 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4373 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4374 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4375 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4376 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4377 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4378 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4379 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4380 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4381 do {\ 4382 HWIO_INTLOCK(); \ 4383 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4384 HWIO_INTFREE();\ 4385 } while (0) 4386 4387 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4388 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4389 4390 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4391 4392 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000804) 4393 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000804) 4394 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4395 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4396 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4397 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4398 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4399 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4400 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4401 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4402 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4403 do {\ 4404 HWIO_INTLOCK(); \ 4405 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4406 HWIO_INTFREE();\ 4407 } while (0) 4408 4409 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4410 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4411 4412 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4413 4414 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000808) 4415 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000808) 4416 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4417 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4418 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4419 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4420 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4421 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4422 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4423 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4424 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4425 do {\ 4426 HWIO_INTLOCK(); \ 4427 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4428 HWIO_INTFREE();\ 4429 } while (0) 4430 4431 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4432 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4433 4434 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4435 4436 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x0000080c) 4437 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x0000080c) 4438 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4439 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4440 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4441 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4442 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4443 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4444 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4445 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4446 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4447 do {\ 4448 HWIO_INTLOCK(); \ 4449 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4450 HWIO_INTFREE();\ 4451 } while (0) 4452 4453 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4454 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4455 4456 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4457 4458 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x00000810) 4459 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x00000810) 4460 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4461 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4462 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4463 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4464 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4465 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4466 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4467 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4468 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4469 do {\ 4470 HWIO_INTLOCK(); \ 4471 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4472 HWIO_INTFREE();\ 4473 } while (0) 4474 4475 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4476 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4477 4478 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4479 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4480 4481 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4482 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4483 4484 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4485 4486 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000814) 4487 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000814) 4488 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4489 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4490 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4491 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4492 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4493 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4494 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4495 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4496 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4497 do {\ 4498 HWIO_INTLOCK(); \ 4499 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 4500 HWIO_INTFREE();\ 4501 } while (0) 4502 4503 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 4504 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 4505 4506 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 4507 4508 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000818) 4509 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000818) 4510 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 4511 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 4512 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 4513 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 4514 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 4515 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 4516 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 4517 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 4518 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 4519 do {\ 4520 HWIO_INTLOCK(); \ 4521 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 4522 HWIO_INTFREE();\ 4523 } while (0) 4524 4525 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 4526 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 4527 4528 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 4529 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 4530 4531 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 4532 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 4533 4534 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 4535 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 4536 4537 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 4538 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 4539 4540 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 4541 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 4542 4543 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 4544 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 4545 4546 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 4547 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 4548 4549 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 4550 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 4551 4552 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 4553 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 4554 4555 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 4556 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 4557 4558 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 4559 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 4560 4561 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 4562 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 4563 4564 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 4565 4566 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x0000081c) 4567 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x0000081c) 4568 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 4569 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 4570 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 4571 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 4572 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 4573 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 4574 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 4575 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 4576 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 4577 do {\ 4578 HWIO_INTLOCK(); \ 4579 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 4580 HWIO_INTFREE();\ 4581 } while (0) 4582 4583 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 4584 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 4585 4586 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 4587 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 4588 4589 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 4590 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 4591 4592 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 4593 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 4594 4595 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 4596 4597 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x00000820) 4598 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x00000820) 4599 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 4600 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 4601 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 4602 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 4603 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 4604 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 4605 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 4606 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 4607 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 4608 do {\ 4609 HWIO_INTLOCK(); \ 4610 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 4611 HWIO_INTFREE();\ 4612 } while (0) 4613 4614 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 4615 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 4616 4617 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 4618 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 4619 4620 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 4621 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 4622 4623 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 4624 4625 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000824) 4626 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000824) 4627 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 4628 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 4629 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 4630 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 4631 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 4632 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 4633 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 4634 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 4635 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 4636 do {\ 4637 HWIO_INTLOCK(); \ 4638 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 4639 HWIO_INTFREE();\ 4640 } while (0) 4641 4642 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 4643 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 4644 4645 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4646 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 4647 4648 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 4649 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 4650 4651 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 4652 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 4653 4654 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 4655 4656 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000828) 4657 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000828) 4658 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 4659 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 4660 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 4661 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 4662 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 4663 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 4664 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 4665 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 4666 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 4667 do {\ 4668 HWIO_INTLOCK(); \ 4669 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 4670 HWIO_INTFREE();\ 4671 } while (0) 4672 4673 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 4674 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 4675 4676 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4677 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 4678 4679 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 4680 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 4681 4682 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 4683 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 4684 4685 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 4686 4687 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x0000082c) 4688 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x0000082c) 4689 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 4690 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 4691 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 4692 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 4693 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 4694 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 4695 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 4696 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 4697 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 4698 do {\ 4699 HWIO_INTLOCK(); \ 4700 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 4701 HWIO_INTFREE();\ 4702 } while (0) 4703 4704 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 4705 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 4706 4707 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 4708 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 4709 4710 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 4711 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 4712 4713 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 4714 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 4715 4716 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 4717 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 4718 4719 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 4720 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 4721 4722 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 4723 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 4724 4725 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 4726 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 4727 4728 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 4729 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 4730 4731 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 4732 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 4733 4734 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 4735 4736 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000830) 4737 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000830) 4738 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 4739 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 4740 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 4741 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 4742 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 4743 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 4744 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 4745 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 4746 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 4747 do {\ 4748 HWIO_INTLOCK(); \ 4749 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 4750 HWIO_INTFREE();\ 4751 } while (0) 4752 4753 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 4754 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 4755 4756 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 4757 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 4758 4759 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 4760 4761 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000834) 4762 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000834) 4763 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 4764 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 4765 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 4766 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 4767 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 4768 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 4769 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 4770 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 4771 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 4772 do {\ 4773 HWIO_INTLOCK(); \ 4774 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 4775 HWIO_INTFREE();\ 4776 } while (0) 4777 4778 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 4779 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 4780 4781 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 4782 4783 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000838) 4784 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000838) 4785 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 4786 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 4787 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 4788 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 4789 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 4790 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 4791 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 4792 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 4793 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 4794 do {\ 4795 HWIO_INTLOCK(); \ 4796 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 4797 HWIO_INTFREE();\ 4798 } while (0) 4799 4800 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 4801 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 4802 4803 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 4804 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 4805 4806 //// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// 4807 4808 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x0000083c) 4809 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x0000083c) 4810 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 4811 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 4812 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 4813 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 4814 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 4815 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 4816 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 4817 out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 4818 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 4819 do {\ 4820 HWIO_INTLOCK(); \ 4821 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 4822 HWIO_INTFREE();\ 4823 } while (0) 4824 4825 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 4826 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 4827 4828 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 4829 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 4830 4831 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 4832 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 4833 4834 //// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// 4835 4836 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x00000840) 4837 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x00000840) 4838 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 4839 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 4840 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 4841 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 4842 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 4843 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 4844 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 4845 out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 4846 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 4847 do {\ 4848 HWIO_INTLOCK(); \ 4849 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 4850 HWIO_INTFREE();\ 4851 } while (0) 4852 4853 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 4854 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 4855 4856 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 4857 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 4858 4859 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 4860 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 4861 4862 //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 4863 4864 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000844) 4865 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000844) 4866 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 4867 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 4868 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 4869 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 4870 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 4871 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 4872 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 4873 out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 4874 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 4875 do {\ 4876 HWIO_INTLOCK(); \ 4877 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 4878 HWIO_INTFREE();\ 4879 } while (0) 4880 4881 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 4882 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 4883 4884 //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 4885 4886 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000848) 4887 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000848) 4888 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 4889 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 4890 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 4891 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 4892 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 4893 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 4894 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 4895 out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 4896 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 4897 do {\ 4898 HWIO_INTLOCK(); \ 4899 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 4900 HWIO_INTFREE();\ 4901 } while (0) 4902 4903 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 4904 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 4905 4906 //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 4907 4908 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x0000084c) 4909 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x0000084c) 4910 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 4911 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 4912 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 4913 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 4914 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 4915 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 4916 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 4917 out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 4918 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 4919 do {\ 4920 HWIO_INTLOCK(); \ 4921 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 4922 HWIO_INTFREE();\ 4923 } while (0) 4924 4925 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 4926 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 4927 4928 //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 4929 4930 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000850) 4931 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000850) 4932 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 4933 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 4934 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 4935 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 4936 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 4937 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 4938 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 4939 out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 4940 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 4941 do {\ 4942 HWIO_INTLOCK(); \ 4943 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 4944 HWIO_INTFREE();\ 4945 } while (0) 4946 4947 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 4948 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 4949 4950 //// Register TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 4951 4952 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x00000854) 4953 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x00000854) 4954 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 4955 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 4956 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 4957 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 4958 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 4959 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 4960 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 4961 out_dword( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 4962 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 4963 do {\ 4964 HWIO_INTLOCK(); \ 4965 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 4966 HWIO_INTFREE();\ 4967 } while (0) 4968 4969 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 4970 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 4971 4972 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 4973 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 4974 4975 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 4976 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 4977 4978 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 4979 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 4980 4981 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 4982 4983 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000858) 4984 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000858) 4985 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 4986 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 4987 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 4988 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 4989 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 4990 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 4991 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 4992 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 4993 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 4994 do {\ 4995 HWIO_INTLOCK(); \ 4996 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 4997 HWIO_INTFREE();\ 4998 } while (0) 4999 5000 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5001 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5002 5003 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 5004 5005 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x0000085c) 5006 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x0000085c) 5007 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5008 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 5009 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 5010 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 5011 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5012 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5013 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5014 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5015 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5016 do {\ 5017 HWIO_INTLOCK(); \ 5018 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 5019 HWIO_INTFREE();\ 5020 } while (0) 5021 5022 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5023 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5024 5025 //// Register TCL_R0_ASE_GST_SIZE //// 5026 5027 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000860) 5028 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000860) 5029 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 5030 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 5031 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 5032 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 5033 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 5034 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 5035 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 5036 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 5037 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 5038 do {\ 5039 HWIO_INTLOCK(); \ 5040 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5041 HWIO_INTFREE();\ 5042 } while (0) 5043 5044 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5045 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5046 5047 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5048 5049 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000864) 5050 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000864) 5051 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff 5052 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5053 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5054 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5055 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5056 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5057 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5058 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5059 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5060 do {\ 5061 HWIO_INTLOCK(); \ 5062 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5063 HWIO_INTFREE();\ 5064 } while (0) 5065 5066 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5067 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5068 5069 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x00002000 5070 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 0xd 5071 5072 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x00001000 5073 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 0xc 5074 5075 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x00000800 5076 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 0xb 5077 5078 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5079 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5080 5081 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5082 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5083 5084 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5085 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5086 5087 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5088 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5089 5090 //// Register TCL_R0_ASE_WATCHDOG //// 5091 5092 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000868) 5093 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000868) 5094 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5095 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5096 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5097 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5098 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5099 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5100 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5101 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5102 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5103 do {\ 5104 HWIO_INTLOCK(); \ 5105 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5106 HWIO_INTFREE();\ 5107 } while (0) 5108 5109 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5110 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5111 5112 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5113 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5114 5115 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5116 5117 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x0000086c) 5118 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x0000086c) 5119 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5120 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5121 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5122 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5123 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5124 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5125 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5126 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5127 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5128 do {\ 5129 HWIO_INTLOCK(); \ 5130 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5131 HWIO_INTFREE();\ 5132 } while (0) 5133 5134 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5135 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5136 5137 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5138 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5139 5140 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5141 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5142 5143 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000400 5144 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0xa 5145 5146 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000200 5147 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x9 5148 5149 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000100 5150 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x8 5151 5152 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5153 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5154 5155 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5156 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5157 5158 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5159 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5160 5161 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5162 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5163 5164 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5165 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5166 5167 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5168 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5169 5170 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5171 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5172 5173 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5174 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5175 5176 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5177 5178 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000870) 5179 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000870) 5180 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5181 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5182 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5183 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5184 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5185 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5186 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5187 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5188 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5189 do {\ 5190 HWIO_INTLOCK(); \ 5191 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5192 HWIO_INTFREE();\ 5193 } while (0) 5194 5195 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5196 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5197 5198 //// Register TCL_R1_SM_STATES_IX_0 //// 5199 5200 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) 5201 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) 5202 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5203 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5204 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5205 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5206 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5207 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5208 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5209 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5210 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5211 do {\ 5212 HWIO_INTLOCK(); \ 5213 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5214 HWIO_INTFREE();\ 5215 } while (0) 5216 5217 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5218 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5219 5220 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5221 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5222 5223 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5224 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5225 5226 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5227 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5228 5229 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x00007000 5230 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 0xc 5231 5232 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5233 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5234 5235 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5236 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5237 5238 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5239 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5240 5241 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5242 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5243 5244 //// Register TCL_R1_SM_STATES_IX_1 //// 5245 5246 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) 5247 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) 5248 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff 5249 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5250 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5251 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5252 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5253 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5254 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5255 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5256 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5257 do {\ 5258 HWIO_INTLOCK(); \ 5259 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5260 HWIO_INTFREE();\ 5261 } while (0) 5262 5263 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 5264 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf 5265 5266 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5267 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5268 5269 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5270 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5271 5272 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5273 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5274 5275 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5276 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5277 5278 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5279 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5280 5281 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5282 5283 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) 5284 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) 5285 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff 5286 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5287 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5288 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5289 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5290 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5291 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5292 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5293 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5294 do {\ 5295 HWIO_INTLOCK(); \ 5296 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5297 HWIO_INTFREE();\ 5298 } while (0) 5299 5300 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000 5301 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d 5302 5303 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5304 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5305 5306 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5307 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5308 5309 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5310 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5311 5312 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5313 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5314 5315 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5316 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5317 5318 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5319 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5320 5321 //// Register TCL_R1_TESTBUS_LOW //// 5322 5323 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) 5324 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) 5325 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5326 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5327 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5328 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5329 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5330 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5331 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5332 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5333 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5334 do {\ 5335 HWIO_INTLOCK(); \ 5336 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5337 HWIO_INTFREE();\ 5338 } while (0) 5339 5340 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5341 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5342 5343 //// Register TCL_R1_TESTBUS_HIGH //// 5344 5345 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) 5346 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) 5347 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5348 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5349 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5350 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5351 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5352 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5353 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5354 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5355 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5356 do {\ 5357 HWIO_INTLOCK(); \ 5358 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5359 HWIO_INTFREE();\ 5360 } while (0) 5361 5362 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5363 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5364 5365 //// Register TCL_R1_EVENTMASK_IX_0 //// 5366 5367 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) 5368 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) 5369 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5370 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5371 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5372 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5373 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5374 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5375 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5376 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5377 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5378 do {\ 5379 HWIO_INTLOCK(); \ 5380 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5381 HWIO_INTFREE();\ 5382 } while (0) 5383 5384 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5385 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5386 5387 //// Register TCL_R1_EVENTMASK_IX_1 //// 5388 5389 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) 5390 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) 5391 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5392 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5393 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5394 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5395 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5396 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5397 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5398 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5399 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5400 do {\ 5401 HWIO_INTLOCK(); \ 5402 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5403 HWIO_INTFREE();\ 5404 } while (0) 5405 5406 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5407 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5408 5409 //// Register TCL_R1_EVENTMASK_IX_2 //// 5410 5411 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) 5412 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) 5413 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5414 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5415 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5416 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5417 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5418 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5419 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5420 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5421 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5422 do {\ 5423 HWIO_INTLOCK(); \ 5424 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5425 HWIO_INTFREE();\ 5426 } while (0) 5427 5428 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5429 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5430 5431 //// Register TCL_R1_EVENTMASK_IX_3 //// 5432 5433 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) 5434 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) 5435 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5436 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5437 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5438 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5439 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5440 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5441 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5442 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5443 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5444 do {\ 5445 HWIO_INTLOCK(); \ 5446 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5447 HWIO_INTFREE();\ 5448 } while (0) 5449 5450 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5451 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5452 5453 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5454 5455 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) 5456 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) 5457 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5458 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5459 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5460 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5461 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5462 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5463 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5464 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5465 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5466 do {\ 5467 HWIO_INTLOCK(); \ 5468 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5469 HWIO_INTFREE();\ 5470 } while (0) 5471 5472 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5473 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5474 5475 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5476 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5477 5478 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5479 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5480 5481 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5482 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5483 5484 //// Register TCL_R1_END_OF_TEST_CHECK //// 5485 5486 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) 5487 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) 5488 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5489 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5490 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5491 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5492 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5493 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5494 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5495 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5496 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5497 do {\ 5498 HWIO_INTLOCK(); \ 5499 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5500 HWIO_INTFREE();\ 5501 } while (0) 5502 5503 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5504 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5505 5506 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5507 5508 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 5509 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 5510 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5511 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5512 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5513 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5514 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5515 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5516 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5517 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5518 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5519 do {\ 5520 HWIO_INTLOCK(); \ 5521 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5522 HWIO_INTFREE();\ 5523 } while (0) 5524 5525 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5526 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5527 5528 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5529 5530 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) 5531 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) 5532 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5533 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5534 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5535 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5536 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5537 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5538 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5539 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5540 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5541 do {\ 5542 HWIO_INTLOCK(); \ 5543 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5544 HWIO_INTFREE();\ 5545 } while (0) 5546 5547 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5548 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5549 5550 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5551 5552 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) 5553 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) 5554 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5555 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5556 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5557 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5558 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5559 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5560 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5561 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5562 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5563 do {\ 5564 HWIO_INTLOCK(); \ 5565 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5566 HWIO_INTFREE();\ 5567 } while (0) 5568 5569 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5570 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5571 5572 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 5573 5574 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) 5575 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) 5576 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5577 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5578 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5579 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 5580 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 5581 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 5582 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 5583 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 5584 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 5585 do {\ 5586 HWIO_INTLOCK(); \ 5587 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 5588 HWIO_INTFREE();\ 5589 } while (0) 5590 5591 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 5592 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 5593 5594 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 5595 5596 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) 5597 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) 5598 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 5599 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 5600 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 5601 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 5602 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 5603 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 5604 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 5605 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 5606 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 5607 do {\ 5608 HWIO_INTLOCK(); \ 5609 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 5610 HWIO_INTFREE();\ 5611 } while (0) 5612 5613 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 5614 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 5615 5616 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 5617 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 5618 5619 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 5620 5621 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) 5622 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) 5623 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 5624 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 5625 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 5626 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 5627 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 5628 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 5629 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 5630 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 5631 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 5632 do {\ 5633 HWIO_INTLOCK(); \ 5634 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 5635 HWIO_INTFREE();\ 5636 } while (0) 5637 5638 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 5639 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 5640 5641 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 5642 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 5643 5644 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 5645 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 5646 5647 //// Register TCL_R1_ASE_SM_STATES //// 5648 5649 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) 5650 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) 5651 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff 5652 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 5653 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 5654 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 5655 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 5656 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 5657 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 5658 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 5659 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 5660 do {\ 5661 HWIO_INTLOCK(); \ 5662 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 5663 HWIO_INTFREE();\ 5664 } while (0) 5665 5666 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 5667 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 5668 5669 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 5670 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 5671 5672 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 5673 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 5674 5675 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 5676 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 5677 5678 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 5679 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 5680 5681 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 5682 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 5683 5684 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 5685 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 5686 5687 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 5688 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 5689 5690 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 5691 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 5692 5693 //// Register TCL_R1_ASE_CACHE_DEBUG //// 5694 5695 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) 5696 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) 5697 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 5698 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 5699 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 5700 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 5701 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 5702 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 5703 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 5704 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 5705 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 5706 do {\ 5707 HWIO_INTLOCK(); \ 5708 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 5709 HWIO_INTFREE();\ 5710 } while (0) 5711 5712 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 5713 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 5714 5715 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 5716 5717 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) 5718 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) 5719 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 5720 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 5721 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 5722 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 5723 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 5724 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 5725 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 5726 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 5727 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 5728 do {\ 5729 HWIO_INTLOCK(); \ 5730 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 5731 HWIO_INTFREE();\ 5732 } while (0) 5733 5734 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 5735 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 5736 5737 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 5738 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 5739 5740 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 5741 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 5742 5743 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 5744 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 5745 5746 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 5747 5748 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) 5749 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) 5750 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 5751 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 5752 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 5753 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 5754 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 5755 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 5756 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 5757 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 5758 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 5759 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 5760 do {\ 5761 HWIO_INTLOCK(); \ 5762 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 5763 HWIO_INTFREE();\ 5764 } while (0) 5765 5766 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 5767 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 5768 5769 //// Register TCL_R2_SW2TCL1_RING_HP //// 5770 5771 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 5772 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 5773 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff 5774 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 5775 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 5776 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 5777 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 5778 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 5779 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 5780 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 5781 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 5782 do {\ 5783 HWIO_INTLOCK(); \ 5784 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 5785 HWIO_INTFREE();\ 5786 } while (0) 5787 5788 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff 5789 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 5790 5791 //// Register TCL_R2_SW2TCL1_RING_TP //// 5792 5793 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 5794 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 5795 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff 5796 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 5797 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 5798 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 5799 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 5800 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 5801 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 5802 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 5803 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 5804 do {\ 5805 HWIO_INTLOCK(); \ 5806 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 5807 HWIO_INTFREE();\ 5808 } while (0) 5809 5810 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff 5811 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 5812 5813 //// Register TCL_R2_SW2TCL2_RING_HP //// 5814 5815 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 5816 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 5817 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff 5818 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 5819 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 5820 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 5821 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 5822 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 5823 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 5824 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 5825 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 5826 do {\ 5827 HWIO_INTLOCK(); \ 5828 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 5829 HWIO_INTFREE();\ 5830 } while (0) 5831 5832 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff 5833 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 5834 5835 //// Register TCL_R2_SW2TCL2_RING_TP //// 5836 5837 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 5838 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 5839 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff 5840 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 5841 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 5842 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 5843 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 5844 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 5845 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 5846 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 5847 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 5848 do {\ 5849 HWIO_INTLOCK(); \ 5850 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 5851 HWIO_INTFREE();\ 5852 } while (0) 5853 5854 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff 5855 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 5856 5857 //// Register TCL_R2_SW2TCL3_RING_HP //// 5858 5859 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 5860 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 5861 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff 5862 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 5863 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 5864 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 5865 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 5866 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 5867 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 5868 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 5869 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 5870 do {\ 5871 HWIO_INTLOCK(); \ 5872 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 5873 HWIO_INTFREE();\ 5874 } while (0) 5875 5876 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff 5877 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 5878 5879 //// Register TCL_R2_SW2TCL3_RING_TP //// 5880 5881 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 5882 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 5883 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff 5884 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 5885 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 5886 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 5887 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 5888 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 5889 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 5890 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 5891 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 5892 do {\ 5893 HWIO_INTLOCK(); \ 5894 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 5895 HWIO_INTFREE();\ 5896 } while (0) 5897 5898 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff 5899 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 5900 5901 //// Register TCL_R2_SW2TCL_CREDIT_RING_HP //// 5902 5903 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) (x+0x00002018) 5904 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) (x+0x00002018) 5905 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0x000fffff 5906 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_SHFT 0 5907 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ 5908 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK) 5909 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, mask) \ 5910 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask) 5911 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, val) \ 5912 out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), val) 5913 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x, mask, val) \ 5914 do {\ 5915 HWIO_INTLOCK(); \ 5916 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)); \ 5917 HWIO_INTFREE();\ 5918 } while (0) 5919 5920 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0x000fffff 5921 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0x0 5922 5923 //// Register TCL_R2_SW2TCL_CREDIT_RING_TP //// 5924 5925 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) (x+0x0000201c) 5926 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) (x+0x0000201c) 5927 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0x000fffff 5928 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_SHFT 0 5929 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ 5930 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK) 5931 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, mask) \ 5932 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask) 5933 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, val) \ 5934 out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), val) 5935 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x, mask, val) \ 5936 do {\ 5937 HWIO_INTLOCK(); \ 5938 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)); \ 5939 HWIO_INTFREE();\ 5940 } while (0) 5941 5942 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0x000fffff 5943 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0x0 5944 5945 //// Register TCL_R2_FW2TCL1_RING_HP //// 5946 5947 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 5948 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 5949 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 5950 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 5951 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 5952 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 5953 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 5954 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 5955 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 5956 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 5957 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 5958 do {\ 5959 HWIO_INTLOCK(); \ 5960 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 5961 HWIO_INTFREE();\ 5962 } while (0) 5963 5964 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 5965 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 5966 5967 //// Register TCL_R2_FW2TCL1_RING_TP //// 5968 5969 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 5970 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 5971 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 5972 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 5973 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 5974 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 5975 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 5976 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 5977 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 5978 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 5979 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 5980 do {\ 5981 HWIO_INTLOCK(); \ 5982 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 5983 HWIO_INTFREE();\ 5984 } while (0) 5985 5986 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 5987 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 5988 5989 //// Register TCL_R2_TCL2TQM_RING_HP //// 5990 5991 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 5992 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 5993 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 5994 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 5995 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 5996 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 5997 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 5998 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 5999 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6000 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6001 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6002 do {\ 6003 HWIO_INTLOCK(); \ 6004 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6005 HWIO_INTFREE();\ 6006 } while (0) 6007 6008 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6009 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6010 6011 //// Register TCL_R2_TCL2TQM_RING_TP //// 6012 6013 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6014 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6015 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6016 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6017 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6018 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6019 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6020 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6021 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6022 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6023 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6024 do {\ 6025 HWIO_INTLOCK(); \ 6026 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 6027 HWIO_INTFREE();\ 6028 } while (0) 6029 6030 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6031 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 6032 6033 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 6034 6035 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 6036 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 6037 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 6038 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 6039 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 6040 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 6041 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 6042 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 6043 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 6044 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 6045 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 6046 do {\ 6047 HWIO_INTLOCK(); \ 6048 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 6049 HWIO_INTFREE();\ 6050 } while (0) 6051 6052 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6053 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 6054 6055 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 6056 6057 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 6058 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 6059 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 6060 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 6061 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 6062 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 6063 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 6064 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 6065 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 6066 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 6067 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 6068 do {\ 6069 HWIO_INTLOCK(); \ 6070 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 6071 HWIO_INTFREE();\ 6072 } while (0) 6073 6074 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6075 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 6076 6077 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 6078 6079 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 6080 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 6081 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 6082 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6083 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6084 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6085 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6086 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6087 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6088 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6089 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6090 do {\ 6091 HWIO_INTLOCK(); \ 6092 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6093 HWIO_INTFREE();\ 6094 } while (0) 6095 6096 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6097 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6098 6099 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6100 6101 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6102 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6103 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6104 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6105 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6106 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6107 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6108 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6109 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6110 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6111 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6112 do {\ 6113 HWIO_INTLOCK(); \ 6114 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6115 HWIO_INTFREE();\ 6116 } while (0) 6117 6118 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6119 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6120 6121 //// Register TCL_R2_TCL2FW_RING_HP //// 6122 6123 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6124 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6125 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6126 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6127 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6128 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6129 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6130 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6131 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6132 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6133 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6134 do {\ 6135 HWIO_INTLOCK(); \ 6136 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6137 HWIO_INTFREE();\ 6138 } while (0) 6139 6140 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6141 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6142 6143 //// Register TCL_R2_TCL2FW_RING_TP //// 6144 6145 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6146 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6147 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6148 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6149 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6150 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6151 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6152 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6153 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6154 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6155 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6156 do {\ 6157 HWIO_INTLOCK(); \ 6158 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6159 HWIO_INTFREE();\ 6160 } while (0) 6161 6162 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6163 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6164 6165 6166 #endif 6167 6168