1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __MSMHWIOBASE_H__ 18 #define __MSMHWIOBASE_H__ 19 /* 20 =========================================================================== 21 */ 22 /** 23 @file msmhwiobase.h 24 @brief Auto-generated HWIO base include file. 25 */ 26 /* 27 =========================================================================== 28 */ 29 30 /*---------------------------------------------------------------------------- 31 * BASE: WCSS_WCSS 32 *--------------------------------------------------------------------------*/ 33 34 #define WCSS_WCSS_BASE 0x00000000 35 #define WCSS_WCSS_BASE_SIZE 0x01000000 36 #define WCSS_WCSS_BASE_PHYS 0x00000000 37 38 /*---------------------------------------------------------------------------- 39 * BASE: BOOT_ROM_SIZE 40 *--------------------------------------------------------------------------*/ 41 42 #define BOOT_ROM_SIZE_BASE 0x00100000 43 #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 44 #define BOOT_ROM_SIZE_BASE_PHYS 0x00100000 45 46 /*---------------------------------------------------------------------------- 47 * BASE: QDSS_STM_SIZE 48 *--------------------------------------------------------------------------*/ 49 50 #define QDSS_STM_SIZE_BASE 0x00100000 51 #define QDSS_STM_SIZE_BASE_SIZE 0x100000000 52 #define QDSS_STM_SIZE_BASE_PHYS 0x00100000 53 54 /*---------------------------------------------------------------------------- 55 * BASE: SYSTEM_IRAM_SIZE 56 *--------------------------------------------------------------------------*/ 57 58 #define SYSTEM_IRAM_SIZE_BASE 0x00400000 59 #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 60 #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 61 62 /*---------------------------------------------------------------------------- 63 * BASE: BOOT_ROM_START_ADDRESS 64 *--------------------------------------------------------------------------*/ 65 66 #define BOOT_ROM_START_ADDRESS_BASE 0x00800000 67 #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 68 #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x00800000 69 70 /*---------------------------------------------------------------------------- 71 * BASE: BOOT_ROM_END_ADDRESS 72 *--------------------------------------------------------------------------*/ 73 74 #define BOOT_ROM_END_ADDRESS_BASE 0x008fffff 75 #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 76 #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x008fffff 77 78 /*---------------------------------------------------------------------------- 79 * BASE: QDSS_STM 80 *--------------------------------------------------------------------------*/ 81 82 #define QDSS_STM_BASE 0x00900000 83 #define QDSS_STM_BASE_SIZE 0x100000000 84 #define QDSS_STM_BASE_PHYS 0x00900000 85 86 /*---------------------------------------------------------------------------- 87 * BASE: QDSS_STM_END 88 *--------------------------------------------------------------------------*/ 89 90 #define QDSS_STM_END_BASE 0x009fffff 91 #define QDSS_STM_END_BASE_SIZE 0x100000000 92 #define QDSS_STM_END_BASE_PHYS 0x009fffff 93 94 /*---------------------------------------------------------------------------- 95 * BASE: SYSTEM_IRAM_START_ADDRESS 96 *--------------------------------------------------------------------------*/ 97 98 #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 99 #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 100 #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 101 102 /*---------------------------------------------------------------------------- 103 * BASE: SYSTEM_IRAM_END_ADDRESS 104 *--------------------------------------------------------------------------*/ 105 106 #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff 107 #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 108 #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff 109 110 /*---------------------------------------------------------------------------- 111 * BASE: TLMM 112 *--------------------------------------------------------------------------*/ 113 114 #define TLMM_BASE 0x01800000 115 #define TLMM_BASE_SIZE 0x00300000 116 #define TLMM_BASE_PHYS 0x01800000 117 118 /*---------------------------------------------------------------------------- 119 * BASE: CORE_TOP_CSR 120 *--------------------------------------------------------------------------*/ 121 122 #define CORE_TOP_CSR_BASE 0x01b00000 123 #define CORE_TOP_CSR_BASE_SIZE 0x00040000 124 #define CORE_TOP_CSR_BASE_PHYS 0x01b00000 125 126 /*---------------------------------------------------------------------------- 127 * BASE: BLSP1_BLSP 128 *--------------------------------------------------------------------------*/ 129 130 #define BLSP1_BLSP_BASE 0x01b40000 131 #define BLSP1_BLSP_BASE_SIZE 0x00040000 132 #define BLSP1_BLSP_BASE_PHYS 0x01b40000 133 134 /*---------------------------------------------------------------------------- 135 * BASE: MEMSS_CSR 136 *--------------------------------------------------------------------------*/ 137 138 #define MEMSS_CSR_BASE 0x01bc0000 139 #define MEMSS_CSR_BASE_SIZE 0x0000001c 140 #define MEMSS_CSR_BASE_PHYS 0x01bc0000 141 142 /*---------------------------------------------------------------------------- 143 * BASE: TSENS_SROT 144 *--------------------------------------------------------------------------*/ 145 146 #define TSENS_SROT_BASE 0x01bf0000 147 #define TSENS_SROT_BASE_SIZE 0x00001000 148 #define TSENS_SROT_BASE_PHYS 0x01bf0000 149 150 /*---------------------------------------------------------------------------- 151 * BASE: TSENS_TM 152 *--------------------------------------------------------------------------*/ 153 154 #define TSENS_TM_BASE 0x01bf1000 155 #define TSENS_TM_BASE_SIZE 0x00001000 156 #define TSENS_TM_BASE_PHYS 0x01bf1000 157 158 /*---------------------------------------------------------------------------- 159 * BASE: QDSS_APB_DEC_QDSS_APB 160 *--------------------------------------------------------------------------*/ 161 162 #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 163 #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 164 #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 165 166 /*---------------------------------------------------------------------------- 167 * BASE: QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG 168 *--------------------------------------------------------------------------*/ 169 170 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01c80000 171 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00080000 172 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01c80000 173 174 /*---------------------------------------------------------------------------- 175 * BASE: QDSS_WRAPPER_TOP 176 *--------------------------------------------------------------------------*/ 177 178 #define QDSS_WRAPPER_TOP_BASE 0x01d00000 179 #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd 180 #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01d00000 181 182 /*---------------------------------------------------------------------------- 183 * BASE: PCIE_PCIE_TOP_WRAPPER 184 *--------------------------------------------------------------------------*/ 185 186 #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 187 #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 188 #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 189 190 /*---------------------------------------------------------------------------- 191 * BASE: SECURITY_CONTROL_WLAN 192 *--------------------------------------------------------------------------*/ 193 194 #define SECURITY_CONTROL_WLAN_BASE 0x01e20000 195 #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 196 #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 197 198 /*---------------------------------------------------------------------------- 199 * BASE: CPR_CX_CPR3 200 *--------------------------------------------------------------------------*/ 201 202 #define CPR_CX_CPR3_BASE 0x01e30000 203 #define CPR_CX_CPR3_BASE_SIZE 0x00004000 204 #define CPR_CX_CPR3_BASE_PHYS 0x01e30000 205 206 /*---------------------------------------------------------------------------- 207 * BASE: CPR_MX_CPR3 208 *--------------------------------------------------------------------------*/ 209 210 #define CPR_MX_CPR3_BASE 0x01e34000 211 #define CPR_MX_CPR3_BASE_SIZE 0x00004000 212 #define CPR_MX_CPR3_BASE_PHYS 0x01e34000 213 214 /*---------------------------------------------------------------------------- 215 * BASE: GCC_GCC 216 *--------------------------------------------------------------------------*/ 217 218 #define GCC_GCC_BASE 0x01e40000 219 #define GCC_GCC_BASE_SIZE 0x00001000 220 #define GCC_GCC_BASE_PHYS 0x01e40000 221 222 /*---------------------------------------------------------------------------- 223 * BASE: PRNG_PRNG_TOP 224 *--------------------------------------------------------------------------*/ 225 226 #define PRNG_PRNG_TOP_BASE 0x01e50000 227 #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 228 #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 229 230 /*---------------------------------------------------------------------------- 231 * BASE: PCNOC_0_BUS_TIMEOUT 232 *--------------------------------------------------------------------------*/ 233 234 #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 235 #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 236 #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 237 238 /*---------------------------------------------------------------------------- 239 * BASE: PCNOC_1_BUS_TIMEOUT 240 *--------------------------------------------------------------------------*/ 241 242 #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 243 #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 244 #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 245 246 /*---------------------------------------------------------------------------- 247 * BASE: PCNOC_2_BUS_TIMEOUT 248 *--------------------------------------------------------------------------*/ 249 250 #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 251 #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 252 #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 253 254 /*---------------------------------------------------------------------------- 255 * BASE: PCNOC_3_BUS_TIMEOUT 256 *--------------------------------------------------------------------------*/ 257 258 #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 259 #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 260 #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 261 262 /*---------------------------------------------------------------------------- 263 * BASE: SYSTEM_NOC 264 *--------------------------------------------------------------------------*/ 265 266 #define SYSTEM_NOC_BASE 0x01e80000 267 #define SYSTEM_NOC_BASE_SIZE 0x00003280 268 #define SYSTEM_NOC_BASE_PHYS 0x01e80000 269 270 /*---------------------------------------------------------------------------- 271 * BASE: PC_NOC 272 *--------------------------------------------------------------------------*/ 273 274 #define PC_NOC_BASE 0x01f00000 275 #define PC_NOC_BASE_SIZE 0x00001180 276 #define PC_NOC_BASE_PHYS 0x01f00000 277 278 /*---------------------------------------------------------------------------- 279 * BASE: WLAON_WL_AON_REG 280 *--------------------------------------------------------------------------*/ 281 282 #define WLAON_WL_AON_REG_BASE 0x01f80000 283 #define WLAON_WL_AON_REG_BASE_SIZE 0x00000704 284 #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 285 286 /*---------------------------------------------------------------------------- 287 * BASE: SYSPM_SYSPM_REG 288 *--------------------------------------------------------------------------*/ 289 290 #define SYSPM_SYSPM_REG_BASE 0x01f82000 291 #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 292 #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 293 294 /*---------------------------------------------------------------------------- 295 * BASE: PMU_WLAN_PMU 296 *--------------------------------------------------------------------------*/ 297 298 #define PMU_WLAN_PMU_BASE 0x01f88000 299 #define PMU_WLAN_PMU_BASE_SIZE 0x00000338 300 #define PMU_WLAN_PMU_BASE_PHYS 0x01f88000 301 302 /*---------------------------------------------------------------------------- 303 * BASE: PMU_NOC 304 *--------------------------------------------------------------------------*/ 305 306 #define PMU_NOC_BASE 0x01f8a000 307 #define PMU_NOC_BASE_SIZE 0x00000080 308 #define PMU_NOC_BASE_PHYS 0x01f8a000 309 310 /*---------------------------------------------------------------------------- 311 * BASE: PCIE_ATU_REGION 312 *--------------------------------------------------------------------------*/ 313 314 #define PCIE_ATU_REGION_BASE 0x04000000 315 #define PCIE_ATU_REGION_BASE_SIZE 0x100000000 316 #define PCIE_ATU_REGION_BASE_PHYS 0x04000000 317 318 /*---------------------------------------------------------------------------- 319 * BASE: PCIE_ATU_REGION_SIZE 320 *--------------------------------------------------------------------------*/ 321 322 #define PCIE_ATU_REGION_SIZE_BASE 0x40000000 323 #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 324 #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 325 326 /*---------------------------------------------------------------------------- 327 * BASE: PCIE_ATU_REGION_END 328 *--------------------------------------------------------------------------*/ 329 330 #define PCIE_ATU_REGION_END_BASE 0x43ffffff 331 #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 332 #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff 333 334 335 #endif /* __MSMHWIOBASE_H__ */ 336