1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_DESTINATION_RING_H_ 18 #define _REO_DESTINATION_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_mpdu_desc_info.h" 24 #include "rx_msdu_desc_info.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 30 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 31 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 32 // 6 rx_reo_queue_desc_addr_31_0[31:0] 33 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 34 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22] 35 // 9 reo_destination_struct_signature[31:0] 36 // 10 reserved_10a[31:0] 37 // 11 reserved_11a[31:0] 38 // 12 reserved_12a[31:0] 39 // 13 reserved_13a[31:0] 40 // 14 reserved_14a[31:0] 41 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 46 47 struct reo_destination_ring { 48 struct buffer_addr_info buf_or_link_desc_addr_info; 49 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 50 struct rx_msdu_desc_info rx_msdu_desc_info_details; 51 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 52 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 53 reo_dest_buffer_type : 1, //[8] 54 reo_push_reason : 2, //[10:9] 55 reo_error_code : 5, //[15:11] 56 receive_queue_number : 16; //[31:16] 57 uint32_t soft_reorder_info_valid : 1, //[0] 58 reorder_opcode : 4, //[4:1] 59 reorder_slot_index : 8, //[12:5] 60 mpdu_fragment_number : 4, //[16:13] 61 captured_msdu_data_size : 4, //[20:17] 62 sw_exception : 1, //[21] 63 reserved_8a : 10; //[31:22] 64 uint32_t reo_destination_struct_signature: 32; //[31:0] 65 uint32_t reserved_10a : 32; //[31:0] 66 uint32_t reserved_11a : 32; //[31:0] 67 uint32_t reserved_12a : 32; //[31:0] 68 uint32_t reserved_13a : 32; //[31:0] 69 uint32_t reserved_14a : 32; //[31:0] 70 uint32_t reserved_15 : 20, //[19:0] 71 ring_id : 8, //[27:20] 72 looping_count : 4; //[31:28] 73 }; 74 75 /* 76 77 struct buffer_addr_info buf_or_link_desc_addr_info 78 79 Consumer: REO/SW/FW 80 81 Producer: RXDMA 82 83 84 85 Details of the physical address of the a buffer or MSDU 86 link descriptor 87 88 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 89 90 Consumer: REO/SW/FW 91 92 Producer: RXDMA 93 94 95 96 General information related to the MPDU that is passed 97 on from REO entrance ring to the REO destination ring 98 99 struct rx_msdu_desc_info rx_msdu_desc_info_details 100 101 General information related to the MSDU that is passed 102 on from RXDMA all the way to to the REO destination ring. 103 104 rx_reo_queue_desc_addr_31_0 105 106 Consumer: REO 107 108 Producer: RXDMA 109 110 111 112 Address (lower 32 bits) of the REO queue descriptor. 113 114 <legal all> 115 116 rx_reo_queue_desc_addr_39_32 117 118 Consumer: REO 119 120 Producer: RXDMA 121 122 123 124 Address (upper 8 bits) of the REO queue descriptor. 125 126 <legal all> 127 128 reo_dest_buffer_type 129 130 Indicates the type of address provided in the 131 'Buf_or_link_desc_addr_info' 132 133 134 135 <enum 0 MSDU_buf_address> The address of an MSDU buffer 136 137 <enum 1 MSDU_link_desc_address> The address of the MSDU 138 link descriptor. 139 140 141 142 <legal all> 143 144 reo_push_reason 145 146 Indicates why REO pushed the frame to this exit ring 147 148 149 150 <enum 0 reo_error_detected> Reo detected an error an 151 pushed this frame to this queue 152 153 <enum 1 reo_routing_instruction> Reo pushed the frame to 154 this queue per received routing instructions. No error 155 within REO was detected 156 157 158 159 160 161 <legal 0 - 1> 162 163 reo_error_code 164 165 Field only valid when 'Reo_push_reason' set to 166 'reo_error_detected'. 167 168 169 170 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 171 provided in the REO_ENTRANCE ring is set to 0 172 173 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 174 valid bit is NOT set 175 176 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 177 session having been setup. 178 179 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 180 SSN, Retry bit set: duplicate frame 181 182 <enum 4 ba_duplicate> BA session, duplicate frame 183 184 <enum 5 regular_frame_2k_jump> A normal (management/data 185 frame) received with 2K jump in SN 186 187 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 188 in SSN 189 190 <enum 7 regular_frame_OOR> A normal (management/data 191 frame) received with SN falling within the OOR window 192 193 <enum 8 bar_frame_OOR> A bar received with SSN falling 194 within the OOR window 195 196 <enum 9 bar_frame_no_ba_session> A bar received without 197 a BA session 198 199 <enum 10 bar_frame_sn_equals_ssn> A bar received with 200 SSN equal to SN 201 202 <enum 11 pn_check_failed> PN Check Failed packet. 203 204 <enum 12 2k_error_handling_flag_set> Frame is forwarded 205 as a result of the 'Seq_2k_error_detected_flag' been set in 206 the REO Queue descriptor 207 208 <enum 13 pn_error_handling_flag_set> Frame is forwarded 209 as a result of the 'pn_error_detected_flag' been set in the 210 REO Queue descriptor 211 212 <enum 14 queue_descriptor_blocked_set> Frame is 213 forwarded as a result of the queue descriptor(address) being 214 blocked as SW/FW seems to be currently in the process of 215 making updates to this descriptor... 216 217 218 219 <legal 0-14> 220 221 receive_queue_number 222 223 This field in NOT valid (should be set to 0), when 224 SW_exception is set. 225 226 This field indicates the REO MPDU reorder queue ID from 227 which this frame originated. This field is populated from a 228 field with the same name in the RX_REO_QUEUE descriptor. 229 230 <legal all> 231 232 soft_reorder_info_valid 233 234 This field in NOT valid (should be set to 0), when 235 SW_exception is set. 236 237 When set, REO has been instructed to not perform the 238 actual re-ordering of frames for this queue, but just to 239 insert the reorder opcodes 240 241 <legal all> 242 243 reorder_opcode 244 245 Field is valid when 'Soft_reorder_info_valid' is set. 246 This field is always valid for debug purpose as well. 247 248 Details are in the MLD. 249 250 251 252 <enum 0 invalid> 253 254 <enum 1 fwdcur_fwdbuf> 255 256 <enum 2 fwdbuf_fwdcur> 257 258 <enum 3 qcur> 259 260 <enum 4 fwdbuf_qcur> 261 262 <enum 5 fwdbuf_drop> 263 264 <enum 6 fwdall_drop> 265 266 <enum 7 fwdall_qcur> 267 268 <enum 8 reserved_reo_opcode_1> 269 270 <enum 9 dropcur> the error reason code is in 271 reo_error_code field. 272 273 <enum 10 reserved_reo_opcode_2> 274 275 <enum 11 reserved_reo_opcode_3> 276 277 <enum 12 reserved_reo_opcode_4> 278 279 <enum 13 reserved_reo_opcode_5> 280 281 <enum 14 reserved_reo_opcode_6> 282 283 <enum 15 reserved_reo_opcode_7> 284 285 286 287 <legal all> 288 289 reorder_slot_index 290 291 Field only valid when 'Soft_reorder_info_valid' is set. 292 293 294 295 TODO: add description 296 297 298 299 <legal all> 300 301 mpdu_fragment_number 302 303 Field only valid when Rx_mpdu_desc_info_details. 304 Fragment_flag is set. 305 306 307 308 The fragment number from the 802.11 header. 309 310 311 312 Note that the sequence number is embedded in the field: 313 Rx_mpdu_desc_info_details. Mpdu_sequence_number 314 315 316 317 <legal all> 318 319 captured_msdu_data_size 320 321 The number of following REO_DESTINATION STRUCTs that 322 have been replaced with msdu_data extracted from the 323 msdu_buffer and copied into the ring for easy FW/SW access. 324 325 Note that it is possible that these STRUCTs wrap around 326 the end of the ring. 327 328 Feature supported only in HastingsPrime 329 330 <legal 0-4> 331 332 sw_exception 333 334 This field has the same setting as the SW_exception 335 field in the corresponding REO_entrance_ring descriptor. 336 337 When set, the REO entrance descriptor is generated by 338 FW, and the MPDU was processed in the following way: 339 340 - NO re-order function is needed. 341 342 - MPDU delinking is determined by the setting of 343 Entrance ring field: SW_excection_mpdu_delink 344 345 - Destination ring selection is based on the setting of 346 347 Feature supported only in HastingsPrime 348 349 <legal all> 350 351 reserved_8a 352 353 <legal 0> 354 355 reo_destination_struct_signature 356 357 Set to value 0x8888_88888 when msdu capture mode is 358 enabled for this ring (supported only in HastingsPrime) 359 360 <legal 0, 2290649224 > 361 362 reserved_10a 363 364 <legal 0> 365 366 reserved_11a 367 368 <legal 0> 369 370 reserved_12a 371 372 <legal 0> 373 374 reserved_13a 375 376 <legal 0> 377 378 reserved_14a 379 380 <legal 0> 381 382 reserved_15 383 384 <legal 0> 385 386 ring_id 387 388 The buffer pointer ring ID. 389 390 0 refers to the IDLE ring 391 392 1 - N refers to other rings 393 394 395 396 Helps with debugging when dumping ring contents. 397 398 <legal all> 399 400 looping_count 401 402 A count value that indicates the number of times the 403 producer of entries into this Ring has looped around the 404 ring. 405 406 At initialization time, this value is set to 0. On the 407 first loop, this value is set to 1. After the max value is 408 reached allowed by the number of bits for this field, the 409 count value continues with 0 again. 410 411 In case SW is the consumer of the ring entries, it can 412 use this field to figure out up to where the producer of 413 entries has created new entries. This eliminates the need to 414 check where the head pointer' of the ring is located once 415 the SW starts processing an interrupt indicating that new 416 entries have been put into this ring... 417 418 419 420 Also note that SW if it wants only needs to look at the 421 LSB bit of this count value. 422 423 <legal all> 424 */ 425 426 427 /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */ 428 429 430 /* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 431 432 Address (lower 32 bits) of the MSDU buffer OR 433 MSDU_EXTENSION descriptor OR Link Descriptor 434 435 436 437 In case of 'NULL' pointer, this field is set to 0 438 439 <legal all> 440 */ 441 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 442 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 443 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 444 445 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 446 447 Address (upper 8 bits) of the MSDU buffer OR 448 MSDU_EXTENSION descriptor OR Link Descriptor 449 450 451 452 In case of 'NULL' pointer, this field is set to 0 453 454 <legal all> 455 */ 456 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 457 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 458 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 459 460 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 461 462 Consumer: WBM 463 464 Producer: SW/FW 465 466 467 468 In case of 'NULL' pointer, this field is set to 0 469 470 471 472 Indicates to which buffer manager the buffer OR 473 MSDU_EXTENSION descriptor OR link descriptor that is being 474 pointed to shall be returned after the frame has been 475 processed. It is used by WBM for routing purposes. 476 477 478 479 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 480 to the WMB buffer idle list 481 482 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 483 returned to the WMB idle link descriptor idle list 484 485 <enum 2 FW_BM> This buffer shall be returned to the FW 486 487 <enum 3 SW0_BM> This buffer shall be returned to the SW, 488 ring 0 489 490 <enum 4 SW1_BM> This buffer shall be returned to the SW, 491 ring 1 492 493 <enum 5 SW2_BM> This buffer shall be returned to the SW, 494 ring 2 495 496 <enum 6 SW3_BM> This buffer shall be returned to the SW, 497 ring 3 498 499 <enum 7 SW4_BM> This buffer shall be returned to the SW, 500 ring 4 501 502 503 504 <legal all> 505 */ 506 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 507 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 508 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 509 510 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 511 512 Cookie field exclusively used by SW. 513 514 515 516 In case of 'NULL' pointer, this field is set to 0 517 518 519 520 HW ignores the contents, accept that it passes the 521 programmed value on to other descriptors together with the 522 physical address 523 524 525 526 Field can be used by SW to for example associate the 527 buffers physical address with the virtual address 528 529 The bit definitions as used by SW are within SW HLD 530 specification 531 532 533 534 NOTE: 535 536 The three most significant bits can have a special 537 meaning in case this struct is embedded in a TX_MPDU_DETAILS 538 STRUCT, and field transmit_bw_restriction is set 539 540 541 542 In case of NON punctured transmission: 543 544 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 545 546 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 547 548 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 549 550 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 551 552 553 554 In case of punctured transmission: 555 556 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 557 558 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 559 560 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 561 562 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 563 564 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 565 566 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 567 568 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 569 570 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 571 572 573 574 Note: a punctured transmission is indicated by the 575 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 576 TLV 577 578 579 580 <legal all> 581 */ 582 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 583 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 584 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 585 586 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 587 588 589 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 590 591 Consumer: REO/SW/FW 592 593 Producer: RXDMA 594 595 596 597 The number of MSDUs within the MPDU 598 599 <legal all> 600 */ 601 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 602 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 603 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 604 605 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 606 607 Consumer: REO/SW/FW 608 609 Producer: RXDMA 610 611 612 613 The field can have two different meanings based on the 614 setting of field 'BAR_frame': 615 616 617 618 'BAR_frame' is NOT set: 619 620 The MPDU sequence number of the received frame. 621 622 623 624 'BAR_frame' is set. 625 626 The MPDU Start sequence number from the BAR frame 627 628 <legal all> 629 */ 630 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 631 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 632 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 633 634 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 635 636 Consumer: REO/SW/FW 637 638 Producer: RXDMA 639 640 641 642 When set, this MPDU is a fragment and REO should forward 643 this fragment MPDU to the REO destination ring without any 644 reorder checks, pn checks or bitmap update. This implies 645 that REO is forwarding the pointer to the MSDU link 646 descriptor. The destination ring is coming from a 647 programmable register setting in REO 648 649 650 651 <legal all> 652 */ 653 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 654 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 655 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 656 657 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 658 659 Consumer: REO/SW/FW 660 661 Producer: RXDMA 662 663 664 665 The retry bit setting from the MPDU header of the 666 received frame 667 668 <legal all> 669 */ 670 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 671 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 672 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 673 674 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 675 676 Consumer: REO/SW/FW 677 678 Producer: RXDMA 679 680 681 682 When set, the MPDU was received as part of an A-MPDU. 683 684 <legal all> 685 */ 686 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 687 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 688 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 689 690 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 691 692 Consumer: REO/SW/FW 693 694 Producer: RXDMA 695 696 697 698 When set, the received frame is a BAR frame. After 699 processing, this frame shall be pushed to SW or deleted. 700 701 <legal all> 702 */ 703 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 704 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 705 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 706 707 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 708 709 Consumer: REO/SW/FW 710 711 Producer: RXDMA 712 713 714 715 Copied here by RXDMA from RX_MPDU_END 716 717 When not set, REO will Not perform a PN sequence number 718 check 719 */ 720 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 721 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 722 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 723 724 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 725 726 When set, OLE found a valid SA entry for all MSDUs in 727 this MPDU 728 729 <legal all> 730 */ 731 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 732 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 733 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 734 735 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 736 737 When set, at least 1 MSDU within the MPDU has an 738 unsuccessful MAC source address search due to the expiration 739 of the search timer. 740 741 <legal all> 742 */ 743 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 744 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 745 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 746 747 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 748 749 When set, OLE found a valid DA entry for all MSDUs in 750 this MPDU 751 752 <legal all> 753 */ 754 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 755 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 756 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 757 758 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 759 760 Field Only valid if da_is_valid is set 761 762 763 764 When set, at least one of the DA addresses is a 765 Multicast or Broadcast address. 766 767 <legal all> 768 */ 769 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 770 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 771 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 772 773 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 774 775 When set, at least 1 MSDU within the MPDU has an 776 unsuccessful MAC destination address search due to the 777 expiration of the search timer. 778 779 <legal all> 780 */ 781 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 782 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 783 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 784 785 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 786 787 Field only valid when first_msdu_in_mpdu_flag is set. 788 789 790 791 When set, the contents in the MSDU buffer contains a 792 'RAW' MPDU. This 'RAW' MPDU might be spread out over 793 multiple MSDU buffers. 794 795 <legal all> 796 */ 797 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 798 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 799 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 800 801 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 802 803 The More Fragment bit setting from the MPDU header of 804 the received frame 805 806 807 808 <legal all> 809 */ 810 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 811 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 812 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 813 814 /* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 815 816 Meta data that SW has programmed in the Peer table entry 817 of the transmitting STA. 818 819 <legal all> 820 */ 821 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 822 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 823 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 824 825 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 826 827 828 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 829 830 Parsed from RX_MSDU_END TLV . In the case MSDU spans 831 over multiple buffers, this field will be valid in the Last 832 buffer used by the MSDU 833 834 835 836 <enum 0 Not_first_msdu> This is not the first MSDU in 837 the MPDU. 838 839 <enum 1 first_msdu> This MSDU is the first one in the 840 MPDU. 841 842 843 844 <legal all> 845 */ 846 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 847 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 848 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 849 850 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 851 852 Consumer: WBM/REO/SW/FW 853 854 Producer: RXDMA 855 856 857 858 Parsed from RX_MSDU_END TLV . In the case MSDU spans 859 over multiple buffers, this field will be valid in the Last 860 buffer used by the MSDU 861 862 863 864 <enum 0 Not_last_msdu> There are more MSDUs linked to 865 this MSDU that belongs to this MPDU 866 867 <enum 1 Last_msdu> this MSDU is the last one in the 868 MPDU. This setting is only allowed in combination with 869 'Msdu_continuation' set to 0. This implies that when an msdu 870 is spread out over multiple buffers and thus 871 msdu_continuation is set, only for the very last buffer of 872 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 873 874 875 876 When both first_msdu_in_mpdu_flag and 877 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 878 belongs to only contains a single MSDU. 879 880 881 882 883 884 <legal all> 885 */ 886 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 887 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 888 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 889 890 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 891 892 When set, this MSDU buffer was not able to hold the 893 entire MSDU. The next buffer will therefor contain 894 additional information related to this MSDU. 895 896 897 898 <legal all> 899 */ 900 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 901 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 902 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 903 904 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 905 906 Parsed from RX_MSDU_START TLV . In the case MSDU spans 907 over multiple buffers, this field will be valid in the First 908 buffer used by MSDU. 909 910 911 912 Full MSDU length in bytes after decapsulation. 913 914 915 916 This field is still valid for MPDU frames without 917 A-MSDU. It still represents MSDU length after decapsulation 918 919 920 921 Or in case of RAW MPDUs, it indicates the length of the 922 entire MPDU (without FCS field) 923 924 <legal all> 925 */ 926 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 927 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 928 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 929 930 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 931 932 Parsed from RX_MSDU_END TLV . In the case MSDU spans 933 over multiple buffers, this field will be valid in the Last 934 buffer used by the MSDU 935 936 937 938 The ID of the REO exit ring where the MSDU frame shall 939 push after (MPDU level) reordering has finished. 940 941 942 943 <enum 0 reo_destination_tcl> Reo will push the frame 944 into the REO2TCL ring 945 946 <enum 1 reo_destination_sw1> Reo will push the frame 947 into the REO2SW1 ring 948 949 <enum 2 reo_destination_sw2> Reo will push the frame 950 into the REO2SW2 ring 951 952 <enum 3 reo_destination_sw3> Reo will push the frame 953 into the REO2SW3 ring 954 955 <enum 4 reo_destination_sw4> Reo will push the frame 956 into the REO2SW4 ring 957 958 <enum 5 reo_destination_release> Reo will push the frame 959 into the REO_release ring 960 961 <enum 6 reo_destination_fw> Reo will push the frame into 962 the REO2FW ring 963 964 <enum 7 reo_destination_sw5> Reo will push the frame 965 into the REO2SW5 ring (REO remaps this in chips without 966 REO2SW5 ring, e.g. Pine) 967 968 <enum 8 reo_destination_sw6> Reo will push the frame 969 into the REO2SW6 ring (REO remaps this in chips without 970 REO2SW6 ring, e.g. Pine) 971 972 <enum 9 reo_destination_9> REO remaps this <enum 10 973 reo_destination_10> REO remaps this 974 975 <enum 11 reo_destination_11> REO remaps this 976 977 <enum 12 reo_destination_12> REO remaps this <enum 13 978 reo_destination_13> REO remaps this 979 980 <enum 14 reo_destination_14> REO remaps this 981 982 <enum 15 reo_destination_15> REO remaps this 983 984 <enum 16 reo_destination_16> REO remaps this 985 986 <enum 17 reo_destination_17> REO remaps this 987 988 <enum 18 reo_destination_18> REO remaps this 989 990 <enum 19 reo_destination_19> REO remaps this 991 992 <enum 20 reo_destination_20> REO remaps this 993 994 <enum 21 reo_destination_21> REO remaps this 995 996 <enum 22 reo_destination_22> REO remaps this 997 998 <enum 23 reo_destination_23> REO remaps this 999 1000 <enum 24 reo_destination_24> REO remaps this 1001 1002 <enum 25 reo_destination_25> REO remaps this 1003 1004 <enum 26 reo_destination_26> REO remaps this 1005 1006 <enum 27 reo_destination_27> REO remaps this 1007 1008 <enum 28 reo_destination_28> REO remaps this 1009 1010 <enum 29 reo_destination_29> REO remaps this 1011 1012 <enum 30 reo_destination_30> REO remaps this 1013 1014 <enum 31 reo_destination_31> REO remaps this 1015 1016 1017 1018 <legal all> 1019 */ 1020 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 1021 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1022 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1023 1024 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1025 1026 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1027 over multiple buffers, this field will be valid in the Last 1028 buffer used by the MSDU 1029 1030 1031 1032 When set, REO shall drop this MSDU and not forward it to 1033 any other ring... 1034 1035 <legal all> 1036 */ 1037 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 1038 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1039 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1040 1041 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1042 1043 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1044 over multiple buffers, this field will be valid in the Last 1045 buffer used by the MSDU 1046 1047 1048 1049 Indicates that OLE found a valid SA entry for this MSDU 1050 1051 <legal all> 1052 */ 1053 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 1054 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1055 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1056 1057 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1058 1059 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1060 over multiple buffers, this field will be valid in the Last 1061 buffer used by the MSDU 1062 1063 1064 1065 Indicates an unsuccessful MAC source address search due 1066 to the expiring of the search timer for this MSDU 1067 1068 <legal all> 1069 */ 1070 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 1071 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1072 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1073 1074 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1075 1076 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1077 over multiple buffers, this field will be valid in the Last 1078 buffer used by the MSDU 1079 1080 1081 1082 Indicates that OLE found a valid DA entry for this MSDU 1083 1084 <legal all> 1085 */ 1086 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 1087 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1088 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1089 1090 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1091 1092 Field Only valid if da_is_valid is set 1093 1094 1095 1096 Indicates the DA address was a Multicast of Broadcast 1097 address for this MSDU 1098 1099 <legal all> 1100 */ 1101 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 1102 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1103 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1104 1105 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1106 1107 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1108 over multiple buffers, this field will be valid in the Last 1109 buffer used by the MSDU 1110 1111 1112 1113 Indicates an unsuccessful MAC destination address search 1114 due to the expiring of the search timer for this MSDU 1115 1116 <legal all> 1117 */ 1118 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 1119 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1120 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1121 1122 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1123 1124 <legal 0> 1125 */ 1126 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 1127 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1128 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1129 1130 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1131 1132 <legal 0> 1133 */ 1134 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 1135 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1136 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1137 1138 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 1139 1140 Consumer: REO 1141 1142 Producer: RXDMA 1143 1144 1145 1146 Address (lower 32 bits) of the REO queue descriptor. 1147 1148 <legal all> 1149 */ 1150 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 1151 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1152 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1153 1154 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 1155 1156 Consumer: REO 1157 1158 Producer: RXDMA 1159 1160 1161 1162 Address (upper 8 bits) of the REO queue descriptor. 1163 1164 <legal all> 1165 */ 1166 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 1167 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1168 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1169 1170 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 1171 1172 Indicates the type of address provided in the 1173 'Buf_or_link_desc_addr_info' 1174 1175 1176 1177 <enum 0 MSDU_buf_address> The address of an MSDU buffer 1178 1179 <enum 1 MSDU_link_desc_address> The address of the MSDU 1180 link descriptor. 1181 1182 1183 1184 <legal all> 1185 */ 1186 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 1187 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 1188 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 1189 1190 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 1191 1192 Indicates why REO pushed the frame to this exit ring 1193 1194 1195 1196 <enum 0 reo_error_detected> Reo detected an error an 1197 pushed this frame to this queue 1198 1199 <enum 1 reo_routing_instruction> Reo pushed the frame to 1200 this queue per received routing instructions. No error 1201 within REO was detected 1202 1203 1204 1205 1206 1207 <legal 0 - 1> 1208 */ 1209 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 1210 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 1211 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 1212 1213 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 1214 1215 Field only valid when 'Reo_push_reason' set to 1216 'reo_error_detected'. 1217 1218 1219 1220 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 1221 provided in the REO_ENTRANCE ring is set to 0 1222 1223 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 1224 valid bit is NOT set 1225 1226 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 1227 session having been setup. 1228 1229 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 1230 SSN, Retry bit set: duplicate frame 1231 1232 <enum 4 ba_duplicate> BA session, duplicate frame 1233 1234 <enum 5 regular_frame_2k_jump> A normal (management/data 1235 frame) received with 2K jump in SN 1236 1237 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 1238 in SSN 1239 1240 <enum 7 regular_frame_OOR> A normal (management/data 1241 frame) received with SN falling within the OOR window 1242 1243 <enum 8 bar_frame_OOR> A bar received with SSN falling 1244 within the OOR window 1245 1246 <enum 9 bar_frame_no_ba_session> A bar received without 1247 a BA session 1248 1249 <enum 10 bar_frame_sn_equals_ssn> A bar received with 1250 SSN equal to SN 1251 1252 <enum 11 pn_check_failed> PN Check Failed packet. 1253 1254 <enum 12 2k_error_handling_flag_set> Frame is forwarded 1255 as a result of the 'Seq_2k_error_detected_flag' been set in 1256 the REO Queue descriptor 1257 1258 <enum 13 pn_error_handling_flag_set> Frame is forwarded 1259 as a result of the 'pn_error_detected_flag' been set in the 1260 REO Queue descriptor 1261 1262 <enum 14 queue_descriptor_blocked_set> Frame is 1263 forwarded as a result of the queue descriptor(address) being 1264 blocked as SW/FW seems to be currently in the process of 1265 making updates to this descriptor... 1266 1267 1268 1269 <legal 0-14> 1270 */ 1271 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 1272 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 1273 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 1274 1275 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 1276 1277 This field in NOT valid (should be set to 0), when 1278 SW_exception is set. 1279 1280 This field indicates the REO MPDU reorder queue ID from 1281 which this frame originated. This field is populated from a 1282 field with the same name in the RX_REO_QUEUE descriptor. 1283 1284 <legal all> 1285 */ 1286 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 1287 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 1288 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 1289 1290 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 1291 1292 This field in NOT valid (should be set to 0), when 1293 SW_exception is set. 1294 1295 When set, REO has been instructed to not perform the 1296 actual re-ordering of frames for this queue, but just to 1297 insert the reorder opcodes 1298 1299 <legal all> 1300 */ 1301 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 1302 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 1303 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 1304 1305 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 1306 1307 Field is valid when 'Soft_reorder_info_valid' is set. 1308 This field is always valid for debug purpose as well. 1309 1310 Details are in the MLD. 1311 1312 1313 1314 <enum 0 invalid> 1315 1316 <enum 1 fwdcur_fwdbuf> 1317 1318 <enum 2 fwdbuf_fwdcur> 1319 1320 <enum 3 qcur> 1321 1322 <enum 4 fwdbuf_qcur> 1323 1324 <enum 5 fwdbuf_drop> 1325 1326 <enum 6 fwdall_drop> 1327 1328 <enum 7 fwdall_qcur> 1329 1330 <enum 8 reserved_reo_opcode_1> 1331 1332 <enum 9 dropcur> the error reason code is in 1333 reo_error_code field. 1334 1335 <enum 10 reserved_reo_opcode_2> 1336 1337 <enum 11 reserved_reo_opcode_3> 1338 1339 <enum 12 reserved_reo_opcode_4> 1340 1341 <enum 13 reserved_reo_opcode_5> 1342 1343 <enum 14 reserved_reo_opcode_6> 1344 1345 <enum 15 reserved_reo_opcode_7> 1346 1347 1348 1349 <legal all> 1350 */ 1351 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 1352 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 1353 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 1354 1355 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 1356 1357 Field only valid when 'Soft_reorder_info_valid' is set. 1358 1359 1360 1361 TODO: add description 1362 1363 1364 1365 <legal all> 1366 */ 1367 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 1368 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 1369 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 1370 1371 /* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER 1372 1373 Field only valid when Rx_mpdu_desc_info_details. 1374 Fragment_flag is set. 1375 1376 1377 1378 The fragment number from the 802.11 header. 1379 1380 1381 1382 Note that the sequence number is embedded in the field: 1383 Rx_mpdu_desc_info_details. Mpdu_sequence_number 1384 1385 1386 1387 <legal all> 1388 */ 1389 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 1390 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 1391 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 1392 1393 /* Description REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE 1394 1395 The number of following REO_DESTINATION STRUCTs that 1396 have been replaced with msdu_data extracted from the 1397 msdu_buffer and copied into the ring for easy FW/SW access. 1398 1399 Note that it is possible that these STRUCTs wrap around 1400 the end of the ring. 1401 1402 Feature supported only in HastingsPrime 1403 1404 <legal 0-4> 1405 */ 1406 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 1407 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 1408 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 1409 1410 /* Description REO_DESTINATION_RING_8_SW_EXCEPTION 1411 1412 This field has the same setting as the SW_exception 1413 field in the corresponding REO_entrance_ring descriptor. 1414 1415 When set, the REO entrance descriptor is generated by 1416 FW, and the MPDU was processed in the following way: 1417 1418 - NO re-order function is needed. 1419 1420 - MPDU delinking is determined by the setting of 1421 Entrance ring field: SW_excection_mpdu_delink 1422 1423 - Destination ring selection is based on the setting of 1424 1425 Feature supported only in HastingsPrime 1426 1427 <legal all> 1428 */ 1429 #define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 1430 #define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 1431 #define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 1432 1433 /* Description REO_DESTINATION_RING_8_RESERVED_8A 1434 1435 <legal 0> 1436 */ 1437 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 1438 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 1439 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 1440 1441 /* Description REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE 1442 1443 Set to value 0x8888_88888 when msdu capture mode is 1444 enabled for this ring (supported only in HastingsPrime) 1445 1446 <legal 0, 2290649224 > 1447 */ 1448 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 1449 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 1450 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff 1451 1452 /* Description REO_DESTINATION_RING_10_RESERVED_10A 1453 1454 <legal 0> 1455 */ 1456 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 1457 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 1458 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 1459 1460 /* Description REO_DESTINATION_RING_11_RESERVED_11A 1461 1462 <legal 0> 1463 */ 1464 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 1465 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 1466 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 1467 1468 /* Description REO_DESTINATION_RING_12_RESERVED_12A 1469 1470 <legal 0> 1471 */ 1472 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 1473 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 1474 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 1475 1476 /* Description REO_DESTINATION_RING_13_RESERVED_13A 1477 1478 <legal 0> 1479 */ 1480 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 1481 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 1482 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 1483 1484 /* Description REO_DESTINATION_RING_14_RESERVED_14A 1485 1486 <legal 0> 1487 */ 1488 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 1489 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 1490 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 1491 1492 /* Description REO_DESTINATION_RING_15_RESERVED_15 1493 1494 <legal 0> 1495 */ 1496 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 1497 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 1498 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 1499 1500 /* Description REO_DESTINATION_RING_15_RING_ID 1501 1502 The buffer pointer ring ID. 1503 1504 0 refers to the IDLE ring 1505 1506 1 - N refers to other rings 1507 1508 1509 1510 Helps with debugging when dumping ring contents. 1511 1512 <legal all> 1513 */ 1514 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 1515 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 1516 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 1517 1518 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 1519 1520 A count value that indicates the number of times the 1521 producer of entries into this Ring has looped around the 1522 ring. 1523 1524 At initialization time, this value is set to 0. On the 1525 first loop, this value is set to 1. After the max value is 1526 reached allowed by the number of bits for this field, the 1527 count value continues with 0 again. 1528 1529 In case SW is the consumer of the ring entries, it can 1530 use this field to figure out up to where the producer of 1531 entries has created new entries. This eliminates the need to 1532 check where the head pointer' of the ring is located once 1533 the SW starts processing an interrupt indicating that new 1534 entries have been put into this ring... 1535 1536 1537 1538 Also note that SW if it wants only needs to look at the 1539 LSB bit of this count value. 1540 1541 <legal all> 1542 */ 1543 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 1544 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 1545 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 1546 1547 1548 #endif // _REO_DESTINATION_RING_H_ 1549