1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_ENTRANCE_RING_H_ 18 #define _REO_ENTRANCE_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_details.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 28 // 4 rx_reo_queue_desc_addr_31_0[31:0] 29 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 30 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19] 31 // 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] 32 // 33 // ################ END SUMMARY ################# 34 35 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 36 37 struct reo_entrance_ring { 38 struct rx_mpdu_details reo_level_mpdu_frame_info; 39 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 40 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 41 rounded_mpdu_byte_count : 14, //[21:8] 42 reo_destination_indication : 5, //[26:22] 43 frameless_bar : 1, //[27] 44 reserved_5a : 4; //[31:28] 45 uint32_t rxdma_push_reason : 2, //[1:0] 46 rxdma_error_code : 5, //[6:2] 47 mpdu_fragment_number : 4, //[10:7] 48 sw_exception : 1, //[11] 49 sw_exception_mpdu_delink : 1, //[12] 50 sw_exception_destination_ring_valid: 1, //[13] 51 sw_exception_destination_ring : 5, //[18:14] 52 reserved_6a : 13; //[31:19] 53 uint32_t phy_ppdu_id : 16, //[15:0] 54 reserved_7a : 4, //[19:16] 55 ring_id : 8, //[27:20] 56 looping_count : 4; //[31:28] 57 }; 58 59 /* 60 61 struct rx_mpdu_details reo_level_mpdu_frame_info 62 63 Consumer: REO 64 65 Producer: RXDMA 66 67 68 69 Details related to the MPDU being pushed into the REO 70 71 rx_reo_queue_desc_addr_31_0 72 73 Consumer: REO 74 75 Producer: RXDMA 76 77 78 79 Address (lower 32 bits) of the REO queue descriptor. 80 81 <legal all> 82 83 rx_reo_queue_desc_addr_39_32 84 85 Consumer: REO 86 87 Producer: RXDMA 88 89 90 91 Address (upper 8 bits) of the REO queue descriptor. 92 93 <legal all> 94 95 rounded_mpdu_byte_count 96 97 An approximation of the number of bytes received in this 98 MPDU. 99 100 Used to keeps stats on the amount of data flowing 101 through a queue. 102 103 <legal all> 104 105 reo_destination_indication 106 107 RXDMA copy the MPDU's first MSDU's destination 108 indication field here. This is used for REO to be able to 109 re-route the packet to a different SW destination ring if 110 the packet is detected as error in REO. 111 112 113 114 The ID of the REO exit ring where the MSDU frame shall 115 push after (MPDU level) reordering has finished. 116 117 118 119 <enum 0 reo_destination_tcl> Reo will push the frame 120 into the REO2TCL ring 121 122 <enum 1 reo_destination_sw1> Reo will push the frame 123 into the REO2SW1 ring 124 125 <enum 2 reo_destination_sw2> Reo will push the frame 126 into the REO2SW2 ring 127 128 <enum 3 reo_destination_sw3> Reo will push the frame 129 into the REO2SW3 ring 130 131 <enum 4 reo_destination_sw4> Reo will push the frame 132 into the REO2SW4 ring 133 134 <enum 5 reo_destination_release> Reo will push the frame 135 into the REO_release ring 136 137 <enum 6 reo_destination_fw> Reo will push the frame into 138 the REO2FW ring 139 140 <enum 7 reo_destination_sw5> Reo will push the frame 141 into the REO2SW5 ring (REO remaps this in chips without 142 REO2SW5 ring, e.g. Pine) 143 144 <enum 8 reo_destination_sw6> Reo will push the frame 145 into the REO2SW6 ring (REO remaps this in chips without 146 REO2SW6 ring, e.g. Pine) 147 148 <enum 9 reo_destination_9> REO remaps this <enum 10 149 reo_destination_10> REO remaps this 150 151 <enum 11 reo_destination_11> REO remaps this 152 153 <enum 12 reo_destination_12> REO remaps this <enum 13 154 reo_destination_13> REO remaps this 155 156 <enum 14 reo_destination_14> REO remaps this 157 158 <enum 15 reo_destination_15> REO remaps this 159 160 <enum 16 reo_destination_16> REO remaps this 161 162 <enum 17 reo_destination_17> REO remaps this 163 164 <enum 18 reo_destination_18> REO remaps this 165 166 <enum 19 reo_destination_19> REO remaps this 167 168 <enum 20 reo_destination_20> REO remaps this 169 170 <enum 21 reo_destination_21> REO remaps this 171 172 <enum 22 reo_destination_22> REO remaps this 173 174 <enum 23 reo_destination_23> REO remaps this 175 176 <enum 24 reo_destination_24> REO remaps this 177 178 <enum 25 reo_destination_25> REO remaps this 179 180 <enum 26 reo_destination_26> REO remaps this 181 182 <enum 27 reo_destination_27> REO remaps this 183 184 <enum 28 reo_destination_28> REO remaps this 185 186 <enum 29 reo_destination_29> REO remaps this 187 188 <enum 30 reo_destination_30> REO remaps this 189 190 <enum 31 reo_destination_31> REO remaps this 191 192 193 194 <legal all> 195 196 frameless_bar 197 198 When set, this REO entrance ring struct contains BAR 199 info from a multi TID BAR frame. The original multi TID BAR 200 frame itself contained all the REO info for the first TID, 201 but all the subsequent TID info and their linkage to the REO 202 descriptors is passed down as 'frameless' BAR info. 203 204 205 206 The only fields valid in this descriptor when this bit 207 is set are: 208 209 Rx_reo_queue_desc_addr_31_0 210 211 RX_reo_queue_desc_addr_39_32 212 213 214 215 And within the 216 217 Reo_level_mpdu_frame_info: 218 219 Within Rx_mpdu_desc_info_details: 220 221 Mpdu_Sequence_number 222 223 BAR_frame 224 225 Peer_meta_data 226 227 All other fields shall be set to 0 228 229 230 231 <legal all> 232 233 reserved_5a 234 235 <legal 0> 236 237 rxdma_push_reason 238 239 Indicates why rxdma pushed the frame to this ring 240 241 242 243 This field is ignored by REO. 244 245 246 247 <enum 0 rxdma_error_detected> RXDMA detected an error an 248 pushed this frame to this queue 249 250 <enum 1 rxdma_routing_instruction> RXDMA pushed the 251 frame to this queue per received routing instructions. No 252 error within RXDMA was detected 253 254 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 255 result the MSDU link descriptor might not have the 256 last_msdu_in_mpdu_flag set, but instead WBM might just see a 257 NULL pointer in the MSDU link descriptor. This is to be 258 considered a normal condition for this scenario. 259 260 261 262 <legal 0 - 2> 263 264 rxdma_error_code 265 266 Field only valid when 'rxdma_push_reason' set to 267 'rxdma_error_detected'. 268 269 270 271 This field is ignored by REO. 272 273 274 275 <enum 0 rxdma_overflow_err>MPDU frame is not complete 276 due to a FIFO overflow error in RXPCU. 277 278 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 279 due to receiving incomplete MPDU from the PHY 280 281 282 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 283 error or CRYPTO received an encrypted frame, but did not get 284 a valid corresponding key id in the peer entry. 285 286 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 287 error 288 289 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 290 unencrypted frame error when encrypted was expected 291 292 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 293 length error 294 295 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 296 number of MSDUs allowed in an MPDU got exceeded 297 298 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 299 error 300 301 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 302 parsing error 303 304 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 305 during SA search 306 307 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 308 during DA search 309 310 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 311 timeout during flow search 312 313 <enum 13 rxdma_flush_request>RXDMA received a flush 314 request 315 316 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 317 present as well as a fragmented MPDU. A-MSDU defragmentation 318 is not supported in Lithium SW so this is treated as an 319 error. 320 321 mpdu_fragment_number 322 323 Field only valid when Reo_level_mpdu_frame_info. 324 Rx_mpdu_desc_info_details.Fragment_flag is set. 325 326 327 328 The fragment number from the 802.11 header. 329 330 331 332 Note that the sequence number is embedded in the field: 333 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 334 Mpdu_sequence_number 335 336 337 338 <legal all> 339 340 sw_exception 341 342 When not set, REO is performing all its default MPDU 343 processing operations, 344 345 When set, this REO entrance descriptor is generated by 346 FW, and should be processed as an exception. This implies: 347 348 NO re-order function is needed. 349 350 MPDU delinking is determined by the setting of field 351 SW_excection_mpdu_delink 352 353 Destination ring selection is based on the setting of 354 the field SW_exception_destination_ring_valid 355 356 In the destination ring descriptor set bit: 357 SW_exception_entry 358 359 Feature supported only in HastingsPrime 360 361 <legal all> 362 363 sw_exception_mpdu_delink 364 365 Field only valid when SW_exception is set. 366 367 1'b0: REO should NOT delink the MPDU, and thus pass this 368 MPDU on to the destination ring as is. This implies that in 369 the REO_DESTINATION_RING struct field 370 Buf_or_link_desc_addr_info should point to an MSDU link 371 descriptor 372 373 1'b1: REO should perform the normal MPDU delink into 374 MSDU operations. 375 376 Feature supported only in HastingsPrime 377 378 <legal all> 379 380 sw_exception_destination_ring_valid 381 382 Field only valid when SW_exception is set. 383 384 1'b0: REO shall push the MPDU (or delinked MPDU based on 385 the setting of SW_exception_mpdu_delink) to the destination 386 ring according to field reo_destination_indication. 387 388 1'b1: REO shall push the MPDU (or delinked MPDU based on 389 the setting of SW_exception_mpdu_delink) to the destination 390 ring according to field SW_exception_destination_ring. 391 392 Feature supported only in HastingsPrime 393 394 <legal all> 395 396 sw_exception_destination_ring 397 398 Field only valid when fields SW_exception and 399 SW_exception_destination_ring_valid are set. 400 401 The ID of the ring where REO shall push this frame. 402 403 <enum 0 reo_destination_tcl> Reo will push the frame 404 into the REO2TCL ring 405 406 <enum 1 reo_destination_sw1> Reo will push the frame 407 into the REO2SW1 ring 408 409 <enum 2 reo_destination_sw2> Reo will push the frame 410 into the REO2SW1 ring 411 412 <enum 3 reo_destination_sw3> Reo will push the frame 413 into the REO2SW1 ring 414 415 <enum 4 reo_destination_sw4> Reo will push the frame 416 into the REO2SW1 ring 417 418 <enum 5 reo_destination_release> Reo will push the frame 419 into the REO_release ring 420 421 <enum 6 reo_destination_fw> Reo will push the frame into 422 the REO2FW ring 423 424 <enum 7 reo_destination_sw5> REO remaps this 425 426 <enum 8 reo_destination_sw6> REO remaps this 427 428 <enum 9 reo_destination_9> REO remaps this 429 430 <enum 10 reo_destination_10> REO remaps this 431 432 <enum 11 reo_destination_11> REO remaps this 433 434 <enum 12 reo_destination_12> REO remaps this <enum 13 435 reo_destination_13> REO remaps this 436 437 <enum 14 reo_destination_14> REO remaps this 438 439 <enum 15 reo_destination_15> REO remaps this 440 441 <enum 16 reo_destination_16> REO remaps this 442 443 <enum 17 reo_destination_17> REO remaps this 444 445 <enum 18 reo_destination_18> REO remaps this 446 447 <enum 19 reo_destination_19> REO remaps this 448 449 <enum 20 reo_destination_20> REO remaps this 450 451 <enum 21 reo_destination_21> REO remaps this 452 453 <enum 22 reo_destination_22> REO remaps this 454 455 <enum 23 reo_destination_23> REO remaps this 456 457 <enum 24 reo_destination_24> REO remaps this 458 459 <enum 25 reo_destination_25> REO remaps this 460 461 <enum 26 reo_destination_26> REO remaps this 462 463 <enum 27 reo_destination_27> REO remaps this 464 465 <enum 28 reo_destination_28> REO remaps this 466 467 <enum 29 reo_destination_29> REO remaps this 468 469 <enum 30 reo_destination_30> REO remaps this 470 471 <enum 31 reo_destination_31> REO remaps this 472 473 474 475 Feature supported only in HastingsPrime 476 477 <legal all> 478 479 reserved_6a 480 481 <legal 0> 482 483 phy_ppdu_id 484 485 A PPDU counter value that PHY increments for every PPDU 486 received 487 488 The counter value wraps around. Pine RXDMA can be 489 configured to copy this from the RX_PPDU_START TLV for every 490 output descriptor. 491 492 493 494 This field is ignored by REO. 495 496 497 498 Feature supported only in Pine 499 500 <legal all> 501 502 reserved_7a 503 504 <legal 0> 505 506 ring_id 507 508 Consumer: SW/REO/DEBUG 509 510 Producer: SRNG (of RXDMA) 511 512 513 514 For debugging. 515 516 This field is filled in by the SRNG module. 517 518 It help to identify the ring that is being looked <legal 519 all> 520 521 looping_count 522 523 Consumer: SW/REO/DEBUG 524 525 Producer: SRNG (of RXDMA) 526 527 528 529 For debugging. 530 531 This field is filled in by the SRNG module. 532 533 534 535 A count value that indicates the number of times the 536 producer of entries into this Ring has looped around the 537 ring. 538 539 At initialization time, this value is set to 0. On the 540 first loop, this value is set to 1. After the max value is 541 reached allowed by the number of bits for this field, the 542 count value continues with 0 again. 543 544 545 546 In case SW is the consumer of the ring entries, it can 547 use this field to figure out up to where the producer of 548 entries has created new entries. This eliminates the need to 549 check where the head pointer' of the ring is located once 550 the SW starts processing an interrupt indicating that new 551 entries have been put into this ring... 552 553 554 555 Also note that SW if it wants only needs to look at the 556 LSB bit of this count value. 557 558 <legal all> 559 */ 560 561 562 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 563 564 565 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 566 567 568 /* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 569 570 Address (lower 32 bits) of the MSDU buffer OR 571 MSDU_EXTENSION descriptor OR Link Descriptor 572 573 574 575 In case of 'NULL' pointer, this field is set to 0 576 577 <legal all> 578 */ 579 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 580 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 581 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 582 583 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 584 585 Address (upper 8 bits) of the MSDU buffer OR 586 MSDU_EXTENSION descriptor OR Link Descriptor 587 588 589 590 In case of 'NULL' pointer, this field is set to 0 591 592 <legal all> 593 */ 594 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 595 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 596 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 597 598 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 599 600 Consumer: WBM 601 602 Producer: SW/FW 603 604 605 606 In case of 'NULL' pointer, this field is set to 0 607 608 609 610 Indicates to which buffer manager the buffer OR 611 MSDU_EXTENSION descriptor OR link descriptor that is being 612 pointed to shall be returned after the frame has been 613 processed. It is used by WBM for routing purposes. 614 615 616 617 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 618 to the WMB buffer idle list 619 620 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 621 returned to the WMB idle link descriptor idle list 622 623 <enum 2 FW_BM> This buffer shall be returned to the FW 624 625 <enum 3 SW0_BM> This buffer shall be returned to the SW, 626 ring 0 627 628 <enum 4 SW1_BM> This buffer shall be returned to the SW, 629 ring 1 630 631 <enum 5 SW2_BM> This buffer shall be returned to the SW, 632 ring 2 633 634 <enum 6 SW3_BM> This buffer shall be returned to the SW, 635 ring 3 636 637 <enum 7 SW4_BM> This buffer shall be returned to the SW, 638 ring 4 639 640 641 642 <legal all> 643 */ 644 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 645 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 646 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 647 648 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 649 650 Cookie field exclusively used by SW. 651 652 653 654 In case of 'NULL' pointer, this field is set to 0 655 656 657 658 HW ignores the contents, accept that it passes the 659 programmed value on to other descriptors together with the 660 physical address 661 662 663 664 Field can be used by SW to for example associate the 665 buffers physical address with the virtual address 666 667 The bit definitions as used by SW are within SW HLD 668 specification 669 670 671 672 NOTE: 673 674 The three most significant bits can have a special 675 meaning in case this struct is embedded in a TX_MPDU_DETAILS 676 STRUCT, and field transmit_bw_restriction is set 677 678 679 680 In case of NON punctured transmission: 681 682 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 683 684 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 685 686 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 687 688 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 689 690 691 692 In case of punctured transmission: 693 694 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 695 696 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 697 698 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 699 700 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 701 702 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 703 704 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 705 706 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 707 708 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 709 710 711 712 Note: a punctured transmission is indicated by the 713 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 714 TLV 715 716 717 718 <legal all> 719 */ 720 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 721 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 722 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 723 724 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 725 726 727 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 728 729 Consumer: REO/SW/FW 730 731 Producer: RXDMA 732 733 734 735 The number of MSDUs within the MPDU 736 737 <legal all> 738 */ 739 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 740 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 741 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 742 743 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 744 745 Consumer: REO/SW/FW 746 747 Producer: RXDMA 748 749 750 751 The field can have two different meanings based on the 752 setting of field 'BAR_frame': 753 754 755 756 'BAR_frame' is NOT set: 757 758 The MPDU sequence number of the received frame. 759 760 761 762 'BAR_frame' is set. 763 764 The MPDU Start sequence number from the BAR frame 765 766 <legal all> 767 */ 768 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 769 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 770 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 771 772 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 773 774 Consumer: REO/SW/FW 775 776 Producer: RXDMA 777 778 779 780 When set, this MPDU is a fragment and REO should forward 781 this fragment MPDU to the REO destination ring without any 782 reorder checks, pn checks or bitmap update. This implies 783 that REO is forwarding the pointer to the MSDU link 784 descriptor. The destination ring is coming from a 785 programmable register setting in REO 786 787 788 789 <legal all> 790 */ 791 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 792 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 793 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 794 795 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 796 797 Consumer: REO/SW/FW 798 799 Producer: RXDMA 800 801 802 803 The retry bit setting from the MPDU header of the 804 received frame 805 806 <legal all> 807 */ 808 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 809 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 810 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 811 812 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 813 814 Consumer: REO/SW/FW 815 816 Producer: RXDMA 817 818 819 820 When set, the MPDU was received as part of an A-MPDU. 821 822 <legal all> 823 */ 824 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 825 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 826 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 827 828 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 829 830 Consumer: REO/SW/FW 831 832 Producer: RXDMA 833 834 835 836 When set, the received frame is a BAR frame. After 837 processing, this frame shall be pushed to SW or deleted. 838 839 <legal all> 840 */ 841 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 842 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 843 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 844 845 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 846 847 Consumer: REO/SW/FW 848 849 Producer: RXDMA 850 851 852 853 Copied here by RXDMA from RX_MPDU_END 854 855 When not set, REO will Not perform a PN sequence number 856 check 857 */ 858 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 859 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 860 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 861 862 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 863 864 When set, OLE found a valid SA entry for all MSDUs in 865 this MPDU 866 867 <legal all> 868 */ 869 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 870 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 871 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 872 873 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 874 875 When set, at least 1 MSDU within the MPDU has an 876 unsuccessful MAC source address search due to the expiration 877 of the search timer. 878 879 <legal all> 880 */ 881 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 882 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 883 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 884 885 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 886 887 When set, OLE found a valid DA entry for all MSDUs in 888 this MPDU 889 890 <legal all> 891 */ 892 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 893 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 894 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 895 896 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 897 898 Field Only valid if da_is_valid is set 899 900 901 902 When set, at least one of the DA addresses is a 903 Multicast or Broadcast address. 904 905 <legal all> 906 */ 907 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 908 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 909 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 910 911 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 912 913 When set, at least 1 MSDU within the MPDU has an 914 unsuccessful MAC destination address search due to the 915 expiration of the search timer. 916 917 <legal all> 918 */ 919 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 920 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 921 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 922 923 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 924 925 Field only valid when first_msdu_in_mpdu_flag is set. 926 927 928 929 When set, the contents in the MSDU buffer contains a 930 'RAW' MPDU. This 'RAW' MPDU might be spread out over 931 multiple MSDU buffers. 932 933 <legal all> 934 */ 935 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 936 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 937 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 938 939 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 940 941 The More Fragment bit setting from the MPDU header of 942 the received frame 943 944 945 946 <legal all> 947 */ 948 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 949 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 950 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 951 952 /* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 953 954 Meta data that SW has programmed in the Peer table entry 955 of the transmitting STA. 956 957 <legal all> 958 */ 959 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 960 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 961 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 962 963 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 964 965 Consumer: REO 966 967 Producer: RXDMA 968 969 970 971 Address (lower 32 bits) of the REO queue descriptor. 972 973 <legal all> 974 */ 975 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 976 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 977 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 978 979 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 980 981 Consumer: REO 982 983 Producer: RXDMA 984 985 986 987 Address (upper 8 bits) of the REO queue descriptor. 988 989 <legal all> 990 */ 991 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 992 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 993 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 994 995 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 996 997 An approximation of the number of bytes received in this 998 MPDU. 999 1000 Used to keeps stats on the amount of data flowing 1001 through a queue. 1002 1003 <legal all> 1004 */ 1005 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 1006 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 1007 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 1008 1009 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 1010 1011 RXDMA copy the MPDU's first MSDU's destination 1012 indication field here. This is used for REO to be able to 1013 re-route the packet to a different SW destination ring if 1014 the packet is detected as error in REO. 1015 1016 1017 1018 The ID of the REO exit ring where the MSDU frame shall 1019 push after (MPDU level) reordering has finished. 1020 1021 1022 1023 <enum 0 reo_destination_tcl> Reo will push the frame 1024 into the REO2TCL ring 1025 1026 <enum 1 reo_destination_sw1> Reo will push the frame 1027 into the REO2SW1 ring 1028 1029 <enum 2 reo_destination_sw2> Reo will push the frame 1030 into the REO2SW2 ring 1031 1032 <enum 3 reo_destination_sw3> Reo will push the frame 1033 into the REO2SW3 ring 1034 1035 <enum 4 reo_destination_sw4> Reo will push the frame 1036 into the REO2SW4 ring 1037 1038 <enum 5 reo_destination_release> Reo will push the frame 1039 into the REO_release ring 1040 1041 <enum 6 reo_destination_fw> Reo will push the frame into 1042 the REO2FW ring 1043 1044 <enum 7 reo_destination_sw5> Reo will push the frame 1045 into the REO2SW5 ring (REO remaps this in chips without 1046 REO2SW5 ring, e.g. Pine) 1047 1048 <enum 8 reo_destination_sw6> Reo will push the frame 1049 into the REO2SW6 ring (REO remaps this in chips without 1050 REO2SW6 ring, e.g. Pine) 1051 1052 <enum 9 reo_destination_9> REO remaps this <enum 10 1053 reo_destination_10> REO remaps this 1054 1055 <enum 11 reo_destination_11> REO remaps this 1056 1057 <enum 12 reo_destination_12> REO remaps this <enum 13 1058 reo_destination_13> REO remaps this 1059 1060 <enum 14 reo_destination_14> REO remaps this 1061 1062 <enum 15 reo_destination_15> REO remaps this 1063 1064 <enum 16 reo_destination_16> REO remaps this 1065 1066 <enum 17 reo_destination_17> REO remaps this 1067 1068 <enum 18 reo_destination_18> REO remaps this 1069 1070 <enum 19 reo_destination_19> REO remaps this 1071 1072 <enum 20 reo_destination_20> REO remaps this 1073 1074 <enum 21 reo_destination_21> REO remaps this 1075 1076 <enum 22 reo_destination_22> REO remaps this 1077 1078 <enum 23 reo_destination_23> REO remaps this 1079 1080 <enum 24 reo_destination_24> REO remaps this 1081 1082 <enum 25 reo_destination_25> REO remaps this 1083 1084 <enum 26 reo_destination_26> REO remaps this 1085 1086 <enum 27 reo_destination_27> REO remaps this 1087 1088 <enum 28 reo_destination_28> REO remaps this 1089 1090 <enum 29 reo_destination_29> REO remaps this 1091 1092 <enum 30 reo_destination_30> REO remaps this 1093 1094 <enum 31 reo_destination_31> REO remaps this 1095 1096 1097 1098 <legal all> 1099 */ 1100 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 1101 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 1102 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 1103 1104 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 1105 1106 When set, this REO entrance ring struct contains BAR 1107 info from a multi TID BAR frame. The original multi TID BAR 1108 frame itself contained all the REO info for the first TID, 1109 but all the subsequent TID info and their linkage to the REO 1110 descriptors is passed down as 'frameless' BAR info. 1111 1112 1113 1114 The only fields valid in this descriptor when this bit 1115 is set are: 1116 1117 Rx_reo_queue_desc_addr_31_0 1118 1119 RX_reo_queue_desc_addr_39_32 1120 1121 1122 1123 And within the 1124 1125 Reo_level_mpdu_frame_info: 1126 1127 Within Rx_mpdu_desc_info_details: 1128 1129 Mpdu_Sequence_number 1130 1131 BAR_frame 1132 1133 Peer_meta_data 1134 1135 All other fields shall be set to 0 1136 1137 1138 1139 <legal all> 1140 */ 1141 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 1142 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 1143 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 1144 1145 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 1146 1147 <legal 0> 1148 */ 1149 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 1150 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 1151 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 1152 1153 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 1154 1155 Indicates why rxdma pushed the frame to this ring 1156 1157 1158 1159 This field is ignored by REO. 1160 1161 1162 1163 <enum 0 rxdma_error_detected> RXDMA detected an error an 1164 pushed this frame to this queue 1165 1166 <enum 1 rxdma_routing_instruction> RXDMA pushed the 1167 frame to this queue per received routing instructions. No 1168 error within RXDMA was detected 1169 1170 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 1171 result the MSDU link descriptor might not have the 1172 last_msdu_in_mpdu_flag set, but instead WBM might just see a 1173 NULL pointer in the MSDU link descriptor. This is to be 1174 considered a normal condition for this scenario. 1175 1176 1177 1178 <legal 0 - 2> 1179 */ 1180 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 1181 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 1182 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 1183 1184 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 1185 1186 Field only valid when 'rxdma_push_reason' set to 1187 'rxdma_error_detected'. 1188 1189 1190 1191 This field is ignored by REO. 1192 1193 1194 1195 <enum 0 rxdma_overflow_err>MPDU frame is not complete 1196 due to a FIFO overflow error in RXPCU. 1197 1198 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 1199 due to receiving incomplete MPDU from the PHY 1200 1201 1202 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 1203 error or CRYPTO received an encrypted frame, but did not get 1204 a valid corresponding key id in the peer entry. 1205 1206 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 1207 error 1208 1209 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 1210 unencrypted frame error when encrypted was expected 1211 1212 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 1213 length error 1214 1215 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 1216 number of MSDUs allowed in an MPDU got exceeded 1217 1218 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 1219 error 1220 1221 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 1222 parsing error 1223 1224 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 1225 during SA search 1226 1227 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 1228 during DA search 1229 1230 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 1231 timeout during flow search 1232 1233 <enum 13 rxdma_flush_request>RXDMA received a flush 1234 request 1235 1236 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 1237 present as well as a fragmented MPDU. A-MSDU defragmentation 1238 is not supported in Lithium SW so this is treated as an 1239 error. 1240 */ 1241 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 1242 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 1243 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 1244 1245 /* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER 1246 1247 Field only valid when Reo_level_mpdu_frame_info. 1248 Rx_mpdu_desc_info_details.Fragment_flag is set. 1249 1250 1251 1252 The fragment number from the 802.11 header. 1253 1254 1255 1256 Note that the sequence number is embedded in the field: 1257 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 1258 Mpdu_sequence_number 1259 1260 1261 1262 <legal all> 1263 */ 1264 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 1265 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 1266 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 1267 1268 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION 1269 1270 When not set, REO is performing all its default MPDU 1271 processing operations, 1272 1273 When set, this REO entrance descriptor is generated by 1274 FW, and should be processed as an exception. This implies: 1275 1276 NO re-order function is needed. 1277 1278 MPDU delinking is determined by the setting of field 1279 SW_excection_mpdu_delink 1280 1281 Destination ring selection is based on the setting of 1282 the field SW_exception_destination_ring_valid 1283 1284 In the destination ring descriptor set bit: 1285 SW_exception_entry 1286 1287 Feature supported only in HastingsPrime 1288 1289 <legal all> 1290 */ 1291 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 1292 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 1293 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 1294 1295 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK 1296 1297 Field only valid when SW_exception is set. 1298 1299 1'b0: REO should NOT delink the MPDU, and thus pass this 1300 MPDU on to the destination ring as is. This implies that in 1301 the REO_DESTINATION_RING struct field 1302 Buf_or_link_desc_addr_info should point to an MSDU link 1303 descriptor 1304 1305 1'b1: REO should perform the normal MPDU delink into 1306 MSDU operations. 1307 1308 Feature supported only in HastingsPrime 1309 1310 <legal all> 1311 */ 1312 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 1313 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 1314 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 1315 1316 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID 1317 1318 Field only valid when SW_exception is set. 1319 1320 1'b0: REO shall push the MPDU (or delinked MPDU based on 1321 the setting of SW_exception_mpdu_delink) to the destination 1322 ring according to field reo_destination_indication. 1323 1324 1'b1: REO shall push the MPDU (or delinked MPDU based on 1325 the setting of SW_exception_mpdu_delink) to the destination 1326 ring according to field SW_exception_destination_ring. 1327 1328 Feature supported only in HastingsPrime 1329 1330 <legal all> 1331 */ 1332 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 1333 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 1334 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 1335 1336 /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING 1337 1338 Field only valid when fields SW_exception and 1339 SW_exception_destination_ring_valid are set. 1340 1341 The ID of the ring where REO shall push this frame. 1342 1343 <enum 0 reo_destination_tcl> Reo will push the frame 1344 into the REO2TCL ring 1345 1346 <enum 1 reo_destination_sw1> Reo will push the frame 1347 into the REO2SW1 ring 1348 1349 <enum 2 reo_destination_sw2> Reo will push the frame 1350 into the REO2SW1 ring 1351 1352 <enum 3 reo_destination_sw3> Reo will push the frame 1353 into the REO2SW1 ring 1354 1355 <enum 4 reo_destination_sw4> Reo will push the frame 1356 into the REO2SW1 ring 1357 1358 <enum 5 reo_destination_release> Reo will push the frame 1359 into the REO_release ring 1360 1361 <enum 6 reo_destination_fw> Reo will push the frame into 1362 the REO2FW ring 1363 1364 <enum 7 reo_destination_sw5> REO remaps this 1365 1366 <enum 8 reo_destination_sw6> REO remaps this 1367 1368 <enum 9 reo_destination_9> REO remaps this 1369 1370 <enum 10 reo_destination_10> REO remaps this 1371 1372 <enum 11 reo_destination_11> REO remaps this 1373 1374 <enum 12 reo_destination_12> REO remaps this <enum 13 1375 reo_destination_13> REO remaps this 1376 1377 <enum 14 reo_destination_14> REO remaps this 1378 1379 <enum 15 reo_destination_15> REO remaps this 1380 1381 <enum 16 reo_destination_16> REO remaps this 1382 1383 <enum 17 reo_destination_17> REO remaps this 1384 1385 <enum 18 reo_destination_18> REO remaps this 1386 1387 <enum 19 reo_destination_19> REO remaps this 1388 1389 <enum 20 reo_destination_20> REO remaps this 1390 1391 <enum 21 reo_destination_21> REO remaps this 1392 1393 <enum 22 reo_destination_22> REO remaps this 1394 1395 <enum 23 reo_destination_23> REO remaps this 1396 1397 <enum 24 reo_destination_24> REO remaps this 1398 1399 <enum 25 reo_destination_25> REO remaps this 1400 1401 <enum 26 reo_destination_26> REO remaps this 1402 1403 <enum 27 reo_destination_27> REO remaps this 1404 1405 <enum 28 reo_destination_28> REO remaps this 1406 1407 <enum 29 reo_destination_29> REO remaps this 1408 1409 <enum 30 reo_destination_30> REO remaps this 1410 1411 <enum 31 reo_destination_31> REO remaps this 1412 1413 1414 1415 Feature supported only in HastingsPrime 1416 1417 <legal all> 1418 */ 1419 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 1420 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 1421 #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 1422 1423 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 1424 1425 <legal 0> 1426 */ 1427 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 1428 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 1429 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 1430 1431 /* Description REO_ENTRANCE_RING_7_PHY_PPDU_ID 1432 1433 A PPDU counter value that PHY increments for every PPDU 1434 received 1435 1436 The counter value wraps around. Pine RXDMA can be 1437 configured to copy this from the RX_PPDU_START TLV for every 1438 output descriptor. 1439 1440 1441 1442 This field is ignored by REO. 1443 1444 1445 1446 Feature supported only in Pine 1447 1448 <legal all> 1449 */ 1450 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c 1451 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 1452 #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff 1453 1454 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 1455 1456 <legal 0> 1457 */ 1458 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 1459 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 1460 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 1461 1462 /* Description REO_ENTRANCE_RING_7_RING_ID 1463 1464 Consumer: SW/REO/DEBUG 1465 1466 Producer: SRNG (of RXDMA) 1467 1468 1469 1470 For debugging. 1471 1472 This field is filled in by the SRNG module. 1473 1474 It help to identify the ring that is being looked <legal 1475 all> 1476 */ 1477 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 1478 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 1479 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 1480 1481 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 1482 1483 Consumer: SW/REO/DEBUG 1484 1485 Producer: SRNG (of RXDMA) 1486 1487 1488 1489 For debugging. 1490 1491 This field is filled in by the SRNG module. 1492 1493 1494 1495 A count value that indicates the number of times the 1496 producer of entries into this Ring has looped around the 1497 ring. 1498 1499 At initialization time, this value is set to 0. On the 1500 first loop, this value is set to 1. After the max value is 1501 reached allowed by the number of bits for this field, the 1502 count value continues with 0 again. 1503 1504 1505 1506 In case SW is the consumer of the ring entries, it can 1507 use this field to figure out up to where the producer of 1508 entries has created new entries. This eliminates the need to 1509 check where the head pointer' of the ring is located once 1510 the SW starts processing an interrupt indicating that new 1511 entries have been put into this ring... 1512 1513 1514 1515 Also note that SW if it wants only needs to look at the 1516 LSB bit of this count value. 1517 1518 <legal all> 1519 */ 1520 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1521 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 1522 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 1523 1524 1525 #endif // _REO_ENTRANCE_RING_H_ 1526