1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_DETAILS_H_ 18 #define _RX_MPDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_mpdu_desc_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-1 struct buffer_addr_info msdu_link_desc_addr_info; 29 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 30 // 31 // ################ END SUMMARY ################# 32 33 #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 34 35 struct rx_mpdu_details { 36 struct buffer_addr_info msdu_link_desc_addr_info; 37 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 38 }; 39 40 /* 41 42 struct buffer_addr_info msdu_link_desc_addr_info 43 44 Consumer: REO/SW/FW 45 46 Producer: RXDMA 47 48 49 50 Details of the physical address of the MSDU link 51 descriptor that contains pointers to MSDUs related to this 52 MPDU 53 54 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 55 56 Consumer: REO/SW/FW 57 58 Producer: RXDMA 59 60 61 62 General information related to the MPDU that should be 63 */ 64 65 66 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 67 68 69 /* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 70 71 Address (lower 32 bits) of the MSDU buffer OR 72 MSDU_EXTENSION descriptor OR Link Descriptor 73 74 75 76 In case of 'NULL' pointer, this field is set to 0 77 78 <legal all> 79 */ 80 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 81 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 82 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 83 84 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 85 86 Address (upper 8 bits) of the MSDU buffer OR 87 MSDU_EXTENSION descriptor OR Link Descriptor 88 89 90 91 In case of 'NULL' pointer, this field is set to 0 92 93 <legal all> 94 */ 95 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 96 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 97 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 98 99 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 100 101 Consumer: WBM 102 103 Producer: SW/FW 104 105 106 107 In case of 'NULL' pointer, this field is set to 0 108 109 110 111 Indicates to which buffer manager the buffer OR 112 MSDU_EXTENSION descriptor OR link descriptor that is being 113 pointed to shall be returned after the frame has been 114 processed. It is used by WBM for routing purposes. 115 116 117 118 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 119 to the WMB buffer idle list 120 121 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 122 returned to the WMB idle link descriptor idle list 123 124 <enum 2 FW_BM> This buffer shall be returned to the FW 125 126 <enum 3 SW0_BM> This buffer shall be returned to the SW, 127 ring 0 128 129 <enum 4 SW1_BM> This buffer shall be returned to the SW, 130 ring 1 131 132 <enum 5 SW2_BM> This buffer shall be returned to the SW, 133 ring 2 134 135 <enum 6 SW3_BM> This buffer shall be returned to the SW, 136 ring 3 137 138 <enum 7 SW4_BM> This buffer shall be returned to the SW, 139 ring 4 140 141 142 143 <legal all> 144 */ 145 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 146 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 147 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 148 149 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 150 151 Cookie field exclusively used by SW. 152 153 154 155 In case of 'NULL' pointer, this field is set to 0 156 157 158 159 HW ignores the contents, accept that it passes the 160 programmed value on to other descriptors together with the 161 physical address 162 163 164 165 Field can be used by SW to for example associate the 166 buffers physical address with the virtual address 167 168 The bit definitions as used by SW are within SW HLD 169 specification 170 171 172 173 NOTE: 174 175 The three most significant bits can have a special 176 meaning in case this struct is embedded in a TX_MPDU_DETAILS 177 STRUCT, and field transmit_bw_restriction is set 178 179 180 181 In case of NON punctured transmission: 182 183 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 184 185 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 186 187 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 188 189 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 190 191 192 193 In case of punctured transmission: 194 195 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 196 197 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 198 199 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 200 201 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 202 203 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 204 205 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 206 207 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 208 209 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 210 211 212 213 Note: a punctured transmission is indicated by the 214 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 215 TLV 216 217 218 219 <legal all> 220 */ 221 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 222 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 223 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 224 225 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 226 227 228 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 229 230 Consumer: REO/SW/FW 231 232 Producer: RXDMA 233 234 235 236 The number of MSDUs within the MPDU 237 238 <legal all> 239 */ 240 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 241 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 242 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 243 244 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 245 246 Consumer: REO/SW/FW 247 248 Producer: RXDMA 249 250 251 252 The field can have two different meanings based on the 253 setting of field 'BAR_frame': 254 255 256 257 'BAR_frame' is NOT set: 258 259 The MPDU sequence number of the received frame. 260 261 262 263 'BAR_frame' is set. 264 265 The MPDU Start sequence number from the BAR frame 266 267 <legal all> 268 */ 269 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 270 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 271 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 272 273 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 274 275 Consumer: REO/SW/FW 276 277 Producer: RXDMA 278 279 280 281 When set, this MPDU is a fragment and REO should forward 282 this fragment MPDU to the REO destination ring without any 283 reorder checks, pn checks or bitmap update. This implies 284 that REO is forwarding the pointer to the MSDU link 285 descriptor. The destination ring is coming from a 286 programmable register setting in REO 287 288 289 290 <legal all> 291 */ 292 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 293 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 294 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 295 296 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 297 298 Consumer: REO/SW/FW 299 300 Producer: RXDMA 301 302 303 304 The retry bit setting from the MPDU header of the 305 received frame 306 307 <legal all> 308 */ 309 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 310 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 311 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 312 313 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 314 315 Consumer: REO/SW/FW 316 317 Producer: RXDMA 318 319 320 321 When set, the MPDU was received as part of an A-MPDU. 322 323 <legal all> 324 */ 325 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 326 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 327 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 328 329 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 330 331 Consumer: REO/SW/FW 332 333 Producer: RXDMA 334 335 336 337 When set, the received frame is a BAR frame. After 338 processing, this frame shall be pushed to SW or deleted. 339 340 <legal all> 341 */ 342 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 343 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 344 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 345 346 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 347 348 Consumer: REO/SW/FW 349 350 Producer: RXDMA 351 352 353 354 Copied here by RXDMA from RX_MPDU_END 355 356 When not set, REO will Not perform a PN sequence number 357 check 358 */ 359 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 360 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 361 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 362 363 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 364 365 When set, OLE found a valid SA entry for all MSDUs in 366 this MPDU 367 368 <legal all> 369 */ 370 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 371 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 372 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 373 374 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 375 376 When set, at least 1 MSDU within the MPDU has an 377 unsuccessful MAC source address search due to the expiration 378 of the search timer. 379 380 <legal all> 381 */ 382 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 383 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 384 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 385 386 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 387 388 When set, OLE found a valid DA entry for all MSDUs in 389 this MPDU 390 391 <legal all> 392 */ 393 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 394 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 395 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 396 397 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 398 399 Field Only valid if da_is_valid is set 400 401 402 403 When set, at least one of the DA addresses is a 404 Multicast or Broadcast address. 405 406 <legal all> 407 */ 408 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 409 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 410 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 411 412 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 413 414 When set, at least 1 MSDU within the MPDU has an 415 unsuccessful MAC destination address search due to the 416 expiration of the search timer. 417 418 <legal all> 419 */ 420 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 421 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 422 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 423 424 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 425 426 Field only valid when first_msdu_in_mpdu_flag is set. 427 428 429 430 When set, the contents in the MSDU buffer contains a 431 'RAW' MPDU. This 'RAW' MPDU might be spread out over 432 multiple MSDU buffers. 433 434 <legal all> 435 */ 436 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 437 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 438 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 439 440 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 441 442 The More Fragment bit setting from the MPDU header of 443 the received frame 444 445 446 447 <legal all> 448 */ 449 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 450 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 451 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 452 453 /* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 454 455 Meta data that SW has programmed in the Peer table entry 456 of the transmitting STA. 457 458 <legal all> 459 */ 460 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 461 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 462 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 463 464 465 #endif // _RX_MPDU_DETAILS_H_ 466