1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_DETAILS_H_ 18 #define _RX_MSDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_msdu_desc_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-1 struct buffer_addr_info buffer_addr_info_details; 29 // 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; 30 // 31 // ################ END SUMMARY ################# 32 33 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 34 35 struct rx_msdu_details { 36 struct buffer_addr_info buffer_addr_info_details; 37 struct rx_msdu_desc_info rx_msdu_desc_info_details; 38 }; 39 40 /* 41 42 struct buffer_addr_info buffer_addr_info_details 43 44 Consumer: REO/SW 45 46 Producer: RXDMA 47 48 49 50 Details of the physical address of the buffer containing 51 an MSDU (or entire MPDU) 52 53 struct rx_msdu_desc_info rx_msdu_desc_info_details 54 55 Consumer: REO/SW 56 57 Producer: RXDMA 58 59 60 61 General information related to the MSDU that should be 62 passed on from RXDMA all the way to to the REO destination 63 ring. 64 */ 65 66 67 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 68 69 70 /* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 71 72 Address (lower 32 bits) of the MSDU buffer OR 73 MSDU_EXTENSION descriptor OR Link Descriptor 74 75 76 77 In case of 'NULL' pointer, this field is set to 0 78 79 <legal all> 80 */ 81 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 82 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 83 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 84 85 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 86 87 Address (upper 8 bits) of the MSDU buffer OR 88 MSDU_EXTENSION descriptor OR Link Descriptor 89 90 91 92 In case of 'NULL' pointer, this field is set to 0 93 94 <legal all> 95 */ 96 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 97 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 98 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 99 100 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 101 102 Consumer: WBM 103 104 Producer: SW/FW 105 106 107 108 In case of 'NULL' pointer, this field is set to 0 109 110 111 112 Indicates to which buffer manager the buffer OR 113 MSDU_EXTENSION descriptor OR link descriptor that is being 114 pointed to shall be returned after the frame has been 115 processed. It is used by WBM for routing purposes. 116 117 118 119 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 120 to the WMB buffer idle list 121 122 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 123 returned to the WMB idle link descriptor idle list 124 125 <enum 2 FW_BM> This buffer shall be returned to the FW 126 127 <enum 3 SW0_BM> This buffer shall be returned to the SW, 128 ring 0 129 130 <enum 4 SW1_BM> This buffer shall be returned to the SW, 131 ring 1 132 133 <enum 5 SW2_BM> This buffer shall be returned to the SW, 134 ring 2 135 136 <enum 6 SW3_BM> This buffer shall be returned to the SW, 137 ring 3 138 139 <enum 7 SW4_BM> This buffer shall be returned to the SW, 140 ring 4 141 142 143 144 <legal all> 145 */ 146 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 147 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 148 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 149 150 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 151 152 Cookie field exclusively used by SW. 153 154 155 156 In case of 'NULL' pointer, this field is set to 0 157 158 159 160 HW ignores the contents, accept that it passes the 161 programmed value on to other descriptors together with the 162 physical address 163 164 165 166 Field can be used by SW to for example associate the 167 buffers physical address with the virtual address 168 169 The bit definitions as used by SW are within SW HLD 170 specification 171 172 173 174 NOTE: 175 176 The three most significant bits can have a special 177 meaning in case this struct is embedded in a TX_MPDU_DETAILS 178 STRUCT, and field transmit_bw_restriction is set 179 180 181 182 In case of NON punctured transmission: 183 184 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 185 186 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 187 188 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 189 190 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 191 192 193 194 In case of punctured transmission: 195 196 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 197 198 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 199 200 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 201 202 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 203 204 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 205 206 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 207 208 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 209 210 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 211 212 213 214 Note: a punctured transmission is indicated by the 215 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 216 TLV 217 218 219 220 <legal all> 221 */ 222 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 223 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 224 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 225 226 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 227 228 229 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 230 231 Parsed from RX_MSDU_END TLV . In the case MSDU spans 232 over multiple buffers, this field will be valid in the Last 233 buffer used by the MSDU 234 235 236 237 <enum 0 Not_first_msdu> This is not the first MSDU in 238 the MPDU. 239 240 <enum 1 first_msdu> This MSDU is the first one in the 241 MPDU. 242 243 244 245 <legal all> 246 */ 247 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 248 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 249 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 250 251 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 252 253 Consumer: WBM/REO/SW/FW 254 255 Producer: RXDMA 256 257 258 259 Parsed from RX_MSDU_END TLV . In the case MSDU spans 260 over multiple buffers, this field will be valid in the Last 261 buffer used by the MSDU 262 263 264 265 <enum 0 Not_last_msdu> There are more MSDUs linked to 266 this MSDU that belongs to this MPDU 267 268 <enum 1 Last_msdu> this MSDU is the last one in the 269 MPDU. This setting is only allowed in combination with 270 'Msdu_continuation' set to 0. This implies that when an msdu 271 is spread out over multiple buffers and thus 272 msdu_continuation is set, only for the very last buffer of 273 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 274 275 276 277 When both first_msdu_in_mpdu_flag and 278 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 279 belongs to only contains a single MSDU. 280 281 282 283 284 285 <legal all> 286 */ 287 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 288 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 289 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 290 291 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 292 293 When set, this MSDU buffer was not able to hold the 294 entire MSDU. The next buffer will therefor contain 295 additional information related to this MSDU. 296 297 298 299 <legal all> 300 */ 301 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 302 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 303 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 304 305 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 306 307 Parsed from RX_MSDU_START TLV . In the case MSDU spans 308 over multiple buffers, this field will be valid in the First 309 buffer used by MSDU. 310 311 312 313 Full MSDU length in bytes after decapsulation. 314 315 316 317 This field is still valid for MPDU frames without 318 A-MSDU. It still represents MSDU length after decapsulation 319 320 321 322 Or in case of RAW MPDUs, it indicates the length of the 323 entire MPDU (without FCS field) 324 325 <legal all> 326 */ 327 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 328 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 329 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 330 331 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 332 333 Parsed from RX_MSDU_END TLV . In the case MSDU spans 334 over multiple buffers, this field will be valid in the Last 335 buffer used by the MSDU 336 337 338 339 The ID of the REO exit ring where the MSDU frame shall 340 push after (MPDU level) reordering has finished. 341 342 343 344 <enum 0 reo_destination_tcl> Reo will push the frame 345 into the REO2TCL ring 346 347 <enum 1 reo_destination_sw1> Reo will push the frame 348 into the REO2SW1 ring 349 350 <enum 2 reo_destination_sw2> Reo will push the frame 351 into the REO2SW2 ring 352 353 <enum 3 reo_destination_sw3> Reo will push the frame 354 into the REO2SW3 ring 355 356 <enum 4 reo_destination_sw4> Reo will push the frame 357 into the REO2SW4 ring 358 359 <enum 5 reo_destination_release> Reo will push the frame 360 into the REO_release ring 361 362 <enum 6 reo_destination_fw> Reo will push the frame into 363 the REO2FW ring 364 365 <enum 7 reo_destination_sw5> Reo will push the frame 366 into the REO2SW5 ring (REO remaps this in chips without 367 REO2SW5 ring, e.g. Pine) 368 369 <enum 8 reo_destination_sw6> Reo will push the frame 370 into the REO2SW6 ring (REO remaps this in chips without 371 REO2SW6 ring, e.g. Pine) 372 373 <enum 9 reo_destination_9> REO remaps this <enum 10 374 reo_destination_10> REO remaps this 375 376 <enum 11 reo_destination_11> REO remaps this 377 378 <enum 12 reo_destination_12> REO remaps this <enum 13 379 reo_destination_13> REO remaps this 380 381 <enum 14 reo_destination_14> REO remaps this 382 383 <enum 15 reo_destination_15> REO remaps this 384 385 <enum 16 reo_destination_16> REO remaps this 386 387 <enum 17 reo_destination_17> REO remaps this 388 389 <enum 18 reo_destination_18> REO remaps this 390 391 <enum 19 reo_destination_19> REO remaps this 392 393 <enum 20 reo_destination_20> REO remaps this 394 395 <enum 21 reo_destination_21> REO remaps this 396 397 <enum 22 reo_destination_22> REO remaps this 398 399 <enum 23 reo_destination_23> REO remaps this 400 401 <enum 24 reo_destination_24> REO remaps this 402 403 <enum 25 reo_destination_25> REO remaps this 404 405 <enum 26 reo_destination_26> REO remaps this 406 407 <enum 27 reo_destination_27> REO remaps this 408 409 <enum 28 reo_destination_28> REO remaps this 410 411 <enum 29 reo_destination_29> REO remaps this 412 413 <enum 30 reo_destination_30> REO remaps this 414 415 <enum 31 reo_destination_31> REO remaps this 416 417 418 419 <legal all> 420 */ 421 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 422 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 423 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 424 425 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 426 427 Parsed from RX_MSDU_END TLV . In the case MSDU spans 428 over multiple buffers, this field will be valid in the Last 429 buffer used by the MSDU 430 431 432 433 When set, REO shall drop this MSDU and not forward it to 434 any other ring... 435 436 <legal all> 437 */ 438 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 439 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 440 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 441 442 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 443 444 Parsed from RX_MSDU_END TLV . In the case MSDU spans 445 over multiple buffers, this field will be valid in the Last 446 buffer used by the MSDU 447 448 449 450 Indicates that OLE found a valid SA entry for this MSDU 451 452 <legal all> 453 */ 454 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 455 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 456 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 457 458 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 459 460 Parsed from RX_MSDU_END TLV . In the case MSDU spans 461 over multiple buffers, this field will be valid in the Last 462 buffer used by the MSDU 463 464 465 466 Indicates an unsuccessful MAC source address search due 467 to the expiring of the search timer for this MSDU 468 469 <legal all> 470 */ 471 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 472 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 473 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 474 475 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 476 477 Parsed from RX_MSDU_END TLV . In the case MSDU spans 478 over multiple buffers, this field will be valid in the Last 479 buffer used by the MSDU 480 481 482 483 Indicates that OLE found a valid DA entry for this MSDU 484 485 <legal all> 486 */ 487 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 488 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 489 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 490 491 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 492 493 Field Only valid if da_is_valid is set 494 495 496 497 Indicates the DA address was a Multicast of Broadcast 498 address for this MSDU 499 500 <legal all> 501 */ 502 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 503 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 504 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 505 506 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 507 508 Parsed from RX_MSDU_END TLV . In the case MSDU spans 509 over multiple buffers, this field will be valid in the Last 510 buffer used by the MSDU 511 512 513 514 Indicates an unsuccessful MAC destination address search 515 due to the expiring of the search timer for this MSDU 516 517 <legal all> 518 */ 519 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 520 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 521 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 522 523 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 524 525 <legal 0> 526 */ 527 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 528 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 529 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 530 531 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 532 533 <legal 0> 534 */ 535 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000c 536 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 537 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 538 539 540 #endif // _RX_MSDU_DETAILS_H_ 541