1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_END_H_ 18 #define _RX_MSDU_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 27 // 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30] 28 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], reserved_2a[31:16] 29 // 3 rule_indication_31_0[31:0] 30 // 4 rule_indication_63_32[31:0] 31 // 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16] 32 // 6 ipv6_options_crc[31:0] 33 // 7 tcp_seq_number[31:0] 34 // 8 tcp_ack_number[31:0] 35 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 36 // 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], reserved_10a[31:30] 37 // 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] 38 // 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26] 39 // 13 fse_metadata[31:0] 40 // 14 cce_metadata[15:0], sa_sw_peer_id[31:16] 41 // 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10] 42 // 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_RX_MSDU_END 17 47 48 struct rx_msdu_end { 49 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 50 sw_frame_group_id : 7, //[8:2] 51 reserved_0 : 7, //[15:9] 52 phy_ppdu_id : 16; //[31:16] 53 uint32_t ip_hdr_chksum : 16, //[15:0] 54 reported_mpdu_length : 14, //[29:16] 55 reserved_1a : 2; //[31:30] 56 uint32_t key_id_octet : 8, //[7:0] 57 cce_super_rule : 6, //[13:8] 58 cce_classify_not_done_truncate : 1, //[14] 59 cce_classify_not_done_cce_dis : 1, //[15] 60 reserved_2a : 16; //[31:16] 61 uint32_t rule_indication_31_0 : 32; //[31:0] 62 uint32_t rule_indication_63_32 : 32; //[31:0] 63 uint32_t da_offset : 6, //[5:0] 64 sa_offset : 6, //[11:6] 65 da_offset_valid : 1, //[12] 66 sa_offset_valid : 1, //[13] 67 reserved_5a : 2, //[15:14] 68 l3_type : 16; //[31:16] 69 uint32_t ipv6_options_crc : 32; //[31:0] 70 uint32_t tcp_seq_number : 32; //[31:0] 71 uint32_t tcp_ack_number : 32; //[31:0] 72 uint32_t tcp_flag : 9, //[8:0] 73 lro_eligible : 1, //[9] 74 reserved_9a : 6, //[15:10] 75 window_size : 16; //[31:16] 76 uint32_t tcp_udp_chksum : 16, //[15:0] 77 sa_idx_timeout : 1, //[16] 78 da_idx_timeout : 1, //[17] 79 msdu_limit_error : 1, //[18] 80 flow_idx_timeout : 1, //[19] 81 flow_idx_invalid : 1, //[20] 82 wifi_parser_error : 1, //[21] 83 amsdu_parser_error : 1, //[22] 84 sa_is_valid : 1, //[23] 85 da_is_valid : 1, //[24] 86 da_is_mcbc : 1, //[25] 87 l3_header_padding : 2, //[27:26] 88 first_msdu : 1, //[28] 89 last_msdu : 1, //[29] 90 reserved_10a : 2; //[31:30] 91 uint32_t sa_idx : 16, //[15:0] 92 da_idx_or_sw_peer_id : 16; //[31:16] 93 uint32_t msdu_drop : 1, //[0] 94 reo_destination_indication : 5, //[5:1] 95 flow_idx : 20, //[25:6] 96 reserved_12a : 6; //[31:26] 97 uint32_t fse_metadata : 32; //[31:0] 98 uint32_t cce_metadata : 16, //[15:0] 99 sa_sw_peer_id : 16; //[31:16] 100 uint32_t aggregation_count : 8, //[7:0] 101 flow_aggregation_continuation : 1, //[8] 102 fisa_timeout : 1, //[9] 103 reserved_15a : 22; //[31:10] 104 uint32_t cumulative_l4_checksum : 16, //[15:0] 105 cumulative_ip_length : 16; //[31:16] 106 }; 107 108 /* 109 110 rxpcu_mpdu_filter_in_category 111 112 Field indicates what the reason was that this MPDU frame 113 was allowed to come into the receive path by RXPCU 114 115 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 116 frame filter programming of rxpcu 117 118 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 119 regular frame filter and would have been dropped, were it 120 not for the frame fitting into the 'monitor_client' 121 category. 122 123 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 124 regular frame filter and also did not pass the 125 rxpcu_monitor_client filter. It would have been dropped 126 accept that it did pass the 'monitor_other' category. 127 128 <legal 0-2> 129 130 sw_frame_group_id 131 132 SW processes frames based on certain classifications. 133 This field indicates to what sw classification this MPDU is 134 mapped. 135 136 The classification is given in priority order 137 138 139 140 <enum 0 sw_frame_group_NDP_frame> 141 142 143 144 <enum 1 sw_frame_group_Multicast_data> 145 146 <enum 2 sw_frame_group_Unicast_data> 147 148 <enum 3 sw_frame_group_Null_data > This includes mpdus 149 of type Data Null as well as QoS Data Null 150 151 152 153 <enum 4 sw_frame_group_mgmt_0000 > 154 155 <enum 5 sw_frame_group_mgmt_0001 > 156 157 <enum 6 sw_frame_group_mgmt_0010 > 158 159 <enum 7 sw_frame_group_mgmt_0011 > 160 161 <enum 8 sw_frame_group_mgmt_0100 > 162 163 <enum 9 sw_frame_group_mgmt_0101 > 164 165 <enum 10 sw_frame_group_mgmt_0110 > 166 167 <enum 11 sw_frame_group_mgmt_0111 > 168 169 <enum 12 sw_frame_group_mgmt_1000 > 170 171 <enum 13 sw_frame_group_mgmt_1001 > 172 173 <enum 14 sw_frame_group_mgmt_1010 > 174 175 <enum 15 sw_frame_group_mgmt_1011 > 176 177 <enum 16 sw_frame_group_mgmt_1100 > 178 179 <enum 17 sw_frame_group_mgmt_1101 > 180 181 <enum 18 sw_frame_group_mgmt_1110 > 182 183 <enum 19 sw_frame_group_mgmt_1111 > 184 185 186 187 <enum 20 sw_frame_group_ctrl_0000 > 188 189 <enum 21 sw_frame_group_ctrl_0001 > 190 191 <enum 22 sw_frame_group_ctrl_0010 > 192 193 <enum 23 sw_frame_group_ctrl_0011 > 194 195 <enum 24 sw_frame_group_ctrl_0100 > 196 197 <enum 25 sw_frame_group_ctrl_0101 > 198 199 <enum 26 sw_frame_group_ctrl_0110 > 200 201 <enum 27 sw_frame_group_ctrl_0111 > 202 203 <enum 28 sw_frame_group_ctrl_1000 > 204 205 <enum 29 sw_frame_group_ctrl_1001 > 206 207 <enum 30 sw_frame_group_ctrl_1010 > 208 209 <enum 31 sw_frame_group_ctrl_1011 > 210 211 <enum 32 sw_frame_group_ctrl_1100 > 212 213 <enum 33 sw_frame_group_ctrl_1101 > 214 215 <enum 34 sw_frame_group_ctrl_1110 > 216 217 <enum 35 sw_frame_group_ctrl_1111 > 218 219 220 221 <enum 36 sw_frame_group_unsupported> This covers type 3 222 and protocol version != 0 223 224 225 226 227 228 229 <legal 0-37> 230 231 reserved_0 232 233 <legal 0> 234 235 phy_ppdu_id 236 237 A ppdu counter value that PHY increments for every PPDU 238 received. The counter value wraps around 239 240 <legal all> 241 242 ip_hdr_chksum 243 244 This can include the IP header checksum or the pseudo 245 header checksum used by TCP/UDP checksum. 246 247 (with the first byte in the MSB and the second byte in 248 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 249 w.r.t. the byte order in a packet) 250 251 reported_mpdu_length 252 253 MPDU length before decapsulation. Only valid when 254 first_msdu is set. This field is taken directly from the 255 length field of the A-MPDU delimiter or the preamble length 256 field for non-A-MPDU frames. 257 258 reserved_1a 259 260 <legal 0> 261 262 key_id_octet 263 264 The key ID octet from the IV. Only valid when 265 first_msdu is set. 266 267 cce_super_rule 268 269 Indicates the super filter rule 270 271 cce_classify_not_done_truncate 272 273 Classification failed due to truncated frame 274 275 cce_classify_not_done_cce_dis 276 277 Classification failed due to CCE global disable 278 279 reserved_2a 280 281 <legal 0> 282 283 rule_indication_31_0 284 285 Bitmap indicating which of rules 31-0 have matched 286 287 rule_indication_63_32 288 289 Bitmap indicating which of rules 63-32 have matched 290 291 da_offset 292 293 Offset into MSDU buffer for DA 294 295 sa_offset 296 297 Offset into MSDU buffer for SA 298 299 da_offset_valid 300 301 da_offset field is valid. This will be set to 0 in case 302 of a dynamic A-MSDU when DA is compressed 303 304 sa_offset_valid 305 306 sa_offset field is valid. This will be set to 0 in case 307 of a dynamic A-MSDU when SA is compressed 308 309 reserved_5a 310 311 <legal 0> 312 313 l3_type 314 315 The 16-bit type value indicating the type of L3 later 316 extracted from LLC/SNAP, set to zero if SNAP is not 317 available 318 319 ipv6_options_crc 320 321 32 bit CRC computed out of IP v6 extension headers 322 323 tcp_seq_number 324 325 TCP sequence number (as a number assembled from a TCP 326 packet in big-endian order, i.e. requiring a byte-swap for 327 little-endian FW/SW w.r.t. the byte order in a packet) 328 329 tcp_ack_number 330 331 TCP acknowledge number (as a number assembled from a TCP 332 packet in big-endian order, i.e. requiring a byte-swap for 333 little-endian FW/SW w.r.t. the byte order in a packet) 334 335 tcp_flag 336 337 TCP flags 338 339 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 340 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 341 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 342 the byte order in a packet) 343 344 lro_eligible 345 346 Computed out of TCP and IP fields to indicate that this 347 MSDU is eligible for LRO 348 349 reserved_9a 350 351 NOTE: DO not assign a field... Internally used in 352 RXOLE.. 353 354 <legal 0> 355 356 window_size 357 358 TCP receive window size (as a number assembled from a 359 TCP packet in big-endian order, i.e. requiring a byte-swap 360 for little-endian FW/SW w.r.t. the byte order in a packet) 361 362 tcp_udp_chksum 363 364 The value of the computed TCP/UDP checksum. A mode bit 365 selects whether this checksum is the full checksum or the 366 partial checksum which does not include the pseudo header. 367 (with the first byte in the MSB and the second byte in the 368 LSB, i.e. requiring a byte-swap for little-endian FW/SW 369 w.r.t. the byte order in a packet) 370 371 sa_idx_timeout 372 373 Indicates an unsuccessful MAC source address search due 374 to the expiring of the search timer. 375 376 da_idx_timeout 377 378 Indicates an unsuccessful MAC destination address search 379 due to the expiring of the search timer. 380 381 msdu_limit_error 382 383 Indicates that the MSDU threshold was exceeded and thus 384 all the rest of the MSDUs will not be scattered and will not 385 be decapsulated but will be DMA'ed in RAW format as a single 386 MSDU buffer 387 388 flow_idx_timeout 389 390 Indicates an unsuccessful flow search due to the 391 expiring of the search timer. 392 393 <legal all> 394 395 flow_idx_invalid 396 397 flow id is not valid 398 399 <legal all> 400 401 wifi_parser_error 402 403 Indicates that the WiFi frame has one of the following 404 errors 405 406 o has less than minimum allowed bytes as per standard 407 408 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 409 410 <legal all> 411 412 amsdu_parser_error 413 414 A-MSDU could not be properly de-agregated. 415 416 <legal all> 417 418 sa_is_valid 419 420 Indicates that OLE found a valid SA entry 421 422 da_is_valid 423 424 Indicates that OLE found a valid DA entry 425 426 da_is_mcbc 427 428 Field Only valid if da_is_valid is set 429 430 431 432 Indicates the DA address was a Multicast of Broadcast 433 address. 434 435 l3_header_padding 436 437 Number of bytes padded to make sure that the L3 header 438 will always start of a Dword boundary 439 440 first_msdu 441 442 Indicates the first MSDU of A-MSDU. If both first_msdu 443 and last_msdu are set in the MSDU then this is a 444 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 445 A-MSDU shall have both first_mpdu and last_mpdu bits set to 446 0. 447 448 last_msdu 449 450 Indicates the last MSDU of the A-MSDU. MPDU end status 451 is only valid when last_msdu is set. 452 453 reserved_10a 454 455 <legal 0> 456 457 sa_idx 458 459 The offset in the address table which matches the MAC 460 source address. 461 462 da_idx_or_sw_peer_id 463 464 Based on a register configuration in RXOLE, this field 465 will contain: 466 467 The offset in the address table which matches the MAC 468 destination address 469 470 OR: 471 472 sw_peer_id from the address search entry corresponding 473 to the destination address of the MSDU 474 475 msdu_drop 476 477 When set, REO shall drop this MSDU and not forward it to 478 any other ring... 479 480 <legal all> 481 482 reo_destination_indication 483 484 The ID of the REO exit ring where the MSDU frame shall 485 push after (MPDU level) reordering has finished. 486 487 488 489 <enum 0 reo_destination_tcl> Reo will push the frame 490 into the REO2TCL ring 491 492 <enum 1 reo_destination_sw1> Reo will push the frame 493 into the REO2SW1 ring 494 495 <enum 2 reo_destination_sw2> Reo will push the frame 496 into the REO2SW2 ring 497 498 <enum 3 reo_destination_sw3> Reo will push the frame 499 into the REO2SW3 ring 500 501 <enum 4 reo_destination_sw4> Reo will push the frame 502 into the REO2SW4 ring 503 504 <enum 5 reo_destination_release> Reo will push the frame 505 into the REO_release ring 506 507 <enum 6 reo_destination_fw> Reo will push the frame into 508 the REO2FW ring 509 510 <enum 7 reo_destination_sw5> Reo will push the frame 511 into the REO2SW5 ring (REO remaps this in chips without 512 REO2SW5 ring, e.g. Pine) 513 514 <enum 8 reo_destination_sw6> Reo will push the frame 515 into the REO2SW6 ring (REO remaps this in chips without 516 REO2SW6 ring, e.g. Pine) 517 518 <enum 9 reo_destination_9> REO remaps this <enum 10 519 reo_destination_10> REO remaps this 520 521 <enum 11 reo_destination_11> REO remaps this 522 523 <enum 12 reo_destination_12> REO remaps this <enum 13 524 reo_destination_13> REO remaps this 525 526 <enum 14 reo_destination_14> REO remaps this 527 528 <enum 15 reo_destination_15> REO remaps this 529 530 <enum 16 reo_destination_16> REO remaps this 531 532 <enum 17 reo_destination_17> REO remaps this 533 534 <enum 18 reo_destination_18> REO remaps this 535 536 <enum 19 reo_destination_19> REO remaps this 537 538 <enum 20 reo_destination_20> REO remaps this 539 540 <enum 21 reo_destination_21> REO remaps this 541 542 <enum 22 reo_destination_22> REO remaps this 543 544 <enum 23 reo_destination_23> REO remaps this 545 546 <enum 24 reo_destination_24> REO remaps this 547 548 <enum 25 reo_destination_25> REO remaps this 549 550 <enum 26 reo_destination_26> REO remaps this 551 552 <enum 27 reo_destination_27> REO remaps this 553 554 <enum 28 reo_destination_28> REO remaps this 555 556 <enum 29 reo_destination_29> REO remaps this 557 558 <enum 30 reo_destination_30> REO remaps this 559 560 <enum 31 reo_destination_31> REO remaps this 561 562 563 564 <legal all> 565 566 flow_idx 567 568 Flow table index 569 570 <legal all> 571 572 reserved_12a 573 574 <legal 0> 575 576 fse_metadata 577 578 FSE related meta data: 579 580 <legal all> 581 582 cce_metadata 583 584 CCE related meta data: 585 586 <legal all> 587 588 sa_sw_peer_id 589 590 sw_peer_id from the address search entry corresponding 591 to the source address of the MSDU 592 593 <legal all> 594 595 aggregation_count 596 597 FISA: Number of MSDU's aggregated so far 598 599 600 601 Set to zero in chips not supporting FISA, e.g. Pine 602 603 <legal all> 604 605 flow_aggregation_continuation 606 607 FISA: To indicate that this MSDU can be aggregated with 608 the previous packet with the same flow id 609 610 611 612 Set to zero in chips not supporting FISA, e.g. Pine 613 614 <legal all> 615 616 fisa_timeout 617 618 FISA: To indicate that the aggregation has restarted for 619 this flow due to timeout 620 621 622 623 Set to zero in chips not supporting FISA, e.g. Pine 624 625 <legal all> 626 627 reserved_15a 628 629 <legal 0> 630 631 cumulative_l4_checksum 632 633 FISA: checksum for MSDU's that is part of this flow 634 aggregated so far 635 636 637 638 Set to zero in chips not supporting FISA, e.g. Pine 639 640 <legal all> 641 642 cumulative_ip_length 643 644 FISA: Total MSDU length that is part of this flow 645 aggregated so far 646 647 648 649 Set to zero in chips not supporting FISA, e.g. Pine 650 651 <legal all> 652 */ 653 654 655 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 656 657 Field indicates what the reason was that this MPDU frame 658 was allowed to come into the receive path by RXPCU 659 660 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 661 frame filter programming of rxpcu 662 663 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 664 regular frame filter and would have been dropped, were it 665 not for the frame fitting into the 'monitor_client' 666 category. 667 668 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 669 regular frame filter and also did not pass the 670 rxpcu_monitor_client filter. It would have been dropped 671 accept that it did pass the 'monitor_other' category. 672 673 <legal 0-2> 674 */ 675 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 676 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 677 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 678 679 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 680 681 SW processes frames based on certain classifications. 682 This field indicates to what sw classification this MPDU is 683 mapped. 684 685 The classification is given in priority order 686 687 688 689 <enum 0 sw_frame_group_NDP_frame> 690 691 692 693 <enum 1 sw_frame_group_Multicast_data> 694 695 <enum 2 sw_frame_group_Unicast_data> 696 697 <enum 3 sw_frame_group_Null_data > This includes mpdus 698 of type Data Null as well as QoS Data Null 699 700 701 702 <enum 4 sw_frame_group_mgmt_0000 > 703 704 <enum 5 sw_frame_group_mgmt_0001 > 705 706 <enum 6 sw_frame_group_mgmt_0010 > 707 708 <enum 7 sw_frame_group_mgmt_0011 > 709 710 <enum 8 sw_frame_group_mgmt_0100 > 711 712 <enum 9 sw_frame_group_mgmt_0101 > 713 714 <enum 10 sw_frame_group_mgmt_0110 > 715 716 <enum 11 sw_frame_group_mgmt_0111 > 717 718 <enum 12 sw_frame_group_mgmt_1000 > 719 720 <enum 13 sw_frame_group_mgmt_1001 > 721 722 <enum 14 sw_frame_group_mgmt_1010 > 723 724 <enum 15 sw_frame_group_mgmt_1011 > 725 726 <enum 16 sw_frame_group_mgmt_1100 > 727 728 <enum 17 sw_frame_group_mgmt_1101 > 729 730 <enum 18 sw_frame_group_mgmt_1110 > 731 732 <enum 19 sw_frame_group_mgmt_1111 > 733 734 735 736 <enum 20 sw_frame_group_ctrl_0000 > 737 738 <enum 21 sw_frame_group_ctrl_0001 > 739 740 <enum 22 sw_frame_group_ctrl_0010 > 741 742 <enum 23 sw_frame_group_ctrl_0011 > 743 744 <enum 24 sw_frame_group_ctrl_0100 > 745 746 <enum 25 sw_frame_group_ctrl_0101 > 747 748 <enum 26 sw_frame_group_ctrl_0110 > 749 750 <enum 27 sw_frame_group_ctrl_0111 > 751 752 <enum 28 sw_frame_group_ctrl_1000 > 753 754 <enum 29 sw_frame_group_ctrl_1001 > 755 756 <enum 30 sw_frame_group_ctrl_1010 > 757 758 <enum 31 sw_frame_group_ctrl_1011 > 759 760 <enum 32 sw_frame_group_ctrl_1100 > 761 762 <enum 33 sw_frame_group_ctrl_1101 > 763 764 <enum 34 sw_frame_group_ctrl_1110 > 765 766 <enum 35 sw_frame_group_ctrl_1111 > 767 768 769 770 <enum 36 sw_frame_group_unsupported> This covers type 3 771 and protocol version != 0 772 773 774 775 776 777 778 <legal 0-37> 779 */ 780 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 781 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 782 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 783 784 /* Description RX_MSDU_END_0_RESERVED_0 785 786 <legal 0> 787 */ 788 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 789 #define RX_MSDU_END_0_RESERVED_0_LSB 9 790 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 791 792 /* Description RX_MSDU_END_0_PHY_PPDU_ID 793 794 A ppdu counter value that PHY increments for every PPDU 795 received. The counter value wraps around 796 797 <legal all> 798 */ 799 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 800 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 801 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 802 803 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 804 805 This can include the IP header checksum or the pseudo 806 header checksum used by TCP/UDP checksum. 807 808 (with the first byte in the MSB and the second byte in 809 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 810 w.r.t. the byte order in a packet) 811 */ 812 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 813 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 814 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 815 816 /* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH 817 818 MPDU length before decapsulation. Only valid when 819 first_msdu is set. This field is taken directly from the 820 length field of the A-MPDU delimiter or the preamble length 821 field for non-A-MPDU frames. 822 */ 823 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 824 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 825 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 826 827 /* Description RX_MSDU_END_1_RESERVED_1A 828 829 <legal 0> 830 */ 831 #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 832 #define RX_MSDU_END_1_RESERVED_1A_LSB 30 833 #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 834 835 /* Description RX_MSDU_END_2_KEY_ID_OCTET 836 837 The key ID octet from the IV. Only valid when 838 first_msdu is set. 839 */ 840 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 841 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 842 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 843 844 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 845 846 Indicates the super filter rule 847 */ 848 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 849 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 850 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 851 852 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 853 854 Classification failed due to truncated frame 855 */ 856 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 857 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 858 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 859 860 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 861 862 Classification failed due to CCE global disable 863 */ 864 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 865 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 866 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 867 868 /* Description RX_MSDU_END_2_RESERVED_2A 869 870 <legal 0> 871 */ 872 #define RX_MSDU_END_2_RESERVED_2A_OFFSET 0x00000008 873 #define RX_MSDU_END_2_RESERVED_2A_LSB 16 874 #define RX_MSDU_END_2_RESERVED_2A_MASK 0xffff0000 875 876 /* Description RX_MSDU_END_3_RULE_INDICATION_31_0 877 878 Bitmap indicating which of rules 31-0 have matched 879 */ 880 #define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c 881 #define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 882 #define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff 883 884 /* Description RX_MSDU_END_4_RULE_INDICATION_63_32 885 886 Bitmap indicating which of rules 63-32 have matched 887 */ 888 #define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 889 #define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 890 #define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff 891 892 /* Description RX_MSDU_END_5_DA_OFFSET 893 894 Offset into MSDU buffer for DA 895 */ 896 #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 897 #define RX_MSDU_END_5_DA_OFFSET_LSB 0 898 #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f 899 900 /* Description RX_MSDU_END_5_SA_OFFSET 901 902 Offset into MSDU buffer for SA 903 */ 904 #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 905 #define RX_MSDU_END_5_SA_OFFSET_LSB 6 906 #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 907 908 /* Description RX_MSDU_END_5_DA_OFFSET_VALID 909 910 da_offset field is valid. This will be set to 0 in case 911 of a dynamic A-MSDU when DA is compressed 912 */ 913 #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 914 #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 915 #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 916 917 /* Description RX_MSDU_END_5_SA_OFFSET_VALID 918 919 sa_offset field is valid. This will be set to 0 in case 920 of a dynamic A-MSDU when SA is compressed 921 */ 922 #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 923 #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 924 #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 925 926 /* Description RX_MSDU_END_5_RESERVED_5A 927 928 <legal 0> 929 */ 930 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 931 #define RX_MSDU_END_5_RESERVED_5A_LSB 14 932 #define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 933 934 /* Description RX_MSDU_END_5_L3_TYPE 935 936 The 16-bit type value indicating the type of L3 later 937 extracted from LLC/SNAP, set to zero if SNAP is not 938 available 939 */ 940 #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 941 #define RX_MSDU_END_5_L3_TYPE_LSB 16 942 #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 943 944 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 945 946 32 bit CRC computed out of IP v6 extension headers 947 */ 948 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 949 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 950 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 951 952 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 953 954 TCP sequence number (as a number assembled from a TCP 955 packet in big-endian order, i.e. requiring a byte-swap for 956 little-endian FW/SW w.r.t. the byte order in a packet) 957 */ 958 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 959 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 960 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 961 962 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 963 964 TCP acknowledge number (as a number assembled from a TCP 965 packet in big-endian order, i.e. requiring a byte-swap for 966 little-endian FW/SW w.r.t. the byte order in a packet) 967 */ 968 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 969 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 970 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 971 972 /* Description RX_MSDU_END_9_TCP_FLAG 973 974 TCP flags 975 976 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 977 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 978 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 979 the byte order in a packet) 980 */ 981 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 982 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 983 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 984 985 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 986 987 Computed out of TCP and IP fields to indicate that this 988 MSDU is eligible for LRO 989 */ 990 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 991 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 992 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 993 994 /* Description RX_MSDU_END_9_RESERVED_9A 995 996 NOTE: DO not assign a field... Internally used in 997 RXOLE.. 998 999 <legal 0> 1000 */ 1001 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1002 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1003 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1004 1005 /* Description RX_MSDU_END_9_WINDOW_SIZE 1006 1007 TCP receive window size (as a number assembled from a 1008 TCP packet in big-endian order, i.e. requiring a byte-swap 1009 for little-endian FW/SW w.r.t. the byte order in a packet) 1010 */ 1011 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1012 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1013 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1014 1015 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM 1016 1017 The value of the computed TCP/UDP checksum. A mode bit 1018 selects whether this checksum is the full checksum or the 1019 partial checksum which does not include the pseudo header. 1020 (with the first byte in the MSB and the second byte in the 1021 LSB, i.e. requiring a byte-swap for little-endian FW/SW 1022 w.r.t. the byte order in a packet) 1023 */ 1024 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 1025 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 1026 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff 1027 1028 /* Description RX_MSDU_END_10_SA_IDX_TIMEOUT 1029 1030 Indicates an unsuccessful MAC source address search due 1031 to the expiring of the search timer. 1032 */ 1033 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 1034 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 1035 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 1036 1037 /* Description RX_MSDU_END_10_DA_IDX_TIMEOUT 1038 1039 Indicates an unsuccessful MAC destination address search 1040 due to the expiring of the search timer. 1041 */ 1042 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 1043 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 1044 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 1045 1046 /* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR 1047 1048 Indicates that the MSDU threshold was exceeded and thus 1049 all the rest of the MSDUs will not be scattered and will not 1050 be decapsulated but will be DMA'ed in RAW format as a single 1051 MSDU buffer 1052 */ 1053 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 1054 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 1055 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 1056 1057 /* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT 1058 1059 Indicates an unsuccessful flow search due to the 1060 expiring of the search timer. 1061 1062 <legal all> 1063 */ 1064 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 1065 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 1066 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 1067 1068 /* Description RX_MSDU_END_10_FLOW_IDX_INVALID 1069 1070 flow id is not valid 1071 1072 <legal all> 1073 */ 1074 #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 1075 #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 1076 #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 1077 1078 /* Description RX_MSDU_END_10_WIFI_PARSER_ERROR 1079 1080 Indicates that the WiFi frame has one of the following 1081 errors 1082 1083 o has less than minimum allowed bytes as per standard 1084 1085 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 1086 1087 <legal all> 1088 */ 1089 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 1090 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 1091 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 1092 1093 /* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR 1094 1095 A-MSDU could not be properly de-agregated. 1096 1097 <legal all> 1098 */ 1099 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 1100 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 1101 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 1102 1103 /* Description RX_MSDU_END_10_SA_IS_VALID 1104 1105 Indicates that OLE found a valid SA entry 1106 */ 1107 #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 1108 #define RX_MSDU_END_10_SA_IS_VALID_LSB 23 1109 #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 1110 1111 /* Description RX_MSDU_END_10_DA_IS_VALID 1112 1113 Indicates that OLE found a valid DA entry 1114 */ 1115 #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 1116 #define RX_MSDU_END_10_DA_IS_VALID_LSB 24 1117 #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 1118 1119 /* Description RX_MSDU_END_10_DA_IS_MCBC 1120 1121 Field Only valid if da_is_valid is set 1122 1123 1124 1125 Indicates the DA address was a Multicast of Broadcast 1126 address. 1127 */ 1128 #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 1129 #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 1130 #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 1131 1132 /* Description RX_MSDU_END_10_L3_HEADER_PADDING 1133 1134 Number of bytes padded to make sure that the L3 header 1135 will always start of a Dword boundary 1136 */ 1137 #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 1138 #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 1139 #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 1140 1141 /* Description RX_MSDU_END_10_FIRST_MSDU 1142 1143 Indicates the first MSDU of A-MSDU. If both first_msdu 1144 and last_msdu are set in the MSDU then this is a 1145 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 1146 A-MSDU shall have both first_mpdu and last_mpdu bits set to 1147 0. 1148 */ 1149 #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 1150 #define RX_MSDU_END_10_FIRST_MSDU_LSB 28 1151 #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 1152 1153 /* Description RX_MSDU_END_10_LAST_MSDU 1154 1155 Indicates the last MSDU of the A-MSDU. MPDU end status 1156 is only valid when last_msdu is set. 1157 */ 1158 #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 1159 #define RX_MSDU_END_10_LAST_MSDU_LSB 29 1160 #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 1161 1162 /* Description RX_MSDU_END_10_RESERVED_10A 1163 1164 <legal 0> 1165 */ 1166 #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 1167 #define RX_MSDU_END_10_RESERVED_10A_LSB 30 1168 #define RX_MSDU_END_10_RESERVED_10A_MASK 0xc0000000 1169 1170 /* Description RX_MSDU_END_11_SA_IDX 1171 1172 The offset in the address table which matches the MAC 1173 source address. 1174 */ 1175 #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c 1176 #define RX_MSDU_END_11_SA_IDX_LSB 0 1177 #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff 1178 1179 /* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID 1180 1181 Based on a register configuration in RXOLE, this field 1182 will contain: 1183 1184 The offset in the address table which matches the MAC 1185 destination address 1186 1187 OR: 1188 1189 sw_peer_id from the address search entry corresponding 1190 to the destination address of the MSDU 1191 */ 1192 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 1193 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 1194 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 1195 1196 /* Description RX_MSDU_END_12_MSDU_DROP 1197 1198 When set, REO shall drop this MSDU and not forward it to 1199 any other ring... 1200 1201 <legal all> 1202 */ 1203 #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 1204 #define RX_MSDU_END_12_MSDU_DROP_LSB 0 1205 #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 1206 1207 /* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION 1208 1209 The ID of the REO exit ring where the MSDU frame shall 1210 push after (MPDU level) reordering has finished. 1211 1212 1213 1214 <enum 0 reo_destination_tcl> Reo will push the frame 1215 into the REO2TCL ring 1216 1217 <enum 1 reo_destination_sw1> Reo will push the frame 1218 into the REO2SW1 ring 1219 1220 <enum 2 reo_destination_sw2> Reo will push the frame 1221 into the REO2SW2 ring 1222 1223 <enum 3 reo_destination_sw3> Reo will push the frame 1224 into the REO2SW3 ring 1225 1226 <enum 4 reo_destination_sw4> Reo will push the frame 1227 into the REO2SW4 ring 1228 1229 <enum 5 reo_destination_release> Reo will push the frame 1230 into the REO_release ring 1231 1232 <enum 6 reo_destination_fw> Reo will push the frame into 1233 the REO2FW ring 1234 1235 <enum 7 reo_destination_sw5> Reo will push the frame 1236 into the REO2SW5 ring (REO remaps this in chips without 1237 REO2SW5 ring, e.g. Pine) 1238 1239 <enum 8 reo_destination_sw6> Reo will push the frame 1240 into the REO2SW6 ring (REO remaps this in chips without 1241 REO2SW6 ring, e.g. Pine) 1242 1243 <enum 9 reo_destination_9> REO remaps this <enum 10 1244 reo_destination_10> REO remaps this 1245 1246 <enum 11 reo_destination_11> REO remaps this 1247 1248 <enum 12 reo_destination_12> REO remaps this <enum 13 1249 reo_destination_13> REO remaps this 1250 1251 <enum 14 reo_destination_14> REO remaps this 1252 1253 <enum 15 reo_destination_15> REO remaps this 1254 1255 <enum 16 reo_destination_16> REO remaps this 1256 1257 <enum 17 reo_destination_17> REO remaps this 1258 1259 <enum 18 reo_destination_18> REO remaps this 1260 1261 <enum 19 reo_destination_19> REO remaps this 1262 1263 <enum 20 reo_destination_20> REO remaps this 1264 1265 <enum 21 reo_destination_21> REO remaps this 1266 1267 <enum 22 reo_destination_22> REO remaps this 1268 1269 <enum 23 reo_destination_23> REO remaps this 1270 1271 <enum 24 reo_destination_24> REO remaps this 1272 1273 <enum 25 reo_destination_25> REO remaps this 1274 1275 <enum 26 reo_destination_26> REO remaps this 1276 1277 <enum 27 reo_destination_27> REO remaps this 1278 1279 <enum 28 reo_destination_28> REO remaps this 1280 1281 <enum 29 reo_destination_29> REO remaps this 1282 1283 <enum 30 reo_destination_30> REO remaps this 1284 1285 <enum 31 reo_destination_31> REO remaps this 1286 1287 1288 1289 <legal all> 1290 */ 1291 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 1292 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 1293 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e 1294 1295 /* Description RX_MSDU_END_12_FLOW_IDX 1296 1297 Flow table index 1298 1299 <legal all> 1300 */ 1301 #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 1302 #define RX_MSDU_END_12_FLOW_IDX_LSB 6 1303 #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 1304 1305 /* Description RX_MSDU_END_12_RESERVED_12A 1306 1307 <legal 0> 1308 */ 1309 #define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 1310 #define RX_MSDU_END_12_RESERVED_12A_LSB 26 1311 #define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 1312 1313 /* Description RX_MSDU_END_13_FSE_METADATA 1314 1315 FSE related meta data: 1316 1317 <legal all> 1318 */ 1319 #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 1320 #define RX_MSDU_END_13_FSE_METADATA_LSB 0 1321 #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff 1322 1323 /* Description RX_MSDU_END_14_CCE_METADATA 1324 1325 CCE related meta data: 1326 1327 <legal all> 1328 */ 1329 #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 1330 #define RX_MSDU_END_14_CCE_METADATA_LSB 0 1331 #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff 1332 1333 /* Description RX_MSDU_END_14_SA_SW_PEER_ID 1334 1335 sw_peer_id from the address search entry corresponding 1336 to the source address of the MSDU 1337 1338 <legal all> 1339 */ 1340 #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 1341 #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 1342 #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 1343 1344 /* Description RX_MSDU_END_15_AGGREGATION_COUNT 1345 1346 FISA: Number of MSDU's aggregated so far 1347 1348 1349 1350 Set to zero in chips not supporting FISA, e.g. Pine 1351 1352 <legal all> 1353 */ 1354 #define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c 1355 #define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 1356 #define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff 1357 1358 /* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION 1359 1360 FISA: To indicate that this MSDU can be aggregated with 1361 the previous packet with the same flow id 1362 1363 1364 1365 Set to zero in chips not supporting FISA, e.g. Pine 1366 1367 <legal all> 1368 */ 1369 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c 1370 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 1371 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 1372 1373 /* Description RX_MSDU_END_15_FISA_TIMEOUT 1374 1375 FISA: To indicate that the aggregation has restarted for 1376 this flow due to timeout 1377 1378 1379 1380 Set to zero in chips not supporting FISA, e.g. Pine 1381 1382 <legal all> 1383 */ 1384 #define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c 1385 #define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 1386 #define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 1387 1388 /* Description RX_MSDU_END_15_RESERVED_15A 1389 1390 <legal 0> 1391 */ 1392 #define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c 1393 #define RX_MSDU_END_15_RESERVED_15A_LSB 10 1394 #define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 1395 1396 /* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM 1397 1398 FISA: checksum for MSDU's that is part of this flow 1399 aggregated so far 1400 1401 1402 1403 Set to zero in chips not supporting FISA, e.g. Pine 1404 1405 <legal all> 1406 */ 1407 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 1408 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 1409 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 1410 1411 /* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH 1412 1413 FISA: Total MSDU length that is part of this flow 1414 aggregated so far 1415 1416 1417 1418 Set to zero in chips not supporting FISA, e.g. Pine 1419 1420 <legal all> 1421 */ 1422 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 1423 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 1424 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 1425 1426 1427 #endif // _RX_MSDU_END_H_ 1428