1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_LINK_H_ 18 #define _RX_MSDU_LINK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "buffer_addr_info.h" 24 #include "rx_msdu_details.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 struct uniform_descriptor_header descriptor_header; 30 // 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; 31 // 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] 32 // 4 pn_31_0[31:0] 33 // 5 pn_63_32[31:0] 34 // 6 pn_95_64[31:0] 35 // 7 pn_127_96[31:0] 36 // 8-11 struct rx_msdu_details msdu_0; 37 // 12-15 struct rx_msdu_details msdu_1; 38 // 16-19 struct rx_msdu_details msdu_2; 39 // 20-23 struct rx_msdu_details msdu_3; 40 // 24-27 struct rx_msdu_details msdu_4; 41 // 28-31 struct rx_msdu_details msdu_5; 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 46 47 struct rx_msdu_link { 48 struct uniform_descriptor_header descriptor_header; 49 struct buffer_addr_info next_msdu_link_desc_addr_info; 50 uint32_t receive_queue_number : 16, //[15:0] 51 first_rx_msdu_link_struct : 1, //[16] 52 reserved_3a : 15; //[31:17] 53 uint32_t pn_31_0 : 32; //[31:0] 54 uint32_t pn_63_32 : 32; //[31:0] 55 uint32_t pn_95_64 : 32; //[31:0] 56 uint32_t pn_127_96 : 32; //[31:0] 57 struct rx_msdu_details msdu_0; 58 struct rx_msdu_details msdu_1; 59 struct rx_msdu_details msdu_2; 60 struct rx_msdu_details msdu_3; 61 struct rx_msdu_details msdu_4; 62 struct rx_msdu_details msdu_5; 63 }; 64 65 /* 66 67 struct uniform_descriptor_header descriptor_header 68 69 Details about which module owns this struct. 70 71 Note that sub field Buffer_type shall be set to 72 Receive_MSDU_Link_descriptor 73 74 struct buffer_addr_info next_msdu_link_desc_addr_info 75 76 Details of the physical address of the next MSDU link 77 descriptor that contains info about additional MSDUs that 78 are part of this MPDU. 79 80 receive_queue_number 81 82 Indicates the Receive queue to which this MPDU 83 descriptor belongs 84 85 Used for tracking, finding bugs and debugging. 86 87 <legal all> 88 89 first_rx_msdu_link_struct 90 91 When set, this RX_MSDU_link descriptor is the first one 92 in the MSDU link list. Field MSDU_0 points to the very first 93 MSDU buffer descriptor in the MPDU 94 95 <legal all> 96 97 reserved_3a 98 99 <legal 0> 100 101 pn_31_0 102 103 104 105 106 31-0 bits of the 256-bit packet number bitmap. 107 108 <legal all> 109 110 pn_63_32 111 112 113 114 115 63-32 bits of the 256-bit packet number bitmap. 116 117 <legal all> 118 119 pn_95_64 120 121 122 123 124 95-64 bits of the 256-bit packet number bitmap. 125 126 <legal all> 127 128 pn_127_96 129 130 131 132 133 127-96 bits of the 256-bit packet number bitmap. 134 135 <legal all> 136 137 struct rx_msdu_details msdu_0 138 139 When First_RX_MSDU_link_struct is set, this MSDU is the 140 first in the MPDU 141 142 143 144 When First_RX_MSDU_link_struct is NOT set, this MSDU 145 follows the last MSDU in the previous RX_MSDU_link data 146 structure 147 148 struct rx_msdu_details msdu_1 149 150 Details of next MSDU in this (MSDU flow) linked list 151 152 struct rx_msdu_details msdu_2 153 154 Details of next MSDU in this (MSDU flow) linked list 155 156 struct rx_msdu_details msdu_3 157 158 Details of next MSDU in this (MSDU flow) linked list 159 160 struct rx_msdu_details msdu_4 161 162 Details of next MSDU in this (MSDU flow) linked list 163 164 struct rx_msdu_details msdu_5 165 166 Details of next MSDU in this (MSDU flow) linked list 167 */ 168 169 170 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 171 172 173 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER 174 175 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 176 177 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 178 179 180 181 The owner of this data structure: 182 183 <enum 0 WBM_owned> Buffer Manager currently owns this 184 data structure. 185 186 <enum 1 SW_OR_FW_owned> Software of FW currently owns 187 this data structure. 188 189 <enum 2 TQM_owned> Transmit Queue Manager currently owns 190 this data structure. 191 192 <enum 3 RXDMA_owned> Receive DMA currently owns this 193 data structure. 194 195 <enum 4 REO_owned> Reorder currently owns this data 196 structure. 197 198 <enum 5 SWITCH_owned> SWITCH currently owns this data 199 structure. 200 201 202 203 <legal 0-5> 204 */ 205 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 206 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 207 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 208 209 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE 210 211 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 212 213 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 214 215 216 217 Field describing what contents format is of this 218 descriptor 219 220 221 222 <enum 0 Transmit_MSDU_Link_descriptor > 223 224 <enum 1 Transmit_MPDU_Link_descriptor > 225 226 <enum 2 Transmit_MPDU_Queue_head_descriptor> 227 228 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 229 230 <enum 4 Transmit_flow_descriptor> 231 232 <enum 5 Transmit_buffer > NOT TO BE USED: 233 234 235 236 <enum 6 Receive_MSDU_Link_descriptor > 237 238 <enum 7 Receive_MPDU_Link_descriptor > 239 240 <enum 8 Receive_REO_queue_descriptor > 241 242 <enum 9 Receive_REO_queue_ext_descriptor > 243 244 245 246 <enum 10 Receive_buffer > 247 248 249 250 <enum 11 Idle_link_list_entry> 251 252 253 254 <legal 0-11> 255 */ 256 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 257 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 258 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 259 260 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A 261 262 <legal 0> 263 */ 264 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 265 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 266 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 267 268 /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */ 269 270 271 /* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 272 273 Address (lower 32 bits) of the MSDU buffer OR 274 MSDU_EXTENSION descriptor OR Link Descriptor 275 276 277 278 In case of 'NULL' pointer, this field is set to 0 279 280 <legal all> 281 */ 282 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 283 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 284 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 285 286 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 287 288 Address (upper 8 bits) of the MSDU buffer OR 289 MSDU_EXTENSION descriptor OR Link Descriptor 290 291 292 293 In case of 'NULL' pointer, this field is set to 0 294 295 <legal all> 296 */ 297 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 298 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 299 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 300 301 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 302 303 Consumer: WBM 304 305 Producer: SW/FW 306 307 308 309 In case of 'NULL' pointer, this field is set to 0 310 311 312 313 Indicates to which buffer manager the buffer OR 314 MSDU_EXTENSION descriptor OR link descriptor that is being 315 pointed to shall be returned after the frame has been 316 processed. It is used by WBM for routing purposes. 317 318 319 320 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 321 to the WMB buffer idle list 322 323 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 324 returned to the WMB idle link descriptor idle list 325 326 <enum 2 FW_BM> This buffer shall be returned to the FW 327 328 <enum 3 SW0_BM> This buffer shall be returned to the SW, 329 ring 0 330 331 <enum 4 SW1_BM> This buffer shall be returned to the SW, 332 ring 1 333 334 <enum 5 SW2_BM> This buffer shall be returned to the SW, 335 ring 2 336 337 <enum 6 SW3_BM> This buffer shall be returned to the SW, 338 ring 3 339 340 <enum 7 SW4_BM> This buffer shall be returned to the SW, 341 ring 4 342 343 344 345 <legal all> 346 */ 347 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 348 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 349 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 350 351 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 352 353 Cookie field exclusively used by SW. 354 355 356 357 In case of 'NULL' pointer, this field is set to 0 358 359 360 361 HW ignores the contents, accept that it passes the 362 programmed value on to other descriptors together with the 363 physical address 364 365 366 367 Field can be used by SW to for example associate the 368 buffers physical address with the virtual address 369 370 The bit definitions as used by SW are within SW HLD 371 specification 372 373 374 375 NOTE: 376 377 The three most significant bits can have a special 378 meaning in case this struct is embedded in a TX_MPDU_DETAILS 379 STRUCT, and field transmit_bw_restriction is set 380 381 382 383 In case of NON punctured transmission: 384 385 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 386 387 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 388 389 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 390 391 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 392 393 394 395 In case of punctured transmission: 396 397 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 398 399 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 400 401 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 402 403 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 404 405 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 406 407 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 408 409 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 410 411 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 412 413 414 415 Note: a punctured transmission is indicated by the 416 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 417 TLV 418 419 420 421 <legal all> 422 */ 423 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 424 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 425 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 426 427 /* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER 428 429 Indicates the Receive queue to which this MPDU 430 descriptor belongs 431 432 Used for tracking, finding bugs and debugging. 433 434 <legal all> 435 */ 436 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 437 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 438 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 439 440 /* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT 441 442 When set, this RX_MSDU_link descriptor is the first one 443 in the MSDU link list. Field MSDU_0 points to the very first 444 MSDU buffer descriptor in the MPDU 445 446 <legal all> 447 */ 448 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 449 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 450 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 451 452 /* Description RX_MSDU_LINK_3_RESERVED_3A 453 454 <legal 0> 455 */ 456 #define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c 457 #define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 458 #define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 459 460 /* Description RX_MSDU_LINK_4_PN_31_0 461 462 463 464 465 31-0 bits of the 256-bit packet number bitmap. 466 467 <legal all> 468 */ 469 #define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 470 #define RX_MSDU_LINK_4_PN_31_0_LSB 0 471 #define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff 472 473 /* Description RX_MSDU_LINK_5_PN_63_32 474 475 476 477 478 63-32 bits of the 256-bit packet number bitmap. 479 480 <legal all> 481 */ 482 #define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 483 #define RX_MSDU_LINK_5_PN_63_32_LSB 0 484 #define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff 485 486 /* Description RX_MSDU_LINK_6_PN_95_64 487 488 489 490 491 95-64 bits of the 256-bit packet number bitmap. 492 493 <legal all> 494 */ 495 #define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 496 #define RX_MSDU_LINK_6_PN_95_64_LSB 0 497 #define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff 498 499 /* Description RX_MSDU_LINK_7_PN_127_96 500 501 502 503 504 127-96 bits of the 256-bit packet number bitmap. 505 506 <legal all> 507 */ 508 #define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c 509 #define RX_MSDU_LINK_7_PN_127_96_LSB 0 510 #define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff 511 512 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */ 513 514 515 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 516 517 518 /* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 519 520 Address (lower 32 bits) of the MSDU buffer OR 521 MSDU_EXTENSION descriptor OR Link Descriptor 522 523 524 525 In case of 'NULL' pointer, this field is set to 0 526 527 <legal all> 528 */ 529 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 530 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 531 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 532 533 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 534 535 Address (upper 8 bits) of the MSDU buffer OR 536 MSDU_EXTENSION descriptor OR Link Descriptor 537 538 539 540 In case of 'NULL' pointer, this field is set to 0 541 542 <legal all> 543 */ 544 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 545 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 546 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 547 548 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 549 550 Consumer: WBM 551 552 Producer: SW/FW 553 554 555 556 In case of 'NULL' pointer, this field is set to 0 557 558 559 560 Indicates to which buffer manager the buffer OR 561 MSDU_EXTENSION descriptor OR link descriptor that is being 562 pointed to shall be returned after the frame has been 563 processed. It is used by WBM for routing purposes. 564 565 566 567 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 568 to the WMB buffer idle list 569 570 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 571 returned to the WMB idle link descriptor idle list 572 573 <enum 2 FW_BM> This buffer shall be returned to the FW 574 575 <enum 3 SW0_BM> This buffer shall be returned to the SW, 576 ring 0 577 578 <enum 4 SW1_BM> This buffer shall be returned to the SW, 579 ring 1 580 581 <enum 5 SW2_BM> This buffer shall be returned to the SW, 582 ring 2 583 584 <enum 6 SW3_BM> This buffer shall be returned to the SW, 585 ring 3 586 587 <enum 7 SW4_BM> This buffer shall be returned to the SW, 588 ring 4 589 590 591 592 <legal all> 593 */ 594 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 595 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 596 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 597 598 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 599 600 Cookie field exclusively used by SW. 601 602 603 604 In case of 'NULL' pointer, this field is set to 0 605 606 607 608 HW ignores the contents, accept that it passes the 609 programmed value on to other descriptors together with the 610 physical address 611 612 613 614 Field can be used by SW to for example associate the 615 buffers physical address with the virtual address 616 617 The bit definitions as used by SW are within SW HLD 618 specification 619 620 621 622 NOTE: 623 624 The three most significant bits can have a special 625 meaning in case this struct is embedded in a TX_MPDU_DETAILS 626 STRUCT, and field transmit_bw_restriction is set 627 628 629 630 In case of NON punctured transmission: 631 632 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 633 634 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 635 636 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 637 638 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 639 640 641 642 In case of punctured transmission: 643 644 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 645 646 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 647 648 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 649 650 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 651 652 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 653 654 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 655 656 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 657 658 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 659 660 661 662 Note: a punctured transmission is indicated by the 663 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 664 TLV 665 666 667 668 <legal all> 669 */ 670 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 671 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 672 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 673 674 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 675 676 677 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 678 679 Parsed from RX_MSDU_END TLV . In the case MSDU spans 680 over multiple buffers, this field will be valid in the Last 681 buffer used by the MSDU 682 683 684 685 <enum 0 Not_first_msdu> This is not the first MSDU in 686 the MPDU. 687 688 <enum 1 first_msdu> This MSDU is the first one in the 689 MPDU. 690 691 692 693 <legal all> 694 */ 695 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 696 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 697 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 698 699 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 700 701 Consumer: WBM/REO/SW/FW 702 703 Producer: RXDMA 704 705 706 707 Parsed from RX_MSDU_END TLV . In the case MSDU spans 708 over multiple buffers, this field will be valid in the Last 709 buffer used by the MSDU 710 711 712 713 <enum 0 Not_last_msdu> There are more MSDUs linked to 714 this MSDU that belongs to this MPDU 715 716 <enum 1 Last_msdu> this MSDU is the last one in the 717 MPDU. This setting is only allowed in combination with 718 'Msdu_continuation' set to 0. This implies that when an msdu 719 is spread out over multiple buffers and thus 720 msdu_continuation is set, only for the very last buffer of 721 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 722 723 724 725 When both first_msdu_in_mpdu_flag and 726 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 727 belongs to only contains a single MSDU. 728 729 730 731 732 733 <legal all> 734 */ 735 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 736 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 737 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 738 739 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 740 741 When set, this MSDU buffer was not able to hold the 742 entire MSDU. The next buffer will therefor contain 743 additional information related to this MSDU. 744 745 746 747 <legal all> 748 */ 749 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 750 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 751 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 752 753 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 754 755 Parsed from RX_MSDU_START TLV . In the case MSDU spans 756 over multiple buffers, this field will be valid in the First 757 buffer used by MSDU. 758 759 760 761 Full MSDU length in bytes after decapsulation. 762 763 764 765 This field is still valid for MPDU frames without 766 A-MSDU. It still represents MSDU length after decapsulation 767 768 769 770 Or in case of RAW MPDUs, it indicates the length of the 771 entire MPDU (without FCS field) 772 773 <legal all> 774 */ 775 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 776 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 777 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 778 779 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 780 781 Parsed from RX_MSDU_END TLV . In the case MSDU spans 782 over multiple buffers, this field will be valid in the Last 783 buffer used by the MSDU 784 785 786 787 The ID of the REO exit ring where the MSDU frame shall 788 push after (MPDU level) reordering has finished. 789 790 791 792 <enum 0 reo_destination_tcl> Reo will push the frame 793 into the REO2TCL ring 794 795 <enum 1 reo_destination_sw1> Reo will push the frame 796 into the REO2SW1 ring 797 798 <enum 2 reo_destination_sw2> Reo will push the frame 799 into the REO2SW2 ring 800 801 <enum 3 reo_destination_sw3> Reo will push the frame 802 into the REO2SW3 ring 803 804 <enum 4 reo_destination_sw4> Reo will push the frame 805 into the REO2SW4 ring 806 807 <enum 5 reo_destination_release> Reo will push the frame 808 into the REO_release ring 809 810 <enum 6 reo_destination_fw> Reo will push the frame into 811 the REO2FW ring 812 813 <enum 7 reo_destination_sw5> Reo will push the frame 814 into the REO2SW5 ring 815 816 <enum 8 reo_destination_sw6> Reo will push the frame 817 into the REO2SW6 ring 818 819 <enum 9 reo_destination_9> REO remaps this <enum 10 820 reo_destination_10> REO remaps this 821 822 <enum 11 reo_destination_11> REO remaps this 823 824 <enum 12 reo_destination_12> REO remaps this <enum 13 825 reo_destination_13> REO remaps this 826 827 <enum 14 reo_destination_14> REO remaps this 828 829 <enum 15 reo_destination_15> REO remaps this 830 831 <enum 16 reo_destination_16> REO remaps this 832 833 <enum 17 reo_destination_17> REO remaps this 834 835 <enum 18 reo_destination_18> REO remaps this 836 837 <enum 19 reo_destination_19> REO remaps this 838 839 <enum 20 reo_destination_20> REO remaps this 840 841 <enum 21 reo_destination_21> REO remaps this 842 843 <enum 22 reo_destination_22> REO remaps this 844 845 <enum 23 reo_destination_23> REO remaps this 846 847 <enum 24 reo_destination_24> REO remaps this 848 849 <enum 25 reo_destination_25> REO remaps this 850 851 <enum 26 reo_destination_26> REO remaps this 852 853 <enum 27 reo_destination_27> REO remaps this 854 855 <enum 28 reo_destination_28> REO remaps this 856 857 <enum 29 reo_destination_29> REO remaps this 858 859 <enum 30 reo_destination_30> REO remaps this 860 861 <enum 31 reo_destination_31> REO remaps this 862 863 864 865 <legal all> 866 */ 867 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 868 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 869 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 870 871 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 872 873 Parsed from RX_MSDU_END TLV . In the case MSDU spans 874 over multiple buffers, this field will be valid in the Last 875 buffer used by the MSDU 876 877 878 879 When set, REO shall drop this MSDU and not forward it to 880 any other ring... 881 882 <legal all> 883 */ 884 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 885 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 886 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 887 888 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 889 890 Parsed from RX_MSDU_END TLV . In the case MSDU spans 891 over multiple buffers, this field will be valid in the Last 892 buffer used by the MSDU 893 894 895 896 Indicates that OLE found a valid SA entry for this MSDU 897 898 <legal all> 899 */ 900 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 901 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 902 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 903 904 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 905 906 Parsed from RX_MSDU_END TLV . In the case MSDU spans 907 over multiple buffers, this field will be valid in the Last 908 buffer used by the MSDU 909 910 911 912 Indicates an unsuccessful MAC source address search due 913 to the expiring of the search timer for this MSDU 914 915 <legal all> 916 */ 917 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 918 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 919 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 920 921 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 922 923 Parsed from RX_MSDU_END TLV . In the case MSDU spans 924 over multiple buffers, this field will be valid in the Last 925 buffer used by the MSDU 926 927 928 929 Indicates that OLE found a valid DA entry for this MSDU 930 931 <legal all> 932 */ 933 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 934 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 935 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 936 937 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 938 939 Field Only valid if da_is_valid is set 940 941 942 943 Indicates the DA address was a Multicast of Broadcast 944 address for this MSDU 945 946 <legal all> 947 */ 948 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 949 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 950 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 951 952 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 953 954 Parsed from RX_MSDU_END TLV . In the case MSDU spans 955 over multiple buffers, this field will be valid in the Last 956 buffer used by the MSDU 957 958 959 960 Indicates an unsuccessful MAC destination address search 961 due to the expiring of the search timer for this MSDU 962 963 <legal all> 964 */ 965 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 966 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 967 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 968 969 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 970 971 <legal 0> 972 */ 973 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 974 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 975 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 976 977 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 978 979 <legal 0> 980 */ 981 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000002c 982 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 983 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 984 985 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */ 986 987 988 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 989 990 991 /* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 992 993 Address (lower 32 bits) of the MSDU buffer OR 994 MSDU_EXTENSION descriptor OR Link Descriptor 995 996 997 998 In case of 'NULL' pointer, this field is set to 0 999 1000 <legal all> 1001 */ 1002 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1003 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1004 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1005 1006 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1007 1008 Address (upper 8 bits) of the MSDU buffer OR 1009 MSDU_EXTENSION descriptor OR Link Descriptor 1010 1011 1012 1013 In case of 'NULL' pointer, this field is set to 0 1014 1015 <legal all> 1016 */ 1017 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1018 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1019 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1020 1021 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1022 1023 Consumer: WBM 1024 1025 Producer: SW/FW 1026 1027 1028 1029 In case of 'NULL' pointer, this field is set to 0 1030 1031 1032 1033 Indicates to which buffer manager the buffer OR 1034 MSDU_EXTENSION descriptor OR link descriptor that is being 1035 pointed to shall be returned after the frame has been 1036 processed. It is used by WBM for routing purposes. 1037 1038 1039 1040 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1041 to the WMB buffer idle list 1042 1043 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1044 returned to the WMB idle link descriptor idle list 1045 1046 <enum 2 FW_BM> This buffer shall be returned to the FW 1047 1048 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1049 ring 0 1050 1051 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1052 ring 1 1053 1054 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1055 ring 2 1056 1057 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1058 ring 3 1059 1060 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1061 ring 4 1062 1063 1064 1065 <legal all> 1066 */ 1067 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1068 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1069 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1070 1071 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1072 1073 Cookie field exclusively used by SW. 1074 1075 1076 1077 In case of 'NULL' pointer, this field is set to 0 1078 1079 1080 1081 HW ignores the contents, accept that it passes the 1082 programmed value on to other descriptors together with the 1083 physical address 1084 1085 1086 1087 Field can be used by SW to for example associate the 1088 buffers physical address with the virtual address 1089 1090 The bit definitions as used by SW are within SW HLD 1091 specification 1092 1093 1094 1095 NOTE: 1096 1097 The three most significant bits can have a special 1098 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1099 STRUCT, and field transmit_bw_restriction is set 1100 1101 1102 1103 In case of NON punctured transmission: 1104 1105 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1106 1107 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1108 1109 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1110 1111 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1112 1113 1114 1115 In case of punctured transmission: 1116 1117 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1118 1119 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1120 1121 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1122 1123 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1124 1125 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1126 1127 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1128 1129 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1130 1131 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1132 1133 1134 1135 Note: a punctured transmission is indicated by the 1136 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1137 TLV 1138 1139 1140 1141 <legal all> 1142 */ 1143 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1144 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1145 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1146 1147 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1148 1149 1150 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1151 1152 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1153 over multiple buffers, this field will be valid in the Last 1154 buffer used by the MSDU 1155 1156 1157 1158 <enum 0 Not_first_msdu> This is not the first MSDU in 1159 the MPDU. 1160 1161 <enum 1 first_msdu> This MSDU is the first one in the 1162 MPDU. 1163 1164 1165 1166 <legal all> 1167 */ 1168 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1169 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1170 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1171 1172 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1173 1174 Consumer: WBM/REO/SW/FW 1175 1176 Producer: RXDMA 1177 1178 1179 1180 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1181 over multiple buffers, this field will be valid in the Last 1182 buffer used by the MSDU 1183 1184 1185 1186 <enum 0 Not_last_msdu> There are more MSDUs linked to 1187 this MSDU that belongs to this MPDU 1188 1189 <enum 1 Last_msdu> this MSDU is the last one in the 1190 MPDU. This setting is only allowed in combination with 1191 'Msdu_continuation' set to 0. This implies that when an msdu 1192 is spread out over multiple buffers and thus 1193 msdu_continuation is set, only for the very last buffer of 1194 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1195 1196 1197 1198 When both first_msdu_in_mpdu_flag and 1199 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1200 belongs to only contains a single MSDU. 1201 1202 1203 1204 1205 1206 <legal all> 1207 */ 1208 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1209 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1210 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1211 1212 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1213 1214 When set, this MSDU buffer was not able to hold the 1215 entire MSDU. The next buffer will therefor contain 1216 additional information related to this MSDU. 1217 1218 1219 1220 <legal all> 1221 */ 1222 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1223 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1224 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1225 1226 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1227 1228 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1229 over multiple buffers, this field will be valid in the First 1230 buffer used by MSDU. 1231 1232 1233 1234 Full MSDU length in bytes after decapsulation. 1235 1236 1237 1238 This field is still valid for MPDU frames without 1239 A-MSDU. It still represents MSDU length after decapsulation 1240 1241 1242 1243 Or in case of RAW MPDUs, it indicates the length of the 1244 entire MPDU (without FCS field) 1245 1246 <legal all> 1247 */ 1248 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1249 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1250 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1251 1252 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1253 1254 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1255 over multiple buffers, this field will be valid in the Last 1256 buffer used by the MSDU 1257 1258 1259 1260 The ID of the REO exit ring where the MSDU frame shall 1261 push after (MPDU level) reordering has finished. 1262 1263 1264 1265 <enum 0 reo_destination_tcl> Reo will push the frame 1266 into the REO2TCL ring 1267 1268 <enum 1 reo_destination_sw1> Reo will push the frame 1269 into the REO2SW1 ring 1270 1271 <enum 2 reo_destination_sw2> Reo will push the frame 1272 into the REO2SW2 ring 1273 1274 <enum 3 reo_destination_sw3> Reo will push the frame 1275 into the REO2SW3 ring 1276 1277 <enum 4 reo_destination_sw4> Reo will push the frame 1278 into the REO2SW4 ring 1279 1280 <enum 5 reo_destination_release> Reo will push the frame 1281 into the REO_release ring 1282 1283 <enum 6 reo_destination_fw> Reo will push the frame into 1284 the REO2FW ring 1285 1286 <enum 7 reo_destination_sw5> Reo will push the frame 1287 into the REO2SW5 ring 1288 1289 <enum 8 reo_destination_sw6> Reo will push the frame 1290 into the REO2SW6 ring 1291 1292 <enum 9 reo_destination_9> REO remaps this <enum 10 1293 reo_destination_10> REO remaps this 1294 1295 <enum 11 reo_destination_11> REO remaps this 1296 1297 <enum 12 reo_destination_12> REO remaps this <enum 13 1298 reo_destination_13> REO remaps this 1299 1300 <enum 14 reo_destination_14> REO remaps this 1301 1302 <enum 15 reo_destination_15> REO remaps this 1303 1304 <enum 16 reo_destination_16> REO remaps this 1305 1306 <enum 17 reo_destination_17> REO remaps this 1307 1308 <enum 18 reo_destination_18> REO remaps this 1309 1310 <enum 19 reo_destination_19> REO remaps this 1311 1312 <enum 20 reo_destination_20> REO remaps this 1313 1314 <enum 21 reo_destination_21> REO remaps this 1315 1316 <enum 22 reo_destination_22> REO remaps this 1317 1318 <enum 23 reo_destination_23> REO remaps this 1319 1320 <enum 24 reo_destination_24> REO remaps this 1321 1322 <enum 25 reo_destination_25> REO remaps this 1323 1324 <enum 26 reo_destination_26> REO remaps this 1325 1326 <enum 27 reo_destination_27> REO remaps this 1327 1328 <enum 28 reo_destination_28> REO remaps this 1329 1330 <enum 29 reo_destination_29> REO remaps this 1331 1332 <enum 30 reo_destination_30> REO remaps this 1333 1334 <enum 31 reo_destination_31> REO remaps this 1335 1336 1337 1338 <legal all> 1339 */ 1340 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1341 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1342 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1343 1344 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1345 1346 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1347 over multiple buffers, this field will be valid in the Last 1348 buffer used by the MSDU 1349 1350 1351 1352 When set, REO shall drop this MSDU and not forward it to 1353 any other ring... 1354 1355 <legal all> 1356 */ 1357 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1358 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1359 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1360 1361 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1362 1363 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1364 over multiple buffers, this field will be valid in the Last 1365 buffer used by the MSDU 1366 1367 1368 1369 Indicates that OLE found a valid SA entry for this MSDU 1370 1371 <legal all> 1372 */ 1373 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1374 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1375 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1376 1377 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1378 1379 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1380 over multiple buffers, this field will be valid in the Last 1381 buffer used by the MSDU 1382 1383 1384 1385 Indicates an unsuccessful MAC source address search due 1386 to the expiring of the search timer for this MSDU 1387 1388 <legal all> 1389 */ 1390 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 1391 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1392 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1393 1394 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1395 1396 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1397 over multiple buffers, this field will be valid in the Last 1398 buffer used by the MSDU 1399 1400 1401 1402 Indicates that OLE found a valid DA entry for this MSDU 1403 1404 <legal all> 1405 */ 1406 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1407 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1408 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1409 1410 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1411 1412 Field Only valid if da_is_valid is set 1413 1414 1415 1416 Indicates the DA address was a Multicast of Broadcast 1417 address for this MSDU 1418 1419 <legal all> 1420 */ 1421 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1422 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1423 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1424 1425 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1426 1427 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1428 over multiple buffers, this field will be valid in the Last 1429 buffer used by the MSDU 1430 1431 1432 1433 Indicates an unsuccessful MAC destination address search 1434 due to the expiring of the search timer for this MSDU 1435 1436 <legal all> 1437 */ 1438 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 1439 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1440 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1441 1442 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1443 1444 <legal 0> 1445 */ 1446 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 1447 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1448 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1449 1450 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1451 1452 <legal 0> 1453 */ 1454 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000003c 1455 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1456 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1457 1458 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */ 1459 1460 1461 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1462 1463 1464 /* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1465 1466 Address (lower 32 bits) of the MSDU buffer OR 1467 MSDU_EXTENSION descriptor OR Link Descriptor 1468 1469 1470 1471 In case of 'NULL' pointer, this field is set to 0 1472 1473 <legal all> 1474 */ 1475 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1476 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1477 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1478 1479 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1480 1481 Address (upper 8 bits) of the MSDU buffer OR 1482 MSDU_EXTENSION descriptor OR Link Descriptor 1483 1484 1485 1486 In case of 'NULL' pointer, this field is set to 0 1487 1488 <legal all> 1489 */ 1490 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1491 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1492 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1493 1494 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1495 1496 Consumer: WBM 1497 1498 Producer: SW/FW 1499 1500 1501 1502 In case of 'NULL' pointer, this field is set to 0 1503 1504 1505 1506 Indicates to which buffer manager the buffer OR 1507 MSDU_EXTENSION descriptor OR link descriptor that is being 1508 pointed to shall be returned after the frame has been 1509 processed. It is used by WBM for routing purposes. 1510 1511 1512 1513 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1514 to the WMB buffer idle list 1515 1516 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1517 returned to the WMB idle link descriptor idle list 1518 1519 <enum 2 FW_BM> This buffer shall be returned to the FW 1520 1521 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1522 ring 0 1523 1524 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1525 ring 1 1526 1527 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1528 ring 2 1529 1530 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1531 ring 3 1532 1533 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1534 ring 4 1535 1536 1537 1538 <legal all> 1539 */ 1540 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1541 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1542 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1543 1544 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1545 1546 Cookie field exclusively used by SW. 1547 1548 1549 1550 In case of 'NULL' pointer, this field is set to 0 1551 1552 1553 1554 HW ignores the contents, accept that it passes the 1555 programmed value on to other descriptors together with the 1556 physical address 1557 1558 1559 1560 Field can be used by SW to for example associate the 1561 buffers physical address with the virtual address 1562 1563 The bit definitions as used by SW are within SW HLD 1564 specification 1565 1566 1567 1568 NOTE: 1569 1570 The three most significant bits can have a special 1571 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1572 STRUCT, and field transmit_bw_restriction is set 1573 1574 1575 1576 In case of NON punctured transmission: 1577 1578 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1579 1580 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1581 1582 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1583 1584 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1585 1586 1587 1588 In case of punctured transmission: 1589 1590 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1591 1592 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1593 1594 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1595 1596 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1597 1598 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1599 1600 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1601 1602 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1603 1604 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1605 1606 1607 1608 Note: a punctured transmission is indicated by the 1609 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1610 TLV 1611 1612 1613 1614 <legal all> 1615 */ 1616 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1617 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1618 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1619 1620 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1621 1622 1623 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1624 1625 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1626 over multiple buffers, this field will be valid in the Last 1627 buffer used by the MSDU 1628 1629 1630 1631 <enum 0 Not_first_msdu> This is not the first MSDU in 1632 the MPDU. 1633 1634 <enum 1 first_msdu> This MSDU is the first one in the 1635 MPDU. 1636 1637 1638 1639 <legal all> 1640 */ 1641 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1642 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1643 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1644 1645 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1646 1647 Consumer: WBM/REO/SW/FW 1648 1649 Producer: RXDMA 1650 1651 1652 1653 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1654 over multiple buffers, this field will be valid in the Last 1655 buffer used by the MSDU 1656 1657 1658 1659 <enum 0 Not_last_msdu> There are more MSDUs linked to 1660 this MSDU that belongs to this MPDU 1661 1662 <enum 1 Last_msdu> this MSDU is the last one in the 1663 MPDU. This setting is only allowed in combination with 1664 'Msdu_continuation' set to 0. This implies that when an msdu 1665 is spread out over multiple buffers and thus 1666 msdu_continuation is set, only for the very last buffer of 1667 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1668 1669 1670 1671 When both first_msdu_in_mpdu_flag and 1672 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1673 belongs to only contains a single MSDU. 1674 1675 1676 1677 1678 1679 <legal all> 1680 */ 1681 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1682 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1683 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1684 1685 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1686 1687 When set, this MSDU buffer was not able to hold the 1688 entire MSDU. The next buffer will therefor contain 1689 additional information related to this MSDU. 1690 1691 1692 1693 <legal all> 1694 */ 1695 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 1696 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1697 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1698 1699 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1700 1701 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1702 over multiple buffers, this field will be valid in the First 1703 buffer used by MSDU. 1704 1705 1706 1707 Full MSDU length in bytes after decapsulation. 1708 1709 1710 1711 This field is still valid for MPDU frames without 1712 A-MSDU. It still represents MSDU length after decapsulation 1713 1714 1715 1716 Or in case of RAW MPDUs, it indicates the length of the 1717 entire MPDU (without FCS field) 1718 1719 <legal all> 1720 */ 1721 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 1722 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1723 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1724 1725 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1726 1727 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1728 over multiple buffers, this field will be valid in the Last 1729 buffer used by the MSDU 1730 1731 1732 1733 The ID of the REO exit ring where the MSDU frame shall 1734 push after (MPDU level) reordering has finished. 1735 1736 1737 1738 <enum 0 reo_destination_tcl> Reo will push the frame 1739 into the REO2TCL ring 1740 1741 <enum 1 reo_destination_sw1> Reo will push the frame 1742 into the REO2SW1 ring 1743 1744 <enum 2 reo_destination_sw2> Reo will push the frame 1745 into the REO2SW2 ring 1746 1747 <enum 3 reo_destination_sw3> Reo will push the frame 1748 into the REO2SW3 ring 1749 1750 <enum 4 reo_destination_sw4> Reo will push the frame 1751 into the REO2SW4 ring 1752 1753 <enum 5 reo_destination_release> Reo will push the frame 1754 into the REO_release ring 1755 1756 <enum 6 reo_destination_fw> Reo will push the frame into 1757 the REO2FW ring 1758 1759 <enum 7 reo_destination_sw5> Reo will push the frame 1760 into the REO2SW5 ring 1761 1762 <enum 8 reo_destination_sw6> Reo will push the frame 1763 into the REO2SW6 ring 1764 1765 <enum 9 reo_destination_9> REO remaps this <enum 10 1766 reo_destination_10> REO remaps this 1767 1768 <enum 11 reo_destination_11> REO remaps this 1769 1770 <enum 12 reo_destination_12> REO remaps this <enum 13 1771 reo_destination_13> REO remaps this 1772 1773 <enum 14 reo_destination_14> REO remaps this 1774 1775 <enum 15 reo_destination_15> REO remaps this 1776 1777 <enum 16 reo_destination_16> REO remaps this 1778 1779 <enum 17 reo_destination_17> REO remaps this 1780 1781 <enum 18 reo_destination_18> REO remaps this 1782 1783 <enum 19 reo_destination_19> REO remaps this 1784 1785 <enum 20 reo_destination_20> REO remaps this 1786 1787 <enum 21 reo_destination_21> REO remaps this 1788 1789 <enum 22 reo_destination_22> REO remaps this 1790 1791 <enum 23 reo_destination_23> REO remaps this 1792 1793 <enum 24 reo_destination_24> REO remaps this 1794 1795 <enum 25 reo_destination_25> REO remaps this 1796 1797 <enum 26 reo_destination_26> REO remaps this 1798 1799 <enum 27 reo_destination_27> REO remaps this 1800 1801 <enum 28 reo_destination_28> REO remaps this 1802 1803 <enum 29 reo_destination_29> REO remaps this 1804 1805 <enum 30 reo_destination_30> REO remaps this 1806 1807 <enum 31 reo_destination_31> REO remaps this 1808 1809 1810 1811 <legal all> 1812 */ 1813 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 1814 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1815 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1816 1817 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1818 1819 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1820 over multiple buffers, this field will be valid in the Last 1821 buffer used by the MSDU 1822 1823 1824 1825 When set, REO shall drop this MSDU and not forward it to 1826 any other ring... 1827 1828 <legal all> 1829 */ 1830 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 1831 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1832 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1833 1834 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1835 1836 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1837 over multiple buffers, this field will be valid in the Last 1838 buffer used by the MSDU 1839 1840 1841 1842 Indicates that OLE found a valid SA entry for this MSDU 1843 1844 <legal all> 1845 */ 1846 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 1847 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1848 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1849 1850 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1851 1852 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1853 over multiple buffers, this field will be valid in the Last 1854 buffer used by the MSDU 1855 1856 1857 1858 Indicates an unsuccessful MAC source address search due 1859 to the expiring of the search timer for this MSDU 1860 1861 <legal all> 1862 */ 1863 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 1864 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1865 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1866 1867 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1868 1869 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1870 over multiple buffers, this field will be valid in the Last 1871 buffer used by the MSDU 1872 1873 1874 1875 Indicates that OLE found a valid DA entry for this MSDU 1876 1877 <legal all> 1878 */ 1879 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 1880 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1881 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1882 1883 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1884 1885 Field Only valid if da_is_valid is set 1886 1887 1888 1889 Indicates the DA address was a Multicast of Broadcast 1890 address for this MSDU 1891 1892 <legal all> 1893 */ 1894 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 1895 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1896 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1897 1898 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1899 1900 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1901 over multiple buffers, this field will be valid in the Last 1902 buffer used by the MSDU 1903 1904 1905 1906 Indicates an unsuccessful MAC destination address search 1907 due to the expiring of the search timer for this MSDU 1908 1909 <legal all> 1910 */ 1911 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 1912 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1913 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1914 1915 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1916 1917 <legal 0> 1918 */ 1919 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 1920 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1921 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1922 1923 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1924 1925 <legal 0> 1926 */ 1927 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000004c 1928 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1929 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1930 1931 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */ 1932 1933 1934 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1935 1936 1937 /* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1938 1939 Address (lower 32 bits) of the MSDU buffer OR 1940 MSDU_EXTENSION descriptor OR Link Descriptor 1941 1942 1943 1944 In case of 'NULL' pointer, this field is set to 0 1945 1946 <legal all> 1947 */ 1948 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 1949 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1950 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1951 1952 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1953 1954 Address (upper 8 bits) of the MSDU buffer OR 1955 MSDU_EXTENSION descriptor OR Link Descriptor 1956 1957 1958 1959 In case of 'NULL' pointer, this field is set to 0 1960 1961 <legal all> 1962 */ 1963 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 1964 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1965 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1966 1967 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1968 1969 Consumer: WBM 1970 1971 Producer: SW/FW 1972 1973 1974 1975 In case of 'NULL' pointer, this field is set to 0 1976 1977 1978 1979 Indicates to which buffer manager the buffer OR 1980 MSDU_EXTENSION descriptor OR link descriptor that is being 1981 pointed to shall be returned after the frame has been 1982 processed. It is used by WBM for routing purposes. 1983 1984 1985 1986 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1987 to the WMB buffer idle list 1988 1989 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1990 returned to the WMB idle link descriptor idle list 1991 1992 <enum 2 FW_BM> This buffer shall be returned to the FW 1993 1994 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1995 ring 0 1996 1997 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1998 ring 1 1999 2000 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2001 ring 2 2002 2003 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2004 ring 3 2005 2006 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2007 ring 4 2008 2009 2010 2011 <legal all> 2012 */ 2013 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2014 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2015 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2016 2017 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2018 2019 Cookie field exclusively used by SW. 2020 2021 2022 2023 In case of 'NULL' pointer, this field is set to 0 2024 2025 2026 2027 HW ignores the contents, accept that it passes the 2028 programmed value on to other descriptors together with the 2029 physical address 2030 2031 2032 2033 Field can be used by SW to for example associate the 2034 buffers physical address with the virtual address 2035 2036 The bit definitions as used by SW are within SW HLD 2037 specification 2038 2039 2040 2041 NOTE: 2042 2043 The three most significant bits can have a special 2044 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2045 STRUCT, and field transmit_bw_restriction is set 2046 2047 2048 2049 In case of NON punctured transmission: 2050 2051 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2052 2053 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2054 2055 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2056 2057 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2058 2059 2060 2061 In case of punctured transmission: 2062 2063 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2064 2065 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2066 2067 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2068 2069 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2070 2071 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2072 2073 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2074 2075 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2076 2077 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2078 2079 2080 2081 Note: a punctured transmission is indicated by the 2082 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2083 TLV 2084 2085 2086 2087 <legal all> 2088 */ 2089 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2090 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2091 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2092 2093 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2094 2095 2096 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2097 2098 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2099 over multiple buffers, this field will be valid in the Last 2100 buffer used by the MSDU 2101 2102 2103 2104 <enum 0 Not_first_msdu> This is not the first MSDU in 2105 the MPDU. 2106 2107 <enum 1 first_msdu> This MSDU is the first one in the 2108 MPDU. 2109 2110 2111 2112 <legal all> 2113 */ 2114 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2115 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2116 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2117 2118 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2119 2120 Consumer: WBM/REO/SW/FW 2121 2122 Producer: RXDMA 2123 2124 2125 2126 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2127 over multiple buffers, this field will be valid in the Last 2128 buffer used by the MSDU 2129 2130 2131 2132 <enum 0 Not_last_msdu> There are more MSDUs linked to 2133 this MSDU that belongs to this MPDU 2134 2135 <enum 1 Last_msdu> this MSDU is the last one in the 2136 MPDU. This setting is only allowed in combination with 2137 'Msdu_continuation' set to 0. This implies that when an msdu 2138 is spread out over multiple buffers and thus 2139 msdu_continuation is set, only for the very last buffer of 2140 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2141 2142 2143 2144 When both first_msdu_in_mpdu_flag and 2145 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2146 belongs to only contains a single MSDU. 2147 2148 2149 2150 2151 2152 <legal all> 2153 */ 2154 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2155 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2156 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2157 2158 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2159 2160 When set, this MSDU buffer was not able to hold the 2161 entire MSDU. The next buffer will therefor contain 2162 additional information related to this MSDU. 2163 2164 2165 2166 <legal all> 2167 */ 2168 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2169 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2170 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2171 2172 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2173 2174 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2175 over multiple buffers, this field will be valid in the First 2176 buffer used by MSDU. 2177 2178 2179 2180 Full MSDU length in bytes after decapsulation. 2181 2182 2183 2184 This field is still valid for MPDU frames without 2185 A-MSDU. It still represents MSDU length after decapsulation 2186 2187 2188 2189 Or in case of RAW MPDUs, it indicates the length of the 2190 entire MPDU (without FCS field) 2191 2192 <legal all> 2193 */ 2194 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2195 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2196 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2197 2198 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2199 2200 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2201 over multiple buffers, this field will be valid in the Last 2202 buffer used by the MSDU 2203 2204 2205 2206 The ID of the REO exit ring where the MSDU frame shall 2207 push after (MPDU level) reordering has finished. 2208 2209 2210 2211 <enum 0 reo_destination_tcl> Reo will push the frame 2212 into the REO2TCL ring 2213 2214 <enum 1 reo_destination_sw1> Reo will push the frame 2215 into the REO2SW1 ring 2216 2217 <enum 2 reo_destination_sw2> Reo will push the frame 2218 into the REO2SW2 ring 2219 2220 <enum 3 reo_destination_sw3> Reo will push the frame 2221 into the REO2SW3 ring 2222 2223 <enum 4 reo_destination_sw4> Reo will push the frame 2224 into the REO2SW4 ring 2225 2226 <enum 5 reo_destination_release> Reo will push the frame 2227 into the REO_release ring 2228 2229 <enum 6 reo_destination_fw> Reo will push the frame into 2230 the REO2FW ring 2231 2232 <enum 7 reo_destination_sw5> Reo will push the frame 2233 into the REO2SW5 ring 2234 2235 <enum 8 reo_destination_sw6> Reo will push the frame 2236 into the REO2SW6 ring 2237 2238 <enum 9 reo_destination_9> REO remaps this <enum 10 2239 reo_destination_10> REO remaps this 2240 2241 <enum 11 reo_destination_11> REO remaps this 2242 2243 <enum 12 reo_destination_12> REO remaps this <enum 13 2244 reo_destination_13> REO remaps this 2245 2246 <enum 14 reo_destination_14> REO remaps this 2247 2248 <enum 15 reo_destination_15> REO remaps this 2249 2250 <enum 16 reo_destination_16> REO remaps this 2251 2252 <enum 17 reo_destination_17> REO remaps this 2253 2254 <enum 18 reo_destination_18> REO remaps this 2255 2256 <enum 19 reo_destination_19> REO remaps this 2257 2258 <enum 20 reo_destination_20> REO remaps this 2259 2260 <enum 21 reo_destination_21> REO remaps this 2261 2262 <enum 22 reo_destination_22> REO remaps this 2263 2264 <enum 23 reo_destination_23> REO remaps this 2265 2266 <enum 24 reo_destination_24> REO remaps this 2267 2268 <enum 25 reo_destination_25> REO remaps this 2269 2270 <enum 26 reo_destination_26> REO remaps this 2271 2272 <enum 27 reo_destination_27> REO remaps this 2273 2274 <enum 28 reo_destination_28> REO remaps this 2275 2276 <enum 29 reo_destination_29> REO remaps this 2277 2278 <enum 30 reo_destination_30> REO remaps this 2279 2280 <enum 31 reo_destination_31> REO remaps this 2281 2282 2283 2284 <legal all> 2285 */ 2286 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 2287 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2288 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2289 2290 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2291 2292 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2293 over multiple buffers, this field will be valid in the Last 2294 buffer used by the MSDU 2295 2296 2297 2298 When set, REO shall drop this MSDU and not forward it to 2299 any other ring... 2300 2301 <legal all> 2302 */ 2303 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2304 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2305 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2306 2307 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2308 2309 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2310 over multiple buffers, this field will be valid in the Last 2311 buffer used by the MSDU 2312 2313 2314 2315 Indicates that OLE found a valid SA entry for this MSDU 2316 2317 <legal all> 2318 */ 2319 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2320 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2321 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2322 2323 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2324 2325 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2326 over multiple buffers, this field will be valid in the Last 2327 buffer used by the MSDU 2328 2329 2330 2331 Indicates an unsuccessful MAC source address search due 2332 to the expiring of the search timer for this MSDU 2333 2334 <legal all> 2335 */ 2336 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 2337 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2338 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2339 2340 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2341 2342 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2343 over multiple buffers, this field will be valid in the Last 2344 buffer used by the MSDU 2345 2346 2347 2348 Indicates that OLE found a valid DA entry for this MSDU 2349 2350 <legal all> 2351 */ 2352 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2353 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2354 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2355 2356 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2357 2358 Field Only valid if da_is_valid is set 2359 2360 2361 2362 Indicates the DA address was a Multicast of Broadcast 2363 address for this MSDU 2364 2365 <legal all> 2366 */ 2367 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2368 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2369 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2370 2371 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2372 2373 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2374 over multiple buffers, this field will be valid in the Last 2375 buffer used by the MSDU 2376 2377 2378 2379 Indicates an unsuccessful MAC destination address search 2380 due to the expiring of the search timer for this MSDU 2381 2382 <legal all> 2383 */ 2384 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 2385 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2386 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2387 2388 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2389 2390 <legal 0> 2391 */ 2392 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 2393 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2394 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2395 2396 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2397 2398 <legal 0> 2399 */ 2400 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000005c 2401 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2402 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2403 2404 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */ 2405 2406 2407 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2408 2409 2410 /* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2411 2412 Address (lower 32 bits) of the MSDU buffer OR 2413 MSDU_EXTENSION descriptor OR Link Descriptor 2414 2415 2416 2417 In case of 'NULL' pointer, this field is set to 0 2418 2419 <legal all> 2420 */ 2421 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 2422 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2423 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2424 2425 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2426 2427 Address (upper 8 bits) of the MSDU buffer OR 2428 MSDU_EXTENSION descriptor OR Link Descriptor 2429 2430 2431 2432 In case of 'NULL' pointer, this field is set to 0 2433 2434 <legal all> 2435 */ 2436 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 2437 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2438 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2439 2440 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2441 2442 Consumer: WBM 2443 2444 Producer: SW/FW 2445 2446 2447 2448 In case of 'NULL' pointer, this field is set to 0 2449 2450 2451 2452 Indicates to which buffer manager the buffer OR 2453 MSDU_EXTENSION descriptor OR link descriptor that is being 2454 pointed to shall be returned after the frame has been 2455 processed. It is used by WBM for routing purposes. 2456 2457 2458 2459 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2460 to the WMB buffer idle list 2461 2462 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2463 returned to the WMB idle link descriptor idle list 2464 2465 <enum 2 FW_BM> This buffer shall be returned to the FW 2466 2467 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2468 ring 0 2469 2470 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2471 ring 1 2472 2473 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2474 ring 2 2475 2476 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2477 ring 3 2478 2479 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2480 ring 4 2481 2482 2483 2484 <legal all> 2485 */ 2486 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2487 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2488 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2489 2490 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2491 2492 Cookie field exclusively used by SW. 2493 2494 2495 2496 In case of 'NULL' pointer, this field is set to 0 2497 2498 2499 2500 HW ignores the contents, accept that it passes the 2501 programmed value on to other descriptors together with the 2502 physical address 2503 2504 2505 2506 Field can be used by SW to for example associate the 2507 buffers physical address with the virtual address 2508 2509 The bit definitions as used by SW are within SW HLD 2510 specification 2511 2512 2513 2514 NOTE: 2515 2516 The three most significant bits can have a special 2517 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2518 STRUCT, and field transmit_bw_restriction is set 2519 2520 2521 2522 In case of NON punctured transmission: 2523 2524 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2525 2526 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2527 2528 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2529 2530 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2531 2532 2533 2534 In case of punctured transmission: 2535 2536 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2537 2538 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2539 2540 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2541 2542 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2543 2544 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2545 2546 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2547 2548 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2549 2550 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2551 2552 2553 2554 Note: a punctured transmission is indicated by the 2555 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2556 TLV 2557 2558 2559 2560 <legal all> 2561 */ 2562 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 2563 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2564 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2565 2566 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2567 2568 2569 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2570 2571 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2572 over multiple buffers, this field will be valid in the Last 2573 buffer used by the MSDU 2574 2575 2576 2577 <enum 0 Not_first_msdu> This is not the first MSDU in 2578 the MPDU. 2579 2580 <enum 1 first_msdu> This MSDU is the first one in the 2581 MPDU. 2582 2583 2584 2585 <legal all> 2586 */ 2587 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2588 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2589 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2590 2591 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2592 2593 Consumer: WBM/REO/SW/FW 2594 2595 Producer: RXDMA 2596 2597 2598 2599 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2600 over multiple buffers, this field will be valid in the Last 2601 buffer used by the MSDU 2602 2603 2604 2605 <enum 0 Not_last_msdu> There are more MSDUs linked to 2606 this MSDU that belongs to this MPDU 2607 2608 <enum 1 Last_msdu> this MSDU is the last one in the 2609 MPDU. This setting is only allowed in combination with 2610 'Msdu_continuation' set to 0. This implies that when an msdu 2611 is spread out over multiple buffers and thus 2612 msdu_continuation is set, only for the very last buffer of 2613 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2614 2615 2616 2617 When both first_msdu_in_mpdu_flag and 2618 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2619 belongs to only contains a single MSDU. 2620 2621 2622 2623 2624 2625 <legal all> 2626 */ 2627 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 2628 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2629 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2630 2631 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2632 2633 When set, this MSDU buffer was not able to hold the 2634 entire MSDU. The next buffer will therefor contain 2635 additional information related to this MSDU. 2636 2637 2638 2639 <legal all> 2640 */ 2641 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 2642 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2643 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2644 2645 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2646 2647 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2648 over multiple buffers, this field will be valid in the First 2649 buffer used by MSDU. 2650 2651 2652 2653 Full MSDU length in bytes after decapsulation. 2654 2655 2656 2657 This field is still valid for MPDU frames without 2658 A-MSDU. It still represents MSDU length after decapsulation 2659 2660 2661 2662 Or in case of RAW MPDUs, it indicates the length of the 2663 entire MPDU (without FCS field) 2664 2665 <legal all> 2666 */ 2667 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 2668 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2669 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2670 2671 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2672 2673 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2674 over multiple buffers, this field will be valid in the Last 2675 buffer used by the MSDU 2676 2677 2678 2679 The ID of the REO exit ring where the MSDU frame shall 2680 push after (MPDU level) reordering has finished. 2681 2682 2683 2684 <enum 0 reo_destination_tcl> Reo will push the frame 2685 into the REO2TCL ring 2686 2687 <enum 1 reo_destination_sw1> Reo will push the frame 2688 into the REO2SW1 ring 2689 2690 <enum 2 reo_destination_sw2> Reo will push the frame 2691 into the REO2SW2 ring 2692 2693 <enum 3 reo_destination_sw3> Reo will push the frame 2694 into the REO2SW3 ring 2695 2696 <enum 4 reo_destination_sw4> Reo will push the frame 2697 into the REO2SW4 ring 2698 2699 <enum 5 reo_destination_release> Reo will push the frame 2700 into the REO_release ring 2701 2702 <enum 6 reo_destination_fw> Reo will push the frame into 2703 the REO2FW ring 2704 2705 <enum 7 reo_destination_sw5> Reo will push the frame 2706 into the REO2SW5 ring 2707 2708 <enum 8 reo_destination_sw6> Reo will push the frame 2709 into the REO2SW6 ring 2710 2711 <enum 9 reo_destination_9> REO remaps this <enum 10 2712 reo_destination_10> REO remaps this 2713 2714 <enum 11 reo_destination_11> REO remaps this 2715 2716 <enum 12 reo_destination_12> REO remaps this <enum 13 2717 reo_destination_13> REO remaps this 2718 2719 <enum 14 reo_destination_14> REO remaps this 2720 2721 <enum 15 reo_destination_15> REO remaps this 2722 2723 <enum 16 reo_destination_16> REO remaps this 2724 2725 <enum 17 reo_destination_17> REO remaps this 2726 2727 <enum 18 reo_destination_18> REO remaps this 2728 2729 <enum 19 reo_destination_19> REO remaps this 2730 2731 <enum 20 reo_destination_20> REO remaps this 2732 2733 <enum 21 reo_destination_21> REO remaps this 2734 2735 <enum 22 reo_destination_22> REO remaps this 2736 2737 <enum 23 reo_destination_23> REO remaps this 2738 2739 <enum 24 reo_destination_24> REO remaps this 2740 2741 <enum 25 reo_destination_25> REO remaps this 2742 2743 <enum 26 reo_destination_26> REO remaps this 2744 2745 <enum 27 reo_destination_27> REO remaps this 2746 2747 <enum 28 reo_destination_28> REO remaps this 2748 2749 <enum 29 reo_destination_29> REO remaps this 2750 2751 <enum 30 reo_destination_30> REO remaps this 2752 2753 <enum 31 reo_destination_31> REO remaps this 2754 2755 2756 2757 <legal all> 2758 */ 2759 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 2760 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2761 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2762 2763 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2764 2765 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2766 over multiple buffers, this field will be valid in the Last 2767 buffer used by the MSDU 2768 2769 2770 2771 When set, REO shall drop this MSDU and not forward it to 2772 any other ring... 2773 2774 <legal all> 2775 */ 2776 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 2777 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2778 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2779 2780 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2781 2782 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2783 over multiple buffers, this field will be valid in the Last 2784 buffer used by the MSDU 2785 2786 2787 2788 Indicates that OLE found a valid SA entry for this MSDU 2789 2790 <legal all> 2791 */ 2792 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 2793 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2794 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2795 2796 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2797 2798 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2799 over multiple buffers, this field will be valid in the Last 2800 buffer used by the MSDU 2801 2802 2803 2804 Indicates an unsuccessful MAC source address search due 2805 to the expiring of the search timer for this MSDU 2806 2807 <legal all> 2808 */ 2809 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 2810 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2811 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2812 2813 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2814 2815 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2816 over multiple buffers, this field will be valid in the Last 2817 buffer used by the MSDU 2818 2819 2820 2821 Indicates that OLE found a valid DA entry for this MSDU 2822 2823 <legal all> 2824 */ 2825 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 2826 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2827 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2828 2829 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2830 2831 Field Only valid if da_is_valid is set 2832 2833 2834 2835 Indicates the DA address was a Multicast of Broadcast 2836 address for this MSDU 2837 2838 <legal all> 2839 */ 2840 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 2841 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2842 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2843 2844 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2845 2846 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2847 over multiple buffers, this field will be valid in the Last 2848 buffer used by the MSDU 2849 2850 2851 2852 Indicates an unsuccessful MAC destination address search 2853 due to the expiring of the search timer for this MSDU 2854 2855 <legal all> 2856 */ 2857 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 2858 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2859 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2860 2861 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 2862 2863 <legal 0> 2864 */ 2865 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 2866 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 2867 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 2868 2869 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 2870 2871 <legal 0> 2872 */ 2873 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000006c 2874 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 2875 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 2876 2877 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */ 2878 2879 2880 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2881 2882 2883 /* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2884 2885 Address (lower 32 bits) of the MSDU buffer OR 2886 MSDU_EXTENSION descriptor OR Link Descriptor 2887 2888 2889 2890 In case of 'NULL' pointer, this field is set to 0 2891 2892 <legal all> 2893 */ 2894 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 2895 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2896 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2897 2898 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2899 2900 Address (upper 8 bits) of the MSDU buffer OR 2901 MSDU_EXTENSION descriptor OR Link Descriptor 2902 2903 2904 2905 In case of 'NULL' pointer, this field is set to 0 2906 2907 <legal all> 2908 */ 2909 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 2910 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2911 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2912 2913 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2914 2915 Consumer: WBM 2916 2917 Producer: SW/FW 2918 2919 2920 2921 In case of 'NULL' pointer, this field is set to 0 2922 2923 2924 2925 Indicates to which buffer manager the buffer OR 2926 MSDU_EXTENSION descriptor OR link descriptor that is being 2927 pointed to shall be returned after the frame has been 2928 processed. It is used by WBM for routing purposes. 2929 2930 2931 2932 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2933 to the WMB buffer idle list 2934 2935 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2936 returned to the WMB idle link descriptor idle list 2937 2938 <enum 2 FW_BM> This buffer shall be returned to the FW 2939 2940 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2941 ring 0 2942 2943 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2944 ring 1 2945 2946 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2947 ring 2 2948 2949 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2950 ring 3 2951 2952 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2953 ring 4 2954 2955 2956 2957 <legal all> 2958 */ 2959 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2960 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2961 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2962 2963 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2964 2965 Cookie field exclusively used by SW. 2966 2967 2968 2969 In case of 'NULL' pointer, this field is set to 0 2970 2971 2972 2973 HW ignores the contents, accept that it passes the 2974 programmed value on to other descriptors together with the 2975 physical address 2976 2977 2978 2979 Field can be used by SW to for example associate the 2980 buffers physical address with the virtual address 2981 2982 The bit definitions as used by SW are within SW HLD 2983 specification 2984 2985 2986 2987 NOTE: 2988 2989 The three most significant bits can have a special 2990 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2991 STRUCT, and field transmit_bw_restriction is set 2992 2993 2994 2995 In case of NON punctured transmission: 2996 2997 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2998 2999 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3000 3001 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3002 3003 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3004 3005 3006 3007 In case of punctured transmission: 3008 3009 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3010 3011 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3012 3013 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3014 3015 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3016 3017 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3018 3019 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3020 3021 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3022 3023 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3024 3025 3026 3027 Note: a punctured transmission is indicated by the 3028 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3029 TLV 3030 3031 3032 3033 <legal all> 3034 */ 3035 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3036 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 3037 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 3038 3039 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 3040 3041 3042 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 3043 3044 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3045 over multiple buffers, this field will be valid in the Last 3046 buffer used by the MSDU 3047 3048 3049 3050 <enum 0 Not_first_msdu> This is not the first MSDU in 3051 the MPDU. 3052 3053 <enum 1 first_msdu> This MSDU is the first one in the 3054 MPDU. 3055 3056 3057 3058 <legal all> 3059 */ 3060 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3061 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3062 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3063 3064 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 3065 3066 Consumer: WBM/REO/SW/FW 3067 3068 Producer: RXDMA 3069 3070 3071 3072 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3073 over multiple buffers, this field will be valid in the Last 3074 buffer used by the MSDU 3075 3076 3077 3078 <enum 0 Not_last_msdu> There are more MSDUs linked to 3079 this MSDU that belongs to this MPDU 3080 3081 <enum 1 Last_msdu> this MSDU is the last one in the 3082 MPDU. This setting is only allowed in combination with 3083 'Msdu_continuation' set to 0. This implies that when an msdu 3084 is spread out over multiple buffers and thus 3085 msdu_continuation is set, only for the very last buffer of 3086 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 3087 3088 3089 3090 When both first_msdu_in_mpdu_flag and 3091 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 3092 belongs to only contains a single MSDU. 3093 3094 3095 3096 3097 3098 <legal all> 3099 */ 3100 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3101 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3102 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3103 3104 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 3105 3106 When set, this MSDU buffer was not able to hold the 3107 entire MSDU. The next buffer will therefor contain 3108 additional information related to this MSDU. 3109 3110 3111 3112 <legal all> 3113 */ 3114 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3115 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3116 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3117 3118 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 3119 3120 Parsed from RX_MSDU_START TLV . In the case MSDU spans 3121 over multiple buffers, this field will be valid in the First 3122 buffer used by MSDU. 3123 3124 3125 3126 Full MSDU length in bytes after decapsulation. 3127 3128 3129 3130 This field is still valid for MPDU frames without 3131 A-MSDU. It still represents MSDU length after decapsulation 3132 3133 3134 3135 Or in case of RAW MPDUs, it indicates the length of the 3136 entire MPDU (without FCS field) 3137 3138 <legal all> 3139 */ 3140 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3141 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3142 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3143 3144 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 3145 3146 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3147 over multiple buffers, this field will be valid in the Last 3148 buffer used by the MSDU 3149 3150 3151 3152 The ID of the REO exit ring where the MSDU frame shall 3153 push after (MPDU level) reordering has finished. 3154 3155 3156 3157 <enum 0 reo_destination_tcl> Reo will push the frame 3158 into the REO2TCL ring 3159 3160 <enum 1 reo_destination_sw1> Reo will push the frame 3161 into the REO2SW1 ring 3162 3163 <enum 2 reo_destination_sw2> Reo will push the frame 3164 into the REO2SW2 ring 3165 3166 <enum 3 reo_destination_sw3> Reo will push the frame 3167 into the REO2SW3 ring 3168 3169 <enum 4 reo_destination_sw4> Reo will push the frame 3170 into the REO2SW4 ring 3171 3172 <enum 5 reo_destination_release> Reo will push the frame 3173 into the REO_release ring 3174 3175 <enum 6 reo_destination_fw> Reo will push the frame into 3176 the REO2FW ring 3177 3178 <enum 7 reo_destination_sw5> Reo will push the frame 3179 into the REO2SW5 ring 3180 3181 <enum 8 reo_destination_sw6> Reo will push the frame 3182 into the REO2SW6 ring 3183 3184 <enum 9 reo_destination_9> REO remaps this <enum 10 3185 reo_destination_10> REO remaps this 3186 3187 <enum 11 reo_destination_11> REO remaps this 3188 3189 <enum 12 reo_destination_12> REO remaps this <enum 13 3190 reo_destination_13> REO remaps this 3191 3192 <enum 14 reo_destination_14> REO remaps this 3193 3194 <enum 15 reo_destination_15> REO remaps this 3195 3196 <enum 16 reo_destination_16> REO remaps this 3197 3198 <enum 17 reo_destination_17> REO remaps this 3199 3200 <enum 18 reo_destination_18> REO remaps this 3201 3202 <enum 19 reo_destination_19> REO remaps this 3203 3204 <enum 20 reo_destination_20> REO remaps this 3205 3206 <enum 21 reo_destination_21> REO remaps this 3207 3208 <enum 22 reo_destination_22> REO remaps this 3209 3210 <enum 23 reo_destination_23> REO remaps this 3211 3212 <enum 24 reo_destination_24> REO remaps this 3213 3214 <enum 25 reo_destination_25> REO remaps this 3215 3216 <enum 26 reo_destination_26> REO remaps this 3217 3218 <enum 27 reo_destination_27> REO remaps this 3219 3220 <enum 28 reo_destination_28> REO remaps this 3221 3222 <enum 29 reo_destination_29> REO remaps this 3223 3224 <enum 30 reo_destination_30> REO remaps this 3225 3226 <enum 31 reo_destination_31> REO remaps this 3227 3228 3229 3230 <legal all> 3231 */ 3232 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 3233 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 3234 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 3235 3236 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 3237 3238 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3239 over multiple buffers, this field will be valid in the Last 3240 buffer used by the MSDU 3241 3242 3243 3244 When set, REO shall drop this MSDU and not forward it to 3245 any other ring... 3246 3247 <legal all> 3248 */ 3249 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 3250 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 3251 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 3252 3253 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 3254 3255 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3256 over multiple buffers, this field will be valid in the Last 3257 buffer used by the MSDU 3258 3259 3260 3261 Indicates that OLE found a valid SA entry for this MSDU 3262 3263 <legal all> 3264 */ 3265 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 3266 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 3267 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 3268 3269 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 3270 3271 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3272 over multiple buffers, this field will be valid in the Last 3273 buffer used by the MSDU 3274 3275 3276 3277 Indicates an unsuccessful MAC source address search due 3278 to the expiring of the search timer for this MSDU 3279 3280 <legal all> 3281 */ 3282 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 3283 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 3284 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 3285 3286 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 3287 3288 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3289 over multiple buffers, this field will be valid in the Last 3290 buffer used by the MSDU 3291 3292 3293 3294 Indicates that OLE found a valid DA entry for this MSDU 3295 3296 <legal all> 3297 */ 3298 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 3299 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 3300 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 3301 3302 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 3303 3304 Field Only valid if da_is_valid is set 3305 3306 3307 3308 Indicates the DA address was a Multicast of Broadcast 3309 address for this MSDU 3310 3311 <legal all> 3312 */ 3313 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 3314 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 3315 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 3316 3317 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 3318 3319 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3320 over multiple buffers, this field will be valid in the Last 3321 buffer used by the MSDU 3322 3323 3324 3325 Indicates an unsuccessful MAC destination address search 3326 due to the expiring of the search timer for this MSDU 3327 3328 <legal all> 3329 */ 3330 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 3331 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 3332 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 3333 3334 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 3335 3336 <legal 0> 3337 */ 3338 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 3339 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 3340 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 3341 3342 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 3343 3344 <legal 0> 3345 */ 3346 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000007c 3347 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 3348 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 3349 3350 3351 #endif // _RX_MSDU_LINK_H_ 3352