1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_EXT_H_ 18 #define _RX_REO_QUEUE_EXT_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "rx_mpdu_link_ptr.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 struct uniform_descriptor_header descriptor_header; 29 // 1 reserved_1a[31:0] 30 // 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 31 // 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 32 // 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 33 // 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 34 // 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 35 // 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 36 // 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 37 // 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 38 // 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 39 // 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 40 // 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 41 // 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 42 // 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 43 // 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 44 // 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 45 // 46 // ################ END SUMMARY ################# 47 48 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 49 50 struct rx_reo_queue_ext { 51 struct uniform_descriptor_header descriptor_header; 52 uint32_t reserved_1a : 32; //[31:0] 53 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 54 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 55 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 56 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 57 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 58 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 59 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 60 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 64 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 65 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 66 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 67 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 68 }; 69 70 /* 71 72 struct uniform_descriptor_header descriptor_header 73 74 Details about which module owns this struct. 75 76 Note that sub field Buffer_type shall be set to 77 Receive_REO_queue_ext_descriptor 78 79 reserved_1a 80 81 <legal 0> 82 83 struct rx_mpdu_link_ptr mpdu_link_pointer_0 84 85 Consumer: REO 86 87 Producer: REO 88 89 90 91 Pointer to the next MPDU_link descriptor in the MPDU 92 queue 93 94 struct rx_mpdu_link_ptr mpdu_link_pointer_1 95 96 Consumer: REO 97 98 Producer: REO 99 100 101 102 Pointer to the next MPDU_link descriptor in the MPDU 103 queue 104 105 struct rx_mpdu_link_ptr mpdu_link_pointer_2 106 107 Consumer: REO 108 109 Producer: REO 110 111 112 113 Pointer to the next MPDU_link descriptor in the MPDU 114 queue 115 116 struct rx_mpdu_link_ptr mpdu_link_pointer_3 117 118 Consumer: REO 119 120 Producer: REO 121 122 123 124 Pointer to the next MPDU_link descriptor in the MPDU 125 queue 126 127 struct rx_mpdu_link_ptr mpdu_link_pointer_4 128 129 Consumer: REO 130 131 Producer: REO 132 133 134 135 Pointer to the next MPDU_link descriptor in the MPDU 136 queue 137 138 struct rx_mpdu_link_ptr mpdu_link_pointer_5 139 140 Consumer: REO 141 142 Producer: REO 143 144 145 146 Pointer to the next MPDU_link descriptor in the MPDU 147 queue 148 149 struct rx_mpdu_link_ptr mpdu_link_pointer_6 150 151 Consumer: REO 152 153 Producer: REO 154 155 156 157 Pointer to the next MPDU_link descriptor in the MPDU 158 queue 159 160 struct rx_mpdu_link_ptr mpdu_link_pointer_7 161 162 Consumer: REO 163 164 Producer: REO 165 166 167 168 Pointer to the next MPDU_link descriptor in the MPDU 169 queue 170 171 struct rx_mpdu_link_ptr mpdu_link_pointer_8 172 173 Consumer: REO 174 175 Producer: REO 176 177 178 179 Pointer to the next MPDU_link descriptor in the MPDU 180 queue 181 182 struct rx_mpdu_link_ptr mpdu_link_pointer_9 183 184 Consumer: REO 185 186 Producer: REO 187 188 189 190 Pointer to the next MPDU_link descriptor in the MPDU 191 queue 192 193 struct rx_mpdu_link_ptr mpdu_link_pointer_10 194 195 Consumer: REO 196 197 Producer: REO 198 199 200 201 Pointer to the next MPDU_link descriptor in the MPDU 202 queue 203 204 struct rx_mpdu_link_ptr mpdu_link_pointer_11 205 206 Consumer: REO 207 208 Producer: REO 209 210 211 212 Pointer to the next MPDU_link descriptor in the MPDU 213 queue 214 215 struct rx_mpdu_link_ptr mpdu_link_pointer_12 216 217 Consumer: REO 218 219 Producer: REO 220 221 222 223 Pointer to the next MPDU_link descriptor in the MPDU 224 queue 225 226 struct rx_mpdu_link_ptr mpdu_link_pointer_13 227 228 Consumer: REO 229 230 Producer: REO 231 232 233 234 Pointer to the next MPDU_link descriptor in the MPDU 235 queue 236 237 struct rx_mpdu_link_ptr mpdu_link_pointer_14 238 239 Consumer: REO 240 241 Producer: REO 242 243 244 245 Pointer to the next MPDU_link descriptor in the MPDU 246 queue 247 */ 248 249 250 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 251 252 253 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER 254 255 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 256 257 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 258 259 260 261 The owner of this data structure: 262 263 <enum 0 WBM_owned> Buffer Manager currently owns this 264 data structure. 265 266 <enum 1 SW_OR_FW_owned> Software of FW currently owns 267 this data structure. 268 269 <enum 2 TQM_owned> Transmit Queue Manager currently owns 270 this data structure. 271 272 <enum 3 RXDMA_owned> Receive DMA currently owns this 273 data structure. 274 275 <enum 4 REO_owned> Reorder currently owns this data 276 structure. 277 278 <enum 5 SWITCH_owned> SWITCH currently owns this data 279 structure. 280 281 282 283 <legal 0-5> 284 */ 285 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 286 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 287 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 288 289 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE 290 291 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 292 293 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 294 295 296 297 Field describing what contents format is of this 298 descriptor 299 300 301 302 <enum 0 Transmit_MSDU_Link_descriptor > 303 304 <enum 1 Transmit_MPDU_Link_descriptor > 305 306 <enum 2 Transmit_MPDU_Queue_head_descriptor> 307 308 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 309 310 <enum 4 Transmit_flow_descriptor> 311 312 <enum 5 Transmit_buffer > NOT TO BE USED: 313 314 315 316 <enum 6 Receive_MSDU_Link_descriptor > 317 318 <enum 7 Receive_MPDU_Link_descriptor > 319 320 <enum 8 Receive_REO_queue_descriptor > 321 322 <enum 9 Receive_REO_queue_ext_descriptor > 323 324 325 326 <enum 10 Receive_buffer > 327 328 329 330 <enum 11 Idle_link_list_entry> 331 332 333 334 <legal 0-11> 335 */ 336 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 337 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 338 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 339 340 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A 341 342 <legal 0> 343 */ 344 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 345 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 346 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 347 348 /* Description RX_REO_QUEUE_EXT_1_RESERVED_1A 349 350 <legal 0> 351 */ 352 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 353 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 354 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff 355 356 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */ 357 358 359 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 360 361 362 /* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 363 364 Address (lower 32 bits) of the MSDU buffer OR 365 MSDU_EXTENSION descriptor OR Link Descriptor 366 367 368 369 In case of 'NULL' pointer, this field is set to 0 370 371 <legal all> 372 */ 373 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 374 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 375 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 376 377 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 378 379 Address (upper 8 bits) of the MSDU buffer OR 380 MSDU_EXTENSION descriptor OR Link Descriptor 381 382 383 384 In case of 'NULL' pointer, this field is set to 0 385 386 <legal all> 387 */ 388 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 389 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 390 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 391 392 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 393 394 Consumer: WBM 395 396 Producer: SW/FW 397 398 399 400 In case of 'NULL' pointer, this field is set to 0 401 402 403 404 Indicates to which buffer manager the buffer OR 405 MSDU_EXTENSION descriptor OR link descriptor that is being 406 pointed to shall be returned after the frame has been 407 processed. It is used by WBM for routing purposes. 408 409 410 411 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 412 to the WMB buffer idle list 413 414 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 415 returned to the WMB idle link descriptor idle list 416 417 <enum 2 FW_BM> This buffer shall be returned to the FW 418 419 <enum 3 SW0_BM> This buffer shall be returned to the SW, 420 ring 0 421 422 <enum 4 SW1_BM> This buffer shall be returned to the SW, 423 ring 1 424 425 <enum 5 SW2_BM> This buffer shall be returned to the SW, 426 ring 2 427 428 <enum 6 SW3_BM> This buffer shall be returned to the SW, 429 ring 3 430 431 <enum 7 SW4_BM> This buffer shall be returned to the SW, 432 ring 4 433 434 435 436 <legal all> 437 */ 438 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 439 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 440 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 441 442 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 443 444 Cookie field exclusively used by SW. 445 446 447 448 In case of 'NULL' pointer, this field is set to 0 449 450 451 452 HW ignores the contents, accept that it passes the 453 programmed value on to other descriptors together with the 454 physical address 455 456 457 458 Field can be used by SW to for example associate the 459 buffers physical address with the virtual address 460 461 The bit definitions as used by SW are within SW HLD 462 specification 463 464 465 466 NOTE: 467 468 The three most significant bits can have a special 469 meaning in case this struct is embedded in a TX_MPDU_DETAILS 470 STRUCT, and field transmit_bw_restriction is set 471 472 473 474 In case of NON punctured transmission: 475 476 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 477 478 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 479 480 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 481 482 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 483 484 485 486 In case of punctured transmission: 487 488 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 489 490 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 491 492 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 493 494 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 495 496 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 497 498 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 499 500 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 501 502 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 503 504 505 506 Note: a punctured transmission is indicated by the 507 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 508 TLV 509 510 511 512 <legal all> 513 */ 514 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 515 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 516 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 517 518 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */ 519 520 521 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 522 523 524 /* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 525 526 Address (lower 32 bits) of the MSDU buffer OR 527 MSDU_EXTENSION descriptor OR Link Descriptor 528 529 530 531 In case of 'NULL' pointer, this field is set to 0 532 533 <legal all> 534 */ 535 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 536 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 537 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 538 539 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 540 541 Address (upper 8 bits) of the MSDU buffer OR 542 MSDU_EXTENSION descriptor OR Link Descriptor 543 544 545 546 In case of 'NULL' pointer, this field is set to 0 547 548 <legal all> 549 */ 550 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 551 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 552 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 553 554 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 555 556 Consumer: WBM 557 558 Producer: SW/FW 559 560 561 562 In case of 'NULL' pointer, this field is set to 0 563 564 565 566 Indicates to which buffer manager the buffer OR 567 MSDU_EXTENSION descriptor OR link descriptor that is being 568 pointed to shall be returned after the frame has been 569 processed. It is used by WBM for routing purposes. 570 571 572 573 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 574 to the WMB buffer idle list 575 576 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 577 returned to the WMB idle link descriptor idle list 578 579 <enum 2 FW_BM> This buffer shall be returned to the FW 580 581 <enum 3 SW0_BM> This buffer shall be returned to the SW, 582 ring 0 583 584 <enum 4 SW1_BM> This buffer shall be returned to the SW, 585 ring 1 586 587 <enum 5 SW2_BM> This buffer shall be returned to the SW, 588 ring 2 589 590 <enum 6 SW3_BM> This buffer shall be returned to the SW, 591 ring 3 592 593 <enum 7 SW4_BM> This buffer shall be returned to the SW, 594 ring 4 595 596 597 598 <legal all> 599 */ 600 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 601 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 602 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 603 604 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 605 606 Cookie field exclusively used by SW. 607 608 609 610 In case of 'NULL' pointer, this field is set to 0 611 612 613 614 HW ignores the contents, accept that it passes the 615 programmed value on to other descriptors together with the 616 physical address 617 618 619 620 Field can be used by SW to for example associate the 621 buffers physical address with the virtual address 622 623 The bit definitions as used by SW are within SW HLD 624 specification 625 626 627 628 NOTE: 629 630 The three most significant bits can have a special 631 meaning in case this struct is embedded in a TX_MPDU_DETAILS 632 STRUCT, and field transmit_bw_restriction is set 633 634 635 636 In case of NON punctured transmission: 637 638 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 639 640 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 641 642 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 643 644 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 645 646 647 648 In case of punctured transmission: 649 650 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 651 652 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 653 654 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 655 656 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 657 658 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 659 660 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 661 662 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 663 664 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 665 666 667 668 Note: a punctured transmission is indicated by the 669 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 670 TLV 671 672 673 674 <legal all> 675 */ 676 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 677 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 678 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 679 680 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */ 681 682 683 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 684 685 686 /* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 687 688 Address (lower 32 bits) of the MSDU buffer OR 689 MSDU_EXTENSION descriptor OR Link Descriptor 690 691 692 693 In case of 'NULL' pointer, this field is set to 0 694 695 <legal all> 696 */ 697 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 698 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 699 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 700 701 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 702 703 Address (upper 8 bits) of the MSDU buffer OR 704 MSDU_EXTENSION descriptor OR Link Descriptor 705 706 707 708 In case of 'NULL' pointer, this field is set to 0 709 710 <legal all> 711 */ 712 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 713 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 714 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 715 716 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 717 718 Consumer: WBM 719 720 Producer: SW/FW 721 722 723 724 In case of 'NULL' pointer, this field is set to 0 725 726 727 728 Indicates to which buffer manager the buffer OR 729 MSDU_EXTENSION descriptor OR link descriptor that is being 730 pointed to shall be returned after the frame has been 731 processed. It is used by WBM for routing purposes. 732 733 734 735 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 736 to the WMB buffer idle list 737 738 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 739 returned to the WMB idle link descriptor idle list 740 741 <enum 2 FW_BM> This buffer shall be returned to the FW 742 743 <enum 3 SW0_BM> This buffer shall be returned to the SW, 744 ring 0 745 746 <enum 4 SW1_BM> This buffer shall be returned to the SW, 747 ring 1 748 749 <enum 5 SW2_BM> This buffer shall be returned to the SW, 750 ring 2 751 752 <enum 6 SW3_BM> This buffer shall be returned to the SW, 753 ring 3 754 755 <enum 7 SW4_BM> This buffer shall be returned to the SW, 756 ring 4 757 758 759 760 <legal all> 761 */ 762 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 763 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 764 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 765 766 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 767 768 Cookie field exclusively used by SW. 769 770 771 772 In case of 'NULL' pointer, this field is set to 0 773 774 775 776 HW ignores the contents, accept that it passes the 777 programmed value on to other descriptors together with the 778 physical address 779 780 781 782 Field can be used by SW to for example associate the 783 buffers physical address with the virtual address 784 785 The bit definitions as used by SW are within SW HLD 786 specification 787 788 789 790 NOTE: 791 792 The three most significant bits can have a special 793 meaning in case this struct is embedded in a TX_MPDU_DETAILS 794 STRUCT, and field transmit_bw_restriction is set 795 796 797 798 In case of NON punctured transmission: 799 800 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 801 802 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 803 804 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 805 806 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 807 808 809 810 In case of punctured transmission: 811 812 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 813 814 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 815 816 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 817 818 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 819 820 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 821 822 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 823 824 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 825 826 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 827 828 829 830 Note: a punctured transmission is indicated by the 831 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 832 TLV 833 834 835 836 <legal all> 837 */ 838 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 839 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 840 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 841 842 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */ 843 844 845 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 846 847 848 /* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 849 850 Address (lower 32 bits) of the MSDU buffer OR 851 MSDU_EXTENSION descriptor OR Link Descriptor 852 853 854 855 In case of 'NULL' pointer, this field is set to 0 856 857 <legal all> 858 */ 859 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 860 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 861 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 862 863 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 864 865 Address (upper 8 bits) of the MSDU buffer OR 866 MSDU_EXTENSION descriptor OR Link Descriptor 867 868 869 870 In case of 'NULL' pointer, this field is set to 0 871 872 <legal all> 873 */ 874 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 875 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 876 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 877 878 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 879 880 Consumer: WBM 881 882 Producer: SW/FW 883 884 885 886 In case of 'NULL' pointer, this field is set to 0 887 888 889 890 Indicates to which buffer manager the buffer OR 891 MSDU_EXTENSION descriptor OR link descriptor that is being 892 pointed to shall be returned after the frame has been 893 processed. It is used by WBM for routing purposes. 894 895 896 897 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 898 to the WMB buffer idle list 899 900 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 901 returned to the WMB idle link descriptor idle list 902 903 <enum 2 FW_BM> This buffer shall be returned to the FW 904 905 <enum 3 SW0_BM> This buffer shall be returned to the SW, 906 ring 0 907 908 <enum 4 SW1_BM> This buffer shall be returned to the SW, 909 ring 1 910 911 <enum 5 SW2_BM> This buffer shall be returned to the SW, 912 ring 2 913 914 <enum 6 SW3_BM> This buffer shall be returned to the SW, 915 ring 3 916 917 <enum 7 SW4_BM> This buffer shall be returned to the SW, 918 ring 4 919 920 921 922 <legal all> 923 */ 924 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 925 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 926 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 927 928 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 929 930 Cookie field exclusively used by SW. 931 932 933 934 In case of 'NULL' pointer, this field is set to 0 935 936 937 938 HW ignores the contents, accept that it passes the 939 programmed value on to other descriptors together with the 940 physical address 941 942 943 944 Field can be used by SW to for example associate the 945 buffers physical address with the virtual address 946 947 The bit definitions as used by SW are within SW HLD 948 specification 949 950 951 952 NOTE: 953 954 The three most significant bits can have a special 955 meaning in case this struct is embedded in a TX_MPDU_DETAILS 956 STRUCT, and field transmit_bw_restriction is set 957 958 959 960 In case of NON punctured transmission: 961 962 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 963 964 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 965 966 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 967 968 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 969 970 971 972 In case of punctured transmission: 973 974 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 975 976 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 977 978 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 979 980 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 981 982 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 983 984 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 985 986 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 987 988 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 989 990 991 992 Note: a punctured transmission is indicated by the 993 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 994 TLV 995 996 997 998 <legal all> 999 */ 1000 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 1001 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1002 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1003 1004 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */ 1005 1006 1007 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1008 1009 1010 /* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1011 1012 Address (lower 32 bits) of the MSDU buffer OR 1013 MSDU_EXTENSION descriptor OR Link Descriptor 1014 1015 1016 1017 In case of 'NULL' pointer, this field is set to 0 1018 1019 <legal all> 1020 */ 1021 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 1022 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1023 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1024 1025 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1026 1027 Address (upper 8 bits) of the MSDU buffer OR 1028 MSDU_EXTENSION descriptor OR Link Descriptor 1029 1030 1031 1032 In case of 'NULL' pointer, this field is set to 0 1033 1034 <legal all> 1035 */ 1036 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 1037 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1038 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1039 1040 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1041 1042 Consumer: WBM 1043 1044 Producer: SW/FW 1045 1046 1047 1048 In case of 'NULL' pointer, this field is set to 0 1049 1050 1051 1052 Indicates to which buffer manager the buffer OR 1053 MSDU_EXTENSION descriptor OR link descriptor that is being 1054 pointed to shall be returned after the frame has been 1055 processed. It is used by WBM for routing purposes. 1056 1057 1058 1059 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1060 to the WMB buffer idle list 1061 1062 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1063 returned to the WMB idle link descriptor idle list 1064 1065 <enum 2 FW_BM> This buffer shall be returned to the FW 1066 1067 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1068 ring 0 1069 1070 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1071 ring 1 1072 1073 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1074 ring 2 1075 1076 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1077 ring 3 1078 1079 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1080 ring 4 1081 1082 1083 1084 <legal all> 1085 */ 1086 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 1087 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1088 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1089 1090 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1091 1092 Cookie field exclusively used by SW. 1093 1094 1095 1096 In case of 'NULL' pointer, this field is set to 0 1097 1098 1099 1100 HW ignores the contents, accept that it passes the 1101 programmed value on to other descriptors together with the 1102 physical address 1103 1104 1105 1106 Field can be used by SW to for example associate the 1107 buffers physical address with the virtual address 1108 1109 The bit definitions as used by SW are within SW HLD 1110 specification 1111 1112 1113 1114 NOTE: 1115 1116 The three most significant bits can have a special 1117 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1118 STRUCT, and field transmit_bw_restriction is set 1119 1120 1121 1122 In case of NON punctured transmission: 1123 1124 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1125 1126 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1127 1128 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1129 1130 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1131 1132 1133 1134 In case of punctured transmission: 1135 1136 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1137 1138 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1139 1140 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1141 1142 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1143 1144 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1145 1146 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1147 1148 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1149 1150 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1151 1152 1153 1154 Note: a punctured transmission is indicated by the 1155 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1156 TLV 1157 1158 1159 1160 <legal all> 1161 */ 1162 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 1163 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1164 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1165 1166 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */ 1167 1168 1169 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1170 1171 1172 /* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1173 1174 Address (lower 32 bits) of the MSDU buffer OR 1175 MSDU_EXTENSION descriptor OR Link Descriptor 1176 1177 1178 1179 In case of 'NULL' pointer, this field is set to 0 1180 1181 <legal all> 1182 */ 1183 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 1184 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1185 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1186 1187 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1188 1189 Address (upper 8 bits) of the MSDU buffer OR 1190 MSDU_EXTENSION descriptor OR Link Descriptor 1191 1192 1193 1194 In case of 'NULL' pointer, this field is set to 0 1195 1196 <legal all> 1197 */ 1198 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 1199 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1200 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1201 1202 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1203 1204 Consumer: WBM 1205 1206 Producer: SW/FW 1207 1208 1209 1210 In case of 'NULL' pointer, this field is set to 0 1211 1212 1213 1214 Indicates to which buffer manager the buffer OR 1215 MSDU_EXTENSION descriptor OR link descriptor that is being 1216 pointed to shall be returned after the frame has been 1217 processed. It is used by WBM for routing purposes. 1218 1219 1220 1221 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1222 to the WMB buffer idle list 1223 1224 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1225 returned to the WMB idle link descriptor idle list 1226 1227 <enum 2 FW_BM> This buffer shall be returned to the FW 1228 1229 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1230 ring 0 1231 1232 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1233 ring 1 1234 1235 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1236 ring 2 1237 1238 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1239 ring 3 1240 1241 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1242 ring 4 1243 1244 1245 1246 <legal all> 1247 */ 1248 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1249 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1250 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1251 1252 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1253 1254 Cookie field exclusively used by SW. 1255 1256 1257 1258 In case of 'NULL' pointer, this field is set to 0 1259 1260 1261 1262 HW ignores the contents, accept that it passes the 1263 programmed value on to other descriptors together with the 1264 physical address 1265 1266 1267 1268 Field can be used by SW to for example associate the 1269 buffers physical address with the virtual address 1270 1271 The bit definitions as used by SW are within SW HLD 1272 specification 1273 1274 1275 1276 NOTE: 1277 1278 The three most significant bits can have a special 1279 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1280 STRUCT, and field transmit_bw_restriction is set 1281 1282 1283 1284 In case of NON punctured transmission: 1285 1286 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1287 1288 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1289 1290 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1291 1292 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1293 1294 1295 1296 In case of punctured transmission: 1297 1298 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1299 1300 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1301 1302 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1303 1304 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1305 1306 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1307 1308 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1309 1310 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1311 1312 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1313 1314 1315 1316 Note: a punctured transmission is indicated by the 1317 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1318 TLV 1319 1320 1321 1322 <legal all> 1323 */ 1324 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1325 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1326 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1327 1328 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */ 1329 1330 1331 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1332 1333 1334 /* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1335 1336 Address (lower 32 bits) of the MSDU buffer OR 1337 MSDU_EXTENSION descriptor OR Link Descriptor 1338 1339 1340 1341 In case of 'NULL' pointer, this field is set to 0 1342 1343 <legal all> 1344 */ 1345 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1346 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1347 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1348 1349 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1350 1351 Address (upper 8 bits) of the MSDU buffer OR 1352 MSDU_EXTENSION descriptor OR Link Descriptor 1353 1354 1355 1356 In case of 'NULL' pointer, this field is set to 0 1357 1358 <legal all> 1359 */ 1360 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1361 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1362 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1363 1364 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1365 1366 Consumer: WBM 1367 1368 Producer: SW/FW 1369 1370 1371 1372 In case of 'NULL' pointer, this field is set to 0 1373 1374 1375 1376 Indicates to which buffer manager the buffer OR 1377 MSDU_EXTENSION descriptor OR link descriptor that is being 1378 pointed to shall be returned after the frame has been 1379 processed. It is used by WBM for routing purposes. 1380 1381 1382 1383 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1384 to the WMB buffer idle list 1385 1386 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1387 returned to the WMB idle link descriptor idle list 1388 1389 <enum 2 FW_BM> This buffer shall be returned to the FW 1390 1391 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1392 ring 0 1393 1394 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1395 ring 1 1396 1397 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1398 ring 2 1399 1400 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1401 ring 3 1402 1403 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1404 ring 4 1405 1406 1407 1408 <legal all> 1409 */ 1410 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1411 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1412 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1413 1414 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1415 1416 Cookie field exclusively used by SW. 1417 1418 1419 1420 In case of 'NULL' pointer, this field is set to 0 1421 1422 1423 1424 HW ignores the contents, accept that it passes the 1425 programmed value on to other descriptors together with the 1426 physical address 1427 1428 1429 1430 Field can be used by SW to for example associate the 1431 buffers physical address with the virtual address 1432 1433 The bit definitions as used by SW are within SW HLD 1434 specification 1435 1436 1437 1438 NOTE: 1439 1440 The three most significant bits can have a special 1441 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1442 STRUCT, and field transmit_bw_restriction is set 1443 1444 1445 1446 In case of NON punctured transmission: 1447 1448 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1449 1450 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1451 1452 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1453 1454 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1455 1456 1457 1458 In case of punctured transmission: 1459 1460 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1461 1462 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1463 1464 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1465 1466 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1467 1468 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1469 1470 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1471 1472 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1473 1474 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1475 1476 1477 1478 Note: a punctured transmission is indicated by the 1479 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1480 TLV 1481 1482 1483 1484 <legal all> 1485 */ 1486 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1487 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1488 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1489 1490 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */ 1491 1492 1493 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1494 1495 1496 /* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1497 1498 Address (lower 32 bits) of the MSDU buffer OR 1499 MSDU_EXTENSION descriptor OR Link Descriptor 1500 1501 1502 1503 In case of 'NULL' pointer, this field is set to 0 1504 1505 <legal all> 1506 */ 1507 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1508 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1509 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1510 1511 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1512 1513 Address (upper 8 bits) of the MSDU buffer OR 1514 MSDU_EXTENSION descriptor OR Link Descriptor 1515 1516 1517 1518 In case of 'NULL' pointer, this field is set to 0 1519 1520 <legal all> 1521 */ 1522 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1523 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1524 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1525 1526 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1527 1528 Consumer: WBM 1529 1530 Producer: SW/FW 1531 1532 1533 1534 In case of 'NULL' pointer, this field is set to 0 1535 1536 1537 1538 Indicates to which buffer manager the buffer OR 1539 MSDU_EXTENSION descriptor OR link descriptor that is being 1540 pointed to shall be returned after the frame has been 1541 processed. It is used by WBM for routing purposes. 1542 1543 1544 1545 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1546 to the WMB buffer idle list 1547 1548 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1549 returned to the WMB idle link descriptor idle list 1550 1551 <enum 2 FW_BM> This buffer shall be returned to the FW 1552 1553 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1554 ring 0 1555 1556 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1557 ring 1 1558 1559 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1560 ring 2 1561 1562 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1563 ring 3 1564 1565 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1566 ring 4 1567 1568 1569 1570 <legal all> 1571 */ 1572 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1573 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1574 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1575 1576 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1577 1578 Cookie field exclusively used by SW. 1579 1580 1581 1582 In case of 'NULL' pointer, this field is set to 0 1583 1584 1585 1586 HW ignores the contents, accept that it passes the 1587 programmed value on to other descriptors together with the 1588 physical address 1589 1590 1591 1592 Field can be used by SW to for example associate the 1593 buffers physical address with the virtual address 1594 1595 The bit definitions as used by SW are within SW HLD 1596 specification 1597 1598 1599 1600 NOTE: 1601 1602 The three most significant bits can have a special 1603 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1604 STRUCT, and field transmit_bw_restriction is set 1605 1606 1607 1608 In case of NON punctured transmission: 1609 1610 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1611 1612 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1613 1614 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1615 1616 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1617 1618 1619 1620 In case of punctured transmission: 1621 1622 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1623 1624 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1625 1626 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1627 1628 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1629 1630 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1631 1632 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1633 1634 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1635 1636 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1637 1638 1639 1640 Note: a punctured transmission is indicated by the 1641 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1642 TLV 1643 1644 1645 1646 <legal all> 1647 */ 1648 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1649 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1650 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1651 1652 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */ 1653 1654 1655 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1656 1657 1658 /* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1659 1660 Address (lower 32 bits) of the MSDU buffer OR 1661 MSDU_EXTENSION descriptor OR Link Descriptor 1662 1663 1664 1665 In case of 'NULL' pointer, this field is set to 0 1666 1667 <legal all> 1668 */ 1669 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1670 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1671 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1672 1673 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1674 1675 Address (upper 8 bits) of the MSDU buffer OR 1676 MSDU_EXTENSION descriptor OR Link Descriptor 1677 1678 1679 1680 In case of 'NULL' pointer, this field is set to 0 1681 1682 <legal all> 1683 */ 1684 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1685 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1686 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1687 1688 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1689 1690 Consumer: WBM 1691 1692 Producer: SW/FW 1693 1694 1695 1696 In case of 'NULL' pointer, this field is set to 0 1697 1698 1699 1700 Indicates to which buffer manager the buffer OR 1701 MSDU_EXTENSION descriptor OR link descriptor that is being 1702 pointed to shall be returned after the frame has been 1703 processed. It is used by WBM for routing purposes. 1704 1705 1706 1707 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1708 to the WMB buffer idle list 1709 1710 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1711 returned to the WMB idle link descriptor idle list 1712 1713 <enum 2 FW_BM> This buffer shall be returned to the FW 1714 1715 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1716 ring 0 1717 1718 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1719 ring 1 1720 1721 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1722 ring 2 1723 1724 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1725 ring 3 1726 1727 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1728 ring 4 1729 1730 1731 1732 <legal all> 1733 */ 1734 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1735 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1736 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1737 1738 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1739 1740 Cookie field exclusively used by SW. 1741 1742 1743 1744 In case of 'NULL' pointer, this field is set to 0 1745 1746 1747 1748 HW ignores the contents, accept that it passes the 1749 programmed value on to other descriptors together with the 1750 physical address 1751 1752 1753 1754 Field can be used by SW to for example associate the 1755 buffers physical address with the virtual address 1756 1757 The bit definitions as used by SW are within SW HLD 1758 specification 1759 1760 1761 1762 NOTE: 1763 1764 The three most significant bits can have a special 1765 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1766 STRUCT, and field transmit_bw_restriction is set 1767 1768 1769 1770 In case of NON punctured transmission: 1771 1772 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1773 1774 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1775 1776 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1777 1778 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1779 1780 1781 1782 In case of punctured transmission: 1783 1784 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1785 1786 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1787 1788 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1789 1790 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1791 1792 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1793 1794 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1795 1796 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1797 1798 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1799 1800 1801 1802 Note: a punctured transmission is indicated by the 1803 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1804 TLV 1805 1806 1807 1808 <legal all> 1809 */ 1810 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1811 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1812 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1813 1814 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */ 1815 1816 1817 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1818 1819 1820 /* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1821 1822 Address (lower 32 bits) of the MSDU buffer OR 1823 MSDU_EXTENSION descriptor OR Link Descriptor 1824 1825 1826 1827 In case of 'NULL' pointer, this field is set to 0 1828 1829 <legal all> 1830 */ 1831 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1832 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1833 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1834 1835 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1836 1837 Address (upper 8 bits) of the MSDU buffer OR 1838 MSDU_EXTENSION descriptor OR Link Descriptor 1839 1840 1841 1842 In case of 'NULL' pointer, this field is set to 0 1843 1844 <legal all> 1845 */ 1846 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1847 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1848 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1849 1850 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1851 1852 Consumer: WBM 1853 1854 Producer: SW/FW 1855 1856 1857 1858 In case of 'NULL' pointer, this field is set to 0 1859 1860 1861 1862 Indicates to which buffer manager the buffer OR 1863 MSDU_EXTENSION descriptor OR link descriptor that is being 1864 pointed to shall be returned after the frame has been 1865 processed. It is used by WBM for routing purposes. 1866 1867 1868 1869 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1870 to the WMB buffer idle list 1871 1872 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1873 returned to the WMB idle link descriptor idle list 1874 1875 <enum 2 FW_BM> This buffer shall be returned to the FW 1876 1877 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1878 ring 0 1879 1880 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1881 ring 1 1882 1883 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1884 ring 2 1885 1886 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1887 ring 3 1888 1889 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1890 ring 4 1891 1892 1893 1894 <legal all> 1895 */ 1896 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1897 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1898 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1899 1900 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1901 1902 Cookie field exclusively used by SW. 1903 1904 1905 1906 In case of 'NULL' pointer, this field is set to 0 1907 1908 1909 1910 HW ignores the contents, accept that it passes the 1911 programmed value on to other descriptors together with the 1912 physical address 1913 1914 1915 1916 Field can be used by SW to for example associate the 1917 buffers physical address with the virtual address 1918 1919 The bit definitions as used by SW are within SW HLD 1920 specification 1921 1922 1923 1924 NOTE: 1925 1926 The three most significant bits can have a special 1927 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1928 STRUCT, and field transmit_bw_restriction is set 1929 1930 1931 1932 In case of NON punctured transmission: 1933 1934 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1935 1936 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1937 1938 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1939 1940 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1941 1942 1943 1944 In case of punctured transmission: 1945 1946 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1947 1948 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1949 1950 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1951 1952 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1953 1954 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1955 1956 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1957 1958 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1959 1960 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1961 1962 1963 1964 Note: a punctured transmission is indicated by the 1965 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1966 TLV 1967 1968 1969 1970 <legal all> 1971 */ 1972 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1973 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1974 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1975 1976 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */ 1977 1978 1979 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1980 1981 1982 /* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1983 1984 Address (lower 32 bits) of the MSDU buffer OR 1985 MSDU_EXTENSION descriptor OR Link Descriptor 1986 1987 1988 1989 In case of 'NULL' pointer, this field is set to 0 1990 1991 <legal all> 1992 */ 1993 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 1994 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1995 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1996 1997 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1998 1999 Address (upper 8 bits) of the MSDU buffer OR 2000 MSDU_EXTENSION descriptor OR Link Descriptor 2001 2002 2003 2004 In case of 'NULL' pointer, this field is set to 0 2005 2006 <legal all> 2007 */ 2008 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 2009 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2010 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2011 2012 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2013 2014 Consumer: WBM 2015 2016 Producer: SW/FW 2017 2018 2019 2020 In case of 'NULL' pointer, this field is set to 0 2021 2022 2023 2024 Indicates to which buffer manager the buffer OR 2025 MSDU_EXTENSION descriptor OR link descriptor that is being 2026 pointed to shall be returned after the frame has been 2027 processed. It is used by WBM for routing purposes. 2028 2029 2030 2031 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2032 to the WMB buffer idle list 2033 2034 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2035 returned to the WMB idle link descriptor idle list 2036 2037 <enum 2 FW_BM> This buffer shall be returned to the FW 2038 2039 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2040 ring 0 2041 2042 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2043 ring 1 2044 2045 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2046 ring 2 2047 2048 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2049 ring 3 2050 2051 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2052 ring 4 2053 2054 2055 2056 <legal all> 2057 */ 2058 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 2059 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2060 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2061 2062 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2063 2064 Cookie field exclusively used by SW. 2065 2066 2067 2068 In case of 'NULL' pointer, this field is set to 0 2069 2070 2071 2072 HW ignores the contents, accept that it passes the 2073 programmed value on to other descriptors together with the 2074 physical address 2075 2076 2077 2078 Field can be used by SW to for example associate the 2079 buffers physical address with the virtual address 2080 2081 The bit definitions as used by SW are within SW HLD 2082 specification 2083 2084 2085 2086 NOTE: 2087 2088 The three most significant bits can have a special 2089 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2090 STRUCT, and field transmit_bw_restriction is set 2091 2092 2093 2094 In case of NON punctured transmission: 2095 2096 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2097 2098 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2099 2100 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2101 2102 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2103 2104 2105 2106 In case of punctured transmission: 2107 2108 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2109 2110 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2111 2112 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2113 2114 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2115 2116 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2117 2118 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2119 2120 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2121 2122 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2123 2124 2125 2126 Note: a punctured transmission is indicated by the 2127 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2128 TLV 2129 2130 2131 2132 <legal all> 2133 */ 2134 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 2135 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2136 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2137 2138 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */ 2139 2140 2141 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2142 2143 2144 /* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2145 2146 Address (lower 32 bits) of the MSDU buffer OR 2147 MSDU_EXTENSION descriptor OR Link Descriptor 2148 2149 2150 2151 In case of 'NULL' pointer, this field is set to 0 2152 2153 <legal all> 2154 */ 2155 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 2156 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2157 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2158 2159 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2160 2161 Address (upper 8 bits) of the MSDU buffer OR 2162 MSDU_EXTENSION descriptor OR Link Descriptor 2163 2164 2165 2166 In case of 'NULL' pointer, this field is set to 0 2167 2168 <legal all> 2169 */ 2170 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 2171 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2172 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2173 2174 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2175 2176 Consumer: WBM 2177 2178 Producer: SW/FW 2179 2180 2181 2182 In case of 'NULL' pointer, this field is set to 0 2183 2184 2185 2186 Indicates to which buffer manager the buffer OR 2187 MSDU_EXTENSION descriptor OR link descriptor that is being 2188 pointed to shall be returned after the frame has been 2189 processed. It is used by WBM for routing purposes. 2190 2191 2192 2193 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2194 to the WMB buffer idle list 2195 2196 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2197 returned to the WMB idle link descriptor idle list 2198 2199 <enum 2 FW_BM> This buffer shall be returned to the FW 2200 2201 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2202 ring 0 2203 2204 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2205 ring 1 2206 2207 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2208 ring 2 2209 2210 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2211 ring 3 2212 2213 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2214 ring 4 2215 2216 2217 2218 <legal all> 2219 */ 2220 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2221 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2222 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2223 2224 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2225 2226 Cookie field exclusively used by SW. 2227 2228 2229 2230 In case of 'NULL' pointer, this field is set to 0 2231 2232 2233 2234 HW ignores the contents, accept that it passes the 2235 programmed value on to other descriptors together with the 2236 physical address 2237 2238 2239 2240 Field can be used by SW to for example associate the 2241 buffers physical address with the virtual address 2242 2243 The bit definitions as used by SW are within SW HLD 2244 specification 2245 2246 2247 2248 NOTE: 2249 2250 The three most significant bits can have a special 2251 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2252 STRUCT, and field transmit_bw_restriction is set 2253 2254 2255 2256 In case of NON punctured transmission: 2257 2258 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2259 2260 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2261 2262 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2263 2264 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2265 2266 2267 2268 In case of punctured transmission: 2269 2270 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2271 2272 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2273 2274 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2275 2276 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2277 2278 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2279 2280 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2281 2282 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2283 2284 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2285 2286 2287 2288 Note: a punctured transmission is indicated by the 2289 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2290 TLV 2291 2292 2293 2294 <legal all> 2295 */ 2296 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 2297 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2298 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2299 2300 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */ 2301 2302 2303 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2304 2305 2306 /* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2307 2308 Address (lower 32 bits) of the MSDU buffer OR 2309 MSDU_EXTENSION descriptor OR Link Descriptor 2310 2311 2312 2313 In case of 'NULL' pointer, this field is set to 0 2314 2315 <legal all> 2316 */ 2317 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2318 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2319 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2320 2321 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2322 2323 Address (upper 8 bits) of the MSDU buffer OR 2324 MSDU_EXTENSION descriptor OR Link Descriptor 2325 2326 2327 2328 In case of 'NULL' pointer, this field is set to 0 2329 2330 <legal all> 2331 */ 2332 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2333 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2334 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2335 2336 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2337 2338 Consumer: WBM 2339 2340 Producer: SW/FW 2341 2342 2343 2344 In case of 'NULL' pointer, this field is set to 0 2345 2346 2347 2348 Indicates to which buffer manager the buffer OR 2349 MSDU_EXTENSION descriptor OR link descriptor that is being 2350 pointed to shall be returned after the frame has been 2351 processed. It is used by WBM for routing purposes. 2352 2353 2354 2355 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2356 to the WMB buffer idle list 2357 2358 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2359 returned to the WMB idle link descriptor idle list 2360 2361 <enum 2 FW_BM> This buffer shall be returned to the FW 2362 2363 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2364 ring 0 2365 2366 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2367 ring 1 2368 2369 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2370 ring 2 2371 2372 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2373 ring 3 2374 2375 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2376 ring 4 2377 2378 2379 2380 <legal all> 2381 */ 2382 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2383 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2384 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2385 2386 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2387 2388 Cookie field exclusively used by SW. 2389 2390 2391 2392 In case of 'NULL' pointer, this field is set to 0 2393 2394 2395 2396 HW ignores the contents, accept that it passes the 2397 programmed value on to other descriptors together with the 2398 physical address 2399 2400 2401 2402 Field can be used by SW to for example associate the 2403 buffers physical address with the virtual address 2404 2405 The bit definitions as used by SW are within SW HLD 2406 specification 2407 2408 2409 2410 NOTE: 2411 2412 The three most significant bits can have a special 2413 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2414 STRUCT, and field transmit_bw_restriction is set 2415 2416 2417 2418 In case of NON punctured transmission: 2419 2420 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2421 2422 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2423 2424 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2425 2426 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2427 2428 2429 2430 In case of punctured transmission: 2431 2432 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2433 2434 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2435 2436 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2437 2438 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2439 2440 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2441 2442 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2443 2444 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2445 2446 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2447 2448 2449 2450 Note: a punctured transmission is indicated by the 2451 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2452 TLV 2453 2454 2455 2456 <legal all> 2457 */ 2458 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2459 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2460 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2461 2462 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */ 2463 2464 2465 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2466 2467 2468 /* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2469 2470 Address (lower 32 bits) of the MSDU buffer OR 2471 MSDU_EXTENSION descriptor OR Link Descriptor 2472 2473 2474 2475 In case of 'NULL' pointer, this field is set to 0 2476 2477 <legal all> 2478 */ 2479 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2480 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2481 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2482 2483 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2484 2485 Address (upper 8 bits) of the MSDU buffer OR 2486 MSDU_EXTENSION descriptor OR Link Descriptor 2487 2488 2489 2490 In case of 'NULL' pointer, this field is set to 0 2491 2492 <legal all> 2493 */ 2494 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2495 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2496 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2497 2498 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2499 2500 Consumer: WBM 2501 2502 Producer: SW/FW 2503 2504 2505 2506 In case of 'NULL' pointer, this field is set to 0 2507 2508 2509 2510 Indicates to which buffer manager the buffer OR 2511 MSDU_EXTENSION descriptor OR link descriptor that is being 2512 pointed to shall be returned after the frame has been 2513 processed. It is used by WBM for routing purposes. 2514 2515 2516 2517 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2518 to the WMB buffer idle list 2519 2520 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2521 returned to the WMB idle link descriptor idle list 2522 2523 <enum 2 FW_BM> This buffer shall be returned to the FW 2524 2525 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2526 ring 0 2527 2528 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2529 ring 1 2530 2531 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2532 ring 2 2533 2534 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2535 ring 3 2536 2537 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2538 ring 4 2539 2540 2541 2542 <legal all> 2543 */ 2544 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2545 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2546 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2547 2548 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2549 2550 Cookie field exclusively used by SW. 2551 2552 2553 2554 In case of 'NULL' pointer, this field is set to 0 2555 2556 2557 2558 HW ignores the contents, accept that it passes the 2559 programmed value on to other descriptors together with the 2560 physical address 2561 2562 2563 2564 Field can be used by SW to for example associate the 2565 buffers physical address with the virtual address 2566 2567 The bit definitions as used by SW are within SW HLD 2568 specification 2569 2570 2571 2572 NOTE: 2573 2574 The three most significant bits can have a special 2575 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2576 STRUCT, and field transmit_bw_restriction is set 2577 2578 2579 2580 In case of NON punctured transmission: 2581 2582 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2583 2584 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2585 2586 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2587 2588 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2589 2590 2591 2592 In case of punctured transmission: 2593 2594 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2595 2596 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2597 2598 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2599 2600 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2601 2602 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2603 2604 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2605 2606 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2607 2608 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2609 2610 2611 2612 Note: a punctured transmission is indicated by the 2613 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2614 TLV 2615 2616 2617 2618 <legal all> 2619 */ 2620 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2621 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2622 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2623 2624 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */ 2625 2626 2627 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2628 2629 2630 /* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2631 2632 Address (lower 32 bits) of the MSDU buffer OR 2633 MSDU_EXTENSION descriptor OR Link Descriptor 2634 2635 2636 2637 In case of 'NULL' pointer, this field is set to 0 2638 2639 <legal all> 2640 */ 2641 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2642 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2643 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2644 2645 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2646 2647 Address (upper 8 bits) of the MSDU buffer OR 2648 MSDU_EXTENSION descriptor OR Link Descriptor 2649 2650 2651 2652 In case of 'NULL' pointer, this field is set to 0 2653 2654 <legal all> 2655 */ 2656 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2657 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2658 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2659 2660 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2661 2662 Consumer: WBM 2663 2664 Producer: SW/FW 2665 2666 2667 2668 In case of 'NULL' pointer, this field is set to 0 2669 2670 2671 2672 Indicates to which buffer manager the buffer OR 2673 MSDU_EXTENSION descriptor OR link descriptor that is being 2674 pointed to shall be returned after the frame has been 2675 processed. It is used by WBM for routing purposes. 2676 2677 2678 2679 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2680 to the WMB buffer idle list 2681 2682 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2683 returned to the WMB idle link descriptor idle list 2684 2685 <enum 2 FW_BM> This buffer shall be returned to the FW 2686 2687 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2688 ring 0 2689 2690 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2691 ring 1 2692 2693 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2694 ring 2 2695 2696 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2697 ring 3 2698 2699 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2700 ring 4 2701 2702 2703 2704 <legal all> 2705 */ 2706 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2707 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2708 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2709 2710 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2711 2712 Cookie field exclusively used by SW. 2713 2714 2715 2716 In case of 'NULL' pointer, this field is set to 0 2717 2718 2719 2720 HW ignores the contents, accept that it passes the 2721 programmed value on to other descriptors together with the 2722 physical address 2723 2724 2725 2726 Field can be used by SW to for example associate the 2727 buffers physical address with the virtual address 2728 2729 The bit definitions as used by SW are within SW HLD 2730 specification 2731 2732 2733 2734 NOTE: 2735 2736 The three most significant bits can have a special 2737 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2738 STRUCT, and field transmit_bw_restriction is set 2739 2740 2741 2742 In case of NON punctured transmission: 2743 2744 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2745 2746 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2747 2748 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2749 2750 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2751 2752 2753 2754 In case of punctured transmission: 2755 2756 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2757 2758 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2759 2760 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2761 2762 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2763 2764 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2765 2766 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2767 2768 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2769 2770 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2771 2772 2773 2774 Note: a punctured transmission is indicated by the 2775 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2776 TLV 2777 2778 2779 2780 <legal all> 2781 */ 2782 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2783 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2784 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2785 2786 2787 #endif // _RX_REO_QUEUE_EXT_H_ 2788