1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SW_MONITOR_RING_H_ 18 #define _SW_MONITOR_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_details.h" 23 #include "buffer_addr_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 29 // 4-5 struct buffer_addr_info status_buff_addr_info; 30 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], frameless_bar[11], status_buf_count[15:12], end_of_ppdu[16], reserved_6a[31:17] 31 // 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] 32 // 33 // ################ END SUMMARY ################# 34 35 #define NUM_OF_DWORDS_SW_MONITOR_RING 8 36 37 struct sw_monitor_ring { 38 struct rx_mpdu_details reo_level_mpdu_frame_info; 39 struct buffer_addr_info status_buff_addr_info; 40 uint32_t rxdma_push_reason : 2, //[1:0] 41 rxdma_error_code : 5, //[6:2] 42 mpdu_fragment_number : 4, //[10:7] 43 frameless_bar : 1, //[11] 44 status_buf_count : 4, //[15:12] 45 end_of_ppdu : 1, //[16] 46 reserved_6a : 15; //[31:17] 47 uint32_t phy_ppdu_id : 16, //[15:0] 48 reserved_7a : 4, //[19:16] 49 ring_id : 8, //[27:20] 50 looping_count : 4; //[31:28] 51 }; 52 53 /* 54 55 struct rx_mpdu_details reo_level_mpdu_frame_info 56 57 Consumer: SW 58 59 Producer: RXDMA 60 61 62 63 Details related to the MPDU being pushed to SW, valid 64 only if end_of_ppdu is set to 0 65 66 struct buffer_addr_info status_buff_addr_info 67 68 Consumer: SW 69 70 Producer: RXDMA 71 72 73 74 Details of the physical address of the first status 75 buffer used for the PPDU (either the PPDU that included the 76 MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU 77 whose end is indicated through end_of_ppdu = 1) 78 79 rxdma_push_reason 80 81 Indicates why RXDMA pushed the frame to this ring 82 83 84 85 <enum 0 rxdma_error_detected> RXDMA detected an error an 86 pushed this frame to this queue 87 88 <enum 1 rxdma_routing_instruction> RXDMA pushed the 89 frame to this queue per received routing instructions. No 90 error within RXDMA was detected 91 92 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 93 result the MSDU link descriptor might not have the 94 last_msdu_in_mpdu_flag set, but instead WBM might just see a 95 NULL pointer in the MSDU link descriptor. This is to be 96 considered a normal condition for this scenario. 97 98 99 100 <legal 0 - 2> 101 102 rxdma_error_code 103 104 Field only valid when rxdma_push_reason is set to 105 'rxdma_error_detected.' 106 107 108 109 <enum 0 rxdma_overflow_err>MPDU frame is not complete 110 due to a FIFO overflow error in RXPCU. 111 112 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 113 due to receiving incomplete MPDU from the PHY 114 115 116 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 117 error or CRYPTO received an encrypted frame, but did not get 118 a valid corresponding key id in the peer entry. 119 120 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 121 error 122 123 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 124 unencrypted frame error when encrypted was expected 125 126 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 127 length error 128 129 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 130 number of MSDUs allowed in an MPDU got exceeded 131 132 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 133 error 134 135 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 136 parsing error 137 138 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 139 during SA search 140 141 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 142 during DA search 143 144 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 145 timeout during flow search 146 147 <enum 13 rxdma_flush_request>RXDMA received a flush 148 request 149 150 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 151 present as well as a fragmented MPDU. A-MSDU defragmentation 152 is not supported in Lithium SW so this is treated as an 153 error. 154 155 mpdu_fragment_number 156 157 Field only valid when Reo_level_mpdu_frame_info. 158 Rx_mpdu_desc_info_details.Fragment_flag is set and 159 end_of_ppdu is set to 0. 160 161 162 163 The fragment number from the 802.11 header. 164 165 166 167 Note that the sequence number is embedded in the field: 168 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 169 Mpdu_sequence_number 170 171 172 173 <legal all> 174 175 frameless_bar 176 177 When set, this SW monitor ring struct contains BAR info 178 from a multi TID BAR frame. The original multi TID BAR frame 179 itself contained all the REO info for the first TID, but all 180 the subsequent TID info and their linkage to the REO 181 descriptors is passed down as 'frameless' BAR info. 182 183 184 185 The only fields valid in this descriptor when this bit 186 is within the 187 188 Reo_level_mpdu_frame_info: 189 190 Within Rx_mpdu_desc_info_details: 191 192 Mpdu_Sequence_number 193 194 BAR_frame 195 196 Peer_meta_data 197 198 All other fields shall be set to 0. 199 200 201 202 <legal all> 203 204 status_buf_count 205 206 A count of status buffers used so far for the PPDU 207 (either the PPDU that included the MPDU being pushed to SW 208 if end_of_ppdu = 0, or the PPDU whose end is indicated 209 through end_of_ppdu = 1) 210 211 end_of_ppdu 212 213 Pine RXDMA can be configured to generate a separate 214 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 215 through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 216 demarcate PPDUs. 217 218 219 220 For such a descriptor, this bit is set to 1 and fields 221 Reo_level_mpdu_frame_info, mpdu_fragment_number and 222 Frameless_bar are all set to 0. 223 224 225 226 Otherwise this bit is set to 0. 227 228 reserved_6a 229 230 <legal 0> 231 232 phy_ppdu_id 233 234 A PPDU counter value that PHY increments for every PPDU 235 received 236 237 The counter value wraps around. Pine RXDMA can be 238 configured to copy this from the RX_PPDU_START TLV for every 239 output descriptor. 240 241 242 243 <legal all> 244 245 reserved_7a 246 247 <legal 0> 248 249 ring_id 250 251 Consumer: SW/REO/DEBUG 252 253 Producer: SRNG (of RXDMA) 254 255 256 257 For debugging. 258 259 This field is filled in by the SRNG module. 260 261 It help to identify the ring that is being looked <legal 262 all> 263 264 looping_count 265 266 Consumer: SW/REO/DEBUG 267 268 Producer: SRNG (of RXDMA) 269 270 271 272 For debugging. 273 274 This field is filled in by the SRNG module. 275 276 277 278 A count value that indicates the number of times the 279 producer of entries into this Ring has looped around the 280 ring. 281 282 At initialization time, this value is set to 0. On the 283 first loop, this value is set to 1. After the max value is 284 reached allowed by the number of bits for this field, the 285 count value continues with 0 again. 286 287 288 289 In case SW is the consumer of the ring entries, it can 290 use this field to figure out up to where the producer of 291 entries has created new entries. This eliminates the need to 292 check where the head pointer' of the ring is located once 293 the SW starts processing an interrupt indicating that new 294 entries have been put into this ring... 295 296 297 298 Also note that SW if it wants only needs to look at the 299 LSB bit of this count value. 300 301 <legal all> 302 */ 303 304 305 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 306 307 308 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 309 310 311 /* Description SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 312 313 Address (lower 32 bits) of the MSDU buffer OR 314 MSDU_EXTENSION descriptor OR Link Descriptor 315 316 317 318 In case of 'NULL' pointer, this field is set to 0 319 320 <legal all> 321 */ 322 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 323 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 324 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 325 326 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 327 328 Address (upper 8 bits) of the MSDU buffer OR 329 MSDU_EXTENSION descriptor OR Link Descriptor 330 331 332 333 In case of 'NULL' pointer, this field is set to 0 334 335 <legal all> 336 */ 337 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 338 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 339 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 340 341 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 342 343 Consumer: WBM 344 345 Producer: SW/FW 346 347 348 349 In case of 'NULL' pointer, this field is set to 0 350 351 352 353 Indicates to which buffer manager the buffer OR 354 MSDU_EXTENSION descriptor OR link descriptor that is being 355 pointed to shall be returned after the frame has been 356 processed. It is used by WBM for routing purposes. 357 358 359 360 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 361 to the WMB buffer idle list 362 363 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 364 returned to the WMB idle link descriptor idle list 365 366 <enum 2 FW_BM> This buffer shall be returned to the FW 367 368 <enum 3 SW0_BM> This buffer shall be returned to the SW, 369 ring 0 370 371 <enum 4 SW1_BM> This buffer shall be returned to the SW, 372 ring 1 373 374 <enum 5 SW2_BM> This buffer shall be returned to the SW, 375 ring 2 376 377 <enum 6 SW3_BM> This buffer shall be returned to the SW, 378 ring 3 379 380 <enum 7 SW4_BM> This buffer shall be returned to the SW, 381 ring 4 382 383 384 385 <legal all> 386 */ 387 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 388 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 389 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 390 391 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 392 393 Cookie field exclusively used by SW. 394 395 396 397 In case of 'NULL' pointer, this field is set to 0 398 399 400 401 HW ignores the contents, accept that it passes the 402 programmed value on to other descriptors together with the 403 physical address 404 405 406 407 Field can be used by SW to for example associate the 408 buffers physical address with the virtual address 409 410 The bit definitions as used by SW are within SW HLD 411 specification 412 413 414 415 NOTE: 416 417 The three most significant bits can have a special 418 meaning in case this struct is embedded in a TX_MPDU_DETAILS 419 STRUCT, and field transmit_bw_restriction is set 420 421 422 423 In case of NON punctured transmission: 424 425 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 426 427 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 428 429 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 430 431 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 432 433 434 435 In case of punctured transmission: 436 437 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 438 439 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 440 441 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 442 443 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 444 445 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 446 447 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 448 449 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 450 451 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 452 453 454 455 Note: a punctured transmission is indicated by the 456 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 457 TLV 458 459 460 461 <legal all> 462 */ 463 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 464 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 465 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 466 467 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 468 469 470 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 471 472 Consumer: REO/SW/FW 473 474 Producer: RXDMA 475 476 477 478 The number of MSDUs within the MPDU 479 480 <legal all> 481 */ 482 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 483 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 484 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 485 486 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 487 488 Consumer: REO/SW/FW 489 490 Producer: RXDMA 491 492 493 494 The field can have two different meanings based on the 495 setting of field 'BAR_frame': 496 497 498 499 'BAR_frame' is NOT set: 500 501 The MPDU sequence number of the received frame. 502 503 504 505 'BAR_frame' is set. 506 507 The MPDU Start sequence number from the BAR frame 508 509 <legal all> 510 */ 511 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 512 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 513 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 514 515 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 516 517 Consumer: REO/SW/FW 518 519 Producer: RXDMA 520 521 522 523 When set, this MPDU is a fragment and REO should forward 524 this fragment MPDU to the REO destination ring without any 525 reorder checks, pn checks or bitmap update. This implies 526 that REO is forwarding the pointer to the MSDU link 527 descriptor. The destination ring is coming from a 528 programmable register setting in REO 529 530 531 532 <legal all> 533 */ 534 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 535 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 536 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 537 538 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 539 540 Consumer: REO/SW/FW 541 542 Producer: RXDMA 543 544 545 546 The retry bit setting from the MPDU header of the 547 received frame 548 549 <legal all> 550 */ 551 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 552 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 553 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 554 555 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 556 557 Consumer: REO/SW/FW 558 559 Producer: RXDMA 560 561 562 563 When set, the MPDU was received as part of an A-MPDU. 564 565 <legal all> 566 */ 567 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 568 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 569 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 570 571 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 572 573 Consumer: REO/SW/FW 574 575 Producer: RXDMA 576 577 578 579 When set, the received frame is a BAR frame. After 580 processing, this frame shall be pushed to SW or deleted. 581 582 <legal all> 583 */ 584 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 585 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 586 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 587 588 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 589 590 Consumer: REO/SW/FW 591 592 Producer: RXDMA 593 594 595 596 Copied here by RXDMA from RX_MPDU_END 597 598 When not set, REO will Not perform a PN sequence number 599 check 600 */ 601 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 602 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 603 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 604 605 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 606 607 When set, OLE found a valid SA entry for all MSDUs in 608 this MPDU 609 610 <legal all> 611 */ 612 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 613 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 614 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 615 616 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 617 618 When set, at least 1 MSDU within the MPDU has an 619 unsuccessful MAC source address search due to the expiration 620 of the search timer. 621 622 <legal all> 623 */ 624 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 625 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 626 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 627 628 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 629 630 When set, OLE found a valid DA entry for all MSDUs in 631 this MPDU 632 633 <legal all> 634 */ 635 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 636 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 637 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 638 639 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 640 641 Field Only valid if da_is_valid is set 642 643 644 645 When set, at least one of the DA addresses is a 646 Multicast or Broadcast address. 647 648 <legal all> 649 */ 650 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 651 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 652 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 653 654 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 655 656 When set, at least 1 MSDU within the MPDU has an 657 unsuccessful MAC destination address search due to the 658 expiration of the search timer. 659 660 <legal all> 661 */ 662 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 663 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 664 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 665 666 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 667 668 Field only valid when first_msdu_in_mpdu_flag is set. 669 670 671 672 When set, the contents in the MSDU buffer contains a 673 'RAW' MPDU. This 'RAW' MPDU might be spread out over 674 multiple MSDU buffers. 675 676 <legal all> 677 */ 678 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 679 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 680 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 681 682 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 683 684 The More Fragment bit setting from the MPDU header of 685 the received frame 686 687 688 689 <legal all> 690 */ 691 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 692 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 693 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 694 695 /* Description SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 696 697 Meta data that SW has programmed in the Peer table entry 698 of the transmitting STA. 699 700 <legal all> 701 */ 702 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 703 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 704 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 705 706 /* EXTERNAL REFERENCE : struct buffer_addr_info status_buff_addr_info */ 707 708 709 /* Description SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0 710 711 Address (lower 32 bits) of the MSDU buffer OR 712 MSDU_EXTENSION descriptor OR Link Descriptor 713 714 715 716 In case of 'NULL' pointer, this field is set to 0 717 718 <legal all> 719 */ 720 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 721 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 722 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 723 724 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32 725 726 Address (upper 8 bits) of the MSDU buffer OR 727 MSDU_EXTENSION descriptor OR Link Descriptor 728 729 730 731 In case of 'NULL' pointer, this field is set to 0 732 733 <legal all> 734 */ 735 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 736 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 737 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 738 739 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER 740 741 Consumer: WBM 742 743 Producer: SW/FW 744 745 746 747 In case of 'NULL' pointer, this field is set to 0 748 749 750 751 Indicates to which buffer manager the buffer OR 752 MSDU_EXTENSION descriptor OR link descriptor that is being 753 pointed to shall be returned after the frame has been 754 processed. It is used by WBM for routing purposes. 755 756 757 758 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 759 to the WMB buffer idle list 760 761 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 762 returned to the WMB idle link descriptor idle list 763 764 <enum 2 FW_BM> This buffer shall be returned to the FW 765 766 <enum 3 SW0_BM> This buffer shall be returned to the SW, 767 ring 0 768 769 <enum 4 SW1_BM> This buffer shall be returned to the SW, 770 ring 1 771 772 <enum 5 SW2_BM> This buffer shall be returned to the SW, 773 ring 2 774 775 <enum 6 SW3_BM> This buffer shall be returned to the SW, 776 ring 3 777 778 <enum 7 SW4_BM> This buffer shall be returned to the SW, 779 ring 4 780 781 782 783 <legal all> 784 */ 785 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 786 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 787 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 788 789 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE 790 791 Cookie field exclusively used by SW. 792 793 794 795 In case of 'NULL' pointer, this field is set to 0 796 797 798 799 HW ignores the contents, accept that it passes the 800 programmed value on to other descriptors together with the 801 physical address 802 803 804 805 Field can be used by SW to for example associate the 806 buffers physical address with the virtual address 807 808 The bit definitions as used by SW are within SW HLD 809 specification 810 811 812 813 NOTE: 814 815 The three most significant bits can have a special 816 meaning in case this struct is embedded in a TX_MPDU_DETAILS 817 STRUCT, and field transmit_bw_restriction is set 818 819 820 821 In case of NON punctured transmission: 822 823 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 824 825 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 826 827 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 828 829 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 830 831 832 833 In case of punctured transmission: 834 835 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 836 837 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 838 839 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 840 841 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 842 843 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 844 845 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 846 847 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 848 849 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 850 851 852 853 Note: a punctured transmission is indicated by the 854 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 855 TLV 856 857 858 859 <legal all> 860 */ 861 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 862 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 863 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 864 865 /* Description SW_MONITOR_RING_6_RXDMA_PUSH_REASON 866 867 Indicates why RXDMA pushed the frame to this ring 868 869 870 871 <enum 0 rxdma_error_detected> RXDMA detected an error an 872 pushed this frame to this queue 873 874 <enum 1 rxdma_routing_instruction> RXDMA pushed the 875 frame to this queue per received routing instructions. No 876 error within RXDMA was detected 877 878 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 879 result the MSDU link descriptor might not have the 880 last_msdu_in_mpdu_flag set, but instead WBM might just see a 881 NULL pointer in the MSDU link descriptor. This is to be 882 considered a normal condition for this scenario. 883 884 885 886 <legal 0 - 2> 887 */ 888 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 889 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_LSB 0 890 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 891 892 /* Description SW_MONITOR_RING_6_RXDMA_ERROR_CODE 893 894 Field only valid when rxdma_push_reason is set to 895 'rxdma_error_detected.' 896 897 898 899 <enum 0 rxdma_overflow_err>MPDU frame is not complete 900 due to a FIFO overflow error in RXPCU. 901 902 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 903 due to receiving incomplete MPDU from the PHY 904 905 906 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 907 error or CRYPTO received an encrypted frame, but did not get 908 a valid corresponding key id in the peer entry. 909 910 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 911 error 912 913 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 914 unencrypted frame error when encrypted was expected 915 916 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 917 length error 918 919 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 920 number of MSDUs allowed in an MPDU got exceeded 921 922 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 923 error 924 925 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 926 parsing error 927 928 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 929 during SA search 930 931 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 932 during DA search 933 934 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 935 timeout during flow search 936 937 <enum 13 rxdma_flush_request>RXDMA received a flush 938 request 939 940 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 941 present as well as a fragmented MPDU. A-MSDU defragmentation 942 is not supported in Lithium SW so this is treated as an 943 error. 944 */ 945 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 946 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_LSB 2 947 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 948 949 /* Description SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER 950 951 Field only valid when Reo_level_mpdu_frame_info. 952 Rx_mpdu_desc_info_details.Fragment_flag is set and 953 end_of_ppdu is set to 0. 954 955 956 957 The fragment number from the 802.11 header. 958 959 960 961 Note that the sequence number is embedded in the field: 962 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 963 Mpdu_sequence_number 964 965 966 967 <legal all> 968 */ 969 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 970 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 971 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 972 973 /* Description SW_MONITOR_RING_6_FRAMELESS_BAR 974 975 When set, this SW monitor ring struct contains BAR info 976 from a multi TID BAR frame. The original multi TID BAR frame 977 itself contained all the REO info for the first TID, but all 978 the subsequent TID info and their linkage to the REO 979 descriptors is passed down as 'frameless' BAR info. 980 981 982 983 The only fields valid in this descriptor when this bit 984 is within the 985 986 Reo_level_mpdu_frame_info: 987 988 Within Rx_mpdu_desc_info_details: 989 990 Mpdu_Sequence_number 991 992 BAR_frame 993 994 Peer_meta_data 995 996 All other fields shall be set to 0. 997 998 999 1000 <legal all> 1001 */ 1002 #define SW_MONITOR_RING_6_FRAMELESS_BAR_OFFSET 0x00000018 1003 #define SW_MONITOR_RING_6_FRAMELESS_BAR_LSB 11 1004 #define SW_MONITOR_RING_6_FRAMELESS_BAR_MASK 0x00000800 1005 1006 /* Description SW_MONITOR_RING_6_STATUS_BUF_COUNT 1007 1008 A count of status buffers used so far for the PPDU 1009 (either the PPDU that included the MPDU being pushed to SW 1010 if end_of_ppdu = 0, or the PPDU whose end is indicated 1011 through end_of_ppdu = 1) 1012 */ 1013 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_OFFSET 0x00000018 1014 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_LSB 12 1015 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_MASK 0x0000f000 1016 1017 /* Description SW_MONITOR_RING_6_END_OF_PPDU 1018 1019 Pine RXDMA can be configured to generate a separate 1020 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 1021 through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 1022 demarcate PPDUs. 1023 1024 1025 1026 For such a descriptor, this bit is set to 1 and fields 1027 Reo_level_mpdu_frame_info, mpdu_fragment_number and 1028 Frameless_bar are all set to 0. 1029 1030 1031 1032 Otherwise this bit is set to 0. 1033 */ 1034 #define SW_MONITOR_RING_6_END_OF_PPDU_OFFSET 0x00000018 1035 #define SW_MONITOR_RING_6_END_OF_PPDU_LSB 16 1036 #define SW_MONITOR_RING_6_END_OF_PPDU_MASK 0x00010000 1037 1038 /* Description SW_MONITOR_RING_6_RESERVED_6A 1039 1040 <legal 0> 1041 */ 1042 #define SW_MONITOR_RING_6_RESERVED_6A_OFFSET 0x00000018 1043 #define SW_MONITOR_RING_6_RESERVED_6A_LSB 17 1044 #define SW_MONITOR_RING_6_RESERVED_6A_MASK 0xfffe0000 1045 1046 /* Description SW_MONITOR_RING_7_PHY_PPDU_ID 1047 1048 A PPDU counter value that PHY increments for every PPDU 1049 received 1050 1051 The counter value wraps around. Pine RXDMA can be 1052 configured to copy this from the RX_PPDU_START TLV for every 1053 output descriptor. 1054 1055 1056 1057 <legal all> 1058 */ 1059 #define SW_MONITOR_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c 1060 #define SW_MONITOR_RING_7_PHY_PPDU_ID_LSB 0 1061 #define SW_MONITOR_RING_7_PHY_PPDU_ID_MASK 0x0000ffff 1062 1063 /* Description SW_MONITOR_RING_7_RESERVED_7A 1064 1065 <legal 0> 1066 */ 1067 #define SW_MONITOR_RING_7_RESERVED_7A_OFFSET 0x0000001c 1068 #define SW_MONITOR_RING_7_RESERVED_7A_LSB 16 1069 #define SW_MONITOR_RING_7_RESERVED_7A_MASK 0x000f0000 1070 1071 /* Description SW_MONITOR_RING_7_RING_ID 1072 1073 Consumer: SW/REO/DEBUG 1074 1075 Producer: SRNG (of RXDMA) 1076 1077 1078 1079 For debugging. 1080 1081 This field is filled in by the SRNG module. 1082 1083 It help to identify the ring that is being looked <legal 1084 all> 1085 */ 1086 #define SW_MONITOR_RING_7_RING_ID_OFFSET 0x0000001c 1087 #define SW_MONITOR_RING_7_RING_ID_LSB 20 1088 #define SW_MONITOR_RING_7_RING_ID_MASK 0x0ff00000 1089 1090 /* Description SW_MONITOR_RING_7_LOOPING_COUNT 1091 1092 Consumer: SW/REO/DEBUG 1093 1094 Producer: SRNG (of RXDMA) 1095 1096 1097 1098 For debugging. 1099 1100 This field is filled in by the SRNG module. 1101 1102 1103 1104 A count value that indicates the number of times the 1105 producer of entries into this Ring has looped around the 1106 ring. 1107 1108 At initialization time, this value is set to 0. On the 1109 first loop, this value is set to 1. After the max value is 1110 reached allowed by the number of bits for this field, the 1111 count value continues with 0 again. 1112 1113 1114 1115 In case SW is the consumer of the ring entries, it can 1116 use this field to figure out up to where the producer of 1117 entries has created new entries. This eliminates the need to 1118 check where the head pointer' of the ring is located once 1119 the SW starts processing an interrupt indicating that new 1120 entries have been put into this ring... 1121 1122 1123 1124 Also note that SW if it wants only needs to look at the 1125 LSB bit of this count value. 1126 1127 <legal all> 1128 */ 1129 #define SW_MONITOR_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1130 #define SW_MONITOR_RING_7_LOOPING_COUNT_LSB 28 1131 #define SW_MONITOR_RING_7_LOOPING_COUNT_MASK 0xf0000000 1132 1133 1134 #endif // _SW_MONITOR_RING_H_ 1135