1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TCL_STATUS_RING_H_ 18 #define _TCL_STATUS_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8] 27 // 1 msdu_byte_cnt_n[31:0] 28 // 2 msdu_timestmp_n[31:0] 29 // 3 cmd_meta_data_31_0[31:0] 30 // 4 cmd_meta_data_63_32[31:0] 31 // 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24] 32 // 6 reserved_6a[31:0] 33 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 34 // 35 // ################ END SUMMARY ################# 36 37 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 38 39 struct tcl_status_ring { 40 uint32_t gse_ctrl : 4, //[3:0] 41 ase_fse_sel : 1, //[4] 42 cache_op_res : 2, //[6:5] 43 index_search_en : 1, //[7] 44 msdu_cnt_n : 24; //[31:8] 45 uint32_t msdu_byte_cnt_n : 32; //[31:0] 46 uint32_t msdu_timestmp_n : 32; //[31:0] 47 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 48 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 49 uint32_t hash_indx_val : 20, //[19:0] 50 cache_set_num : 4, //[23:20] 51 reserved_5a : 8; //[31:24] 52 uint32_t reserved_6a : 32; //[31:0] 53 uint32_t reserved_7a : 20, //[19:0] 54 ring_id : 8, //[27:20] 55 looping_count : 4; //[31:28] 56 }; 57 58 /* 59 60 gse_ctrl 61 62 GSE control operations. This includes cache operations 63 and table entry statistics read/clear operation. 64 65 <enum 0 rd_stat> Report or Read statistics 66 67 <enum 1 srch_dis> Search disable. Report only Hash 68 69 <enum 2 Wr_bk_single> Write Back single entry 70 71 <enum 3 wr_bk_all> Write Back entire cache entry 72 73 <enum 4 inval_single> Invalidate single cache entry 74 75 <enum 5 inval_all> Invalidate entire cache 76 77 <enum 6 wr_bk_inval_single> Write back and Invalidate 78 single entry in cache 79 80 <enum 7 wr_bk_inval_all> write back and invalidate 81 entire cache 82 83 <enum 8 clr_stat_single> Clear statistics for single 84 entry 85 86 <legal 0-8> 87 88 Rest of the values reserved. 89 90 For all single entry control operations (write back, 91 Invalidate or both)Statistics will be reported 92 93 ase_fse_sel 94 95 Search Engine for which operation is done. 96 97 1'b0: Address Search Engine Result 98 99 1'b1: Flow Search Engine result 100 101 cache_op_res 102 103 Cache operation result. Following are results of cache 104 operation. 105 106 <enum 0 op_done> Operation successful 107 108 <enum 1 not_fnd> Entry not found in Table 109 110 <enum 2 timeout_er> Timeout Error 111 112 <legal 0-2> 113 114 index_search_en 115 116 When this bit is set to 1 control_buffer_addr[19:0] will 117 be considered as index of the AST or Flow table and GSE 118 commands will be executed accordingly on the entry pointed 119 by the index. 120 121 This feature is disabled by setting this bit to 0. 122 123 <enum 0 index_based_cmd_disable> 124 125 <enum 1 index_based_cmd_enable> 126 127 128 129 <legal all> 130 131 msdu_cnt_n 132 133 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 134 4'b1000 135 136 msdu_byte_cnt_n 137 138 MSDU byte count for entry 1. Valid when GSE_CTRL is 139 4'b0111 and 4'b1000 140 141 msdu_timestmp_n 142 143 MSDU timestamp for entry 1. Valid when GSE_CTRL is 144 4'b0111 and 4'b1000 145 146 cmd_meta_data_31_0 147 148 Meta data from input ring 149 150 <legal all> 151 152 cmd_meta_data_63_32 153 154 Meta data from input ring 155 156 <legal all> 157 158 hash_indx_val 159 160 161 Hash value of the entry in table in case of search 162 failed or search disable. 163 164 <legal all> 165 166 cache_set_num 167 168 Cache set number copied from TCL_GSE_CMD 169 170 reserved_5a 171 172 <legal 0> 173 174 reserved_6a 175 176 <legal 0> 177 178 reserved_7a 179 180 <legal 0> 181 182 ring_id 183 184 The buffer pointer ring ID. 185 186 187 188 Helps with debugging when dumping ring contents. 189 190 <legal all> 191 192 looping_count 193 194 A count value that indicates the number of times the 195 producer of entries into the Ring has looped around the 196 ring. 197 198 At initialization time, this value is set to 0. On the 199 first loop, this value is set to 1. After the max value is 200 reached allowed by the number of bits for this field, the 201 count value continues with 0 again. 202 203 204 205 In case SW is the consumer of the ring entries, it can 206 use this field to figure out up to where the producer of 207 entries has created new entries. This eliminates the need to 208 check where the head pointer' of the ring is located once 209 the SW starts processing an interrupt indicating that new 210 entries have been put into this ring... 211 212 213 214 Also note that SW if it wants only needs to look at the 215 LSB bit of this count value. 216 217 <legal all> 218 */ 219 220 221 /* Description TCL_STATUS_RING_0_GSE_CTRL 222 223 GSE control operations. This includes cache operations 224 and table entry statistics read/clear operation. 225 226 <enum 0 rd_stat> Report or Read statistics 227 228 <enum 1 srch_dis> Search disable. Report only Hash 229 230 <enum 2 Wr_bk_single> Write Back single entry 231 232 <enum 3 wr_bk_all> Write Back entire cache entry 233 234 <enum 4 inval_single> Invalidate single cache entry 235 236 <enum 5 inval_all> Invalidate entire cache 237 238 <enum 6 wr_bk_inval_single> Write back and Invalidate 239 single entry in cache 240 241 <enum 7 wr_bk_inval_all> write back and invalidate 242 entire cache 243 244 <enum 8 clr_stat_single> Clear statistics for single 245 entry 246 247 <legal 0-8> 248 249 Rest of the values reserved. 250 251 For all single entry control operations (write back, 252 Invalidate or both)Statistics will be reported 253 */ 254 #define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 255 #define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 256 #define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f 257 258 /* Description TCL_STATUS_RING_0_ASE_FSE_SEL 259 260 Search Engine for which operation is done. 261 262 1'b0: Address Search Engine Result 263 264 1'b1: Flow Search Engine result 265 */ 266 #define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 267 #define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 268 #define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 269 270 /* Description TCL_STATUS_RING_0_CACHE_OP_RES 271 272 Cache operation result. Following are results of cache 273 operation. 274 275 <enum 0 op_done> Operation successful 276 277 <enum 1 not_fnd> Entry not found in Table 278 279 <enum 2 timeout_er> Timeout Error 280 281 <legal 0-2> 282 */ 283 #define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 284 #define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 285 #define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 286 287 /* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN 288 289 When this bit is set to 1 control_buffer_addr[19:0] will 290 be considered as index of the AST or Flow table and GSE 291 commands will be executed accordingly on the entry pointed 292 by the index. 293 294 This feature is disabled by setting this bit to 0. 295 296 <enum 0 index_based_cmd_disable> 297 298 <enum 1 index_based_cmd_enable> 299 300 301 302 <legal all> 303 */ 304 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 305 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 306 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 307 308 /* Description TCL_STATUS_RING_0_MSDU_CNT_N 309 310 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 311 4'b1000 312 */ 313 #define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 314 #define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 315 #define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 316 317 /* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N 318 319 MSDU byte count for entry 1. Valid when GSE_CTRL is 320 4'b0111 and 4'b1000 321 */ 322 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 323 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 324 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff 325 326 /* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N 327 328 MSDU timestamp for entry 1. Valid when GSE_CTRL is 329 4'b0111 and 4'b1000 330 */ 331 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 332 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 333 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff 334 335 /* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 336 337 Meta data from input ring 338 339 <legal all> 340 */ 341 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c 342 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 343 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff 344 345 /* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 346 347 Meta data from input ring 348 349 <legal all> 350 */ 351 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 352 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 353 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff 354 355 /* Description TCL_STATUS_RING_5_HASH_INDX_VAL 356 357 358 Hash value of the entry in table in case of search 359 failed or search disable. 360 361 <legal all> 362 */ 363 #define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 364 #define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 365 #define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff 366 367 /* Description TCL_STATUS_RING_5_CACHE_SET_NUM 368 369 Cache set number copied from TCL_GSE_CMD 370 */ 371 #define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 372 #define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 373 #define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 374 375 /* Description TCL_STATUS_RING_5_RESERVED_5A 376 377 <legal 0> 378 */ 379 #define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 380 #define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 381 #define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 382 383 /* Description TCL_STATUS_RING_6_RESERVED_6A 384 385 <legal 0> 386 */ 387 #define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 388 #define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 389 #define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff 390 391 /* Description TCL_STATUS_RING_7_RESERVED_7A 392 393 <legal 0> 394 */ 395 #define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c 396 #define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 397 #define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff 398 399 /* Description TCL_STATUS_RING_7_RING_ID 400 401 The buffer pointer ring ID. 402 403 404 405 Helps with debugging when dumping ring contents. 406 407 <legal all> 408 */ 409 #define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c 410 #define TCL_STATUS_RING_7_RING_ID_LSB 20 411 #define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 412 413 /* Description TCL_STATUS_RING_7_LOOPING_COUNT 414 415 A count value that indicates the number of times the 416 producer of entries into the Ring has looped around the 417 ring. 418 419 At initialization time, this value is set to 0. On the 420 first loop, this value is set to 1. After the max value is 421 reached allowed by the number of bits for this field, the 422 count value continues with 0 again. 423 424 425 426 In case SW is the consumer of the ring entries, it can 427 use this field to figure out up to where the producer of 428 entries has created new entries. This eliminates the need to 429 check where the head pointer' of the ring is located once 430 the SW starts processing an interrupt indicating that new 431 entries have been put into this ring... 432 433 434 435 Also note that SW if it wants only needs to look at the 436 LSB bit of this count value. 437 438 <legal all> 439 */ 440 #define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 441 #define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 442 #define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 443 444 445 #endif // _TCL_STATUS_RING_H_ 446