1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ 18 #define _UNIFORM_DESCRIPTOR_HEADER_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8] 27 // 28 // ################ END SUMMARY ################# 29 30 #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 31 32 struct uniform_descriptor_header { 33 uint32_t owner : 4, //[3:0] 34 buffer_type : 4, //[7:4] 35 reserved_0a : 24; //[31:8] 36 }; 37 38 /* 39 40 owner 41 42 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 43 44 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 45 46 47 48 The owner of this data structure: 49 50 <enum 0 WBM_owned> Buffer Manager currently owns this 51 data structure. 52 53 <enum 1 SW_OR_FW_owned> Software of FW currently owns 54 this data structure. 55 56 <enum 2 TQM_owned> Transmit Queue Manager currently owns 57 this data structure. 58 59 <enum 3 RXDMA_owned> Receive DMA currently owns this 60 data structure. 61 62 <enum 4 REO_owned> Reorder currently owns this data 63 structure. 64 65 <enum 5 SWITCH_owned> SWITCH currently owns this data 66 structure. 67 68 69 70 <legal 0-5> 71 72 buffer_type 73 74 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 75 76 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 77 78 79 80 Field describing what contents format is of this 81 descriptor 82 83 84 85 <enum 0 Transmit_MSDU_Link_descriptor > 86 87 <enum 1 Transmit_MPDU_Link_descriptor > 88 89 <enum 2 Transmit_MPDU_Queue_head_descriptor> 90 91 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 92 93 <enum 4 Transmit_flow_descriptor> 94 95 <enum 5 Transmit_buffer > NOT TO BE USED: 96 97 98 99 <enum 6 Receive_MSDU_Link_descriptor > 100 101 <enum 7 Receive_MPDU_Link_descriptor > 102 103 <enum 8 Receive_REO_queue_descriptor > 104 105 <enum 9 Receive_REO_queue_ext_descriptor > 106 107 108 109 <enum 10 Receive_buffer > 110 111 112 113 <enum 11 Idle_link_list_entry> 114 115 116 117 <legal 0-11> 118 119 reserved_0a 120 121 <legal 0> 122 */ 123 124 125 /* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER 126 127 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 128 129 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 130 131 132 133 The owner of this data structure: 134 135 <enum 0 WBM_owned> Buffer Manager currently owns this 136 data structure. 137 138 <enum 1 SW_OR_FW_owned> Software of FW currently owns 139 this data structure. 140 141 <enum 2 TQM_owned> Transmit Queue Manager currently owns 142 this data structure. 143 144 <enum 3 RXDMA_owned> Receive DMA currently owns this 145 data structure. 146 147 <enum 4 REO_owned> Reorder currently owns this data 148 structure. 149 150 <enum 5 SWITCH_owned> SWITCH currently owns this data 151 structure. 152 153 154 155 <legal 0-5> 156 */ 157 #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 158 #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 159 #define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f 160 161 /* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE 162 163 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 164 165 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 166 167 168 169 Field describing what contents format is of this 170 descriptor 171 172 173 174 <enum 0 Transmit_MSDU_Link_descriptor > 175 176 <enum 1 Transmit_MPDU_Link_descriptor > 177 178 <enum 2 Transmit_MPDU_Queue_head_descriptor> 179 180 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 181 182 <enum 4 Transmit_flow_descriptor> 183 184 <enum 5 Transmit_buffer > NOT TO BE USED: 185 186 187 188 <enum 6 Receive_MSDU_Link_descriptor > 189 190 <enum 7 Receive_MPDU_Link_descriptor > 191 192 <enum 8 Receive_REO_queue_descriptor > 193 194 <enum 9 Receive_REO_queue_ext_descriptor > 195 196 197 198 <enum 10 Receive_buffer > 199 200 201 202 <enum 11 Idle_link_list_entry> 203 204 205 206 <legal 0-11> 207 */ 208 #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 209 #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 210 #define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 211 212 /* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A 213 214 <legal 0> 215 */ 216 #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 217 #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 218 #define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 219 220 221 #endif // _UNIFORM_DESCRIPTOR_HEADER_H_ 222