1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef __WCSS_SEQ_BASE_H__ 18*5113495bSYour Name #define __WCSS_SEQ_BASE_H__ 19*5113495bSYour Name 20*5113495bSYour Name #ifdef SCALE_INCLUDES 21*5113495bSYour Name #include "HALhwio.h" 22*5113495bSYour Name #else 23*5113495bSYour Name #include "msmhwio.h" 24*5113495bSYour Name #endif 25*5113495bSYour Name 26*5113495bSYour Name 27*5113495bSYour Name #include "wcss_seq_hwiobase_ext.h" 28*5113495bSYour Name #define SOC_WCSS_BASE_ADDR 0x00000000 29*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 30*5113495bSYour Name // Instance Relative Offsets from Block wcss 31*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 32*5113495bSYour Name 33*5113495bSYour Name #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 34*5113495bSYour Name #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 35*5113495bSYour Name #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 36*5113495bSYour Name #define SEQ_WCSS_PHYA_OFFSET 0x00300000 37*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 38*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 39*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 40*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 41*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 42*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 43*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 44*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER0_REG_MAP_OFFSET 0x00381800 45*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 46*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00382c00 47*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC6_REG_MAP_OFFSET 0x00383000 48*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER1_REG_MAP_OFFSET 0x00383400 49*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 50*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 51*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 52*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 53*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 54*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 55*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 56*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 57*5113495bSYour Name #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 58*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 59*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 60*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 61*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 62*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 63*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 64*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 65*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 66*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 67*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 68*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 69*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 70*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 71*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 72*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 73*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 74*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 75*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 76*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 77*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 78*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 79*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6a00 80*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 81*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 82*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x005da000 83*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x005da000 84*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 85*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 86*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 87*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 88*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1000 89*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1300 90*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x005e1600 91*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x005e1640 92*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 93*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 94*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 95*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 96*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9000 97*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9300 98*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x005e9600 99*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x005e9640 100*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 101*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 102*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 103*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 104*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x005f1000 105*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x005f1300 106*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x005f1600 107*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x005f1640 108*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 109*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 110*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 111*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 112*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x005f9000 113*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x005f9300 114*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x005f9600 115*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x005f9640 116*5113495bSYour Name #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 117*5113495bSYour Name #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 118*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 119*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 120*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 121*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 122*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 123*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 124*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 125*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 126*5113495bSYour Name #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 127*5113495bSYour Name #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 128*5113495bSYour Name #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 129*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 130*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 131*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 132*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_CCE_TCL_REG_OFFSET 0x00a4a000 133*5113495bSYour Name #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 134*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 135*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 136*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 137*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 138*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 139*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 140*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 141*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 142*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 143*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 144*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 145*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 146*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 147*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 148*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 149*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 150*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 151*5113495bSYour Name #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 152*5113495bSYour Name #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 153*5113495bSYour Name #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 154*5113495bSYour Name #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 155*5113495bSYour Name #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 156*5113495bSYour Name #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 157*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000 158*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 159*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80080 160*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x00b800c0 161*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00b80340 162*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b803bc 163*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 164*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00b80800 165*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00b80840 166*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00b80880 167*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x00b808c0 168*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00b80900 169*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b8099c 170*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000 171*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81080 172*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x00b810c0 173*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00b81340 174*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b813bc 175*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400 176*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00b81800 177*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00b81840 178*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00b81880 179*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x00b818c0 180*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00b81900 181*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b8199c 182*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH2_OFFSET 0x00b82000 183*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_CH2_OFFSET 0x00b82080 184*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET 0x00b820c0 185*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH2_OFFSET 0x00b82340 186*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET 0x00b823bc 187*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_CH2_OFFSET 0x00b82400 188*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET 0x00b82800 189*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET 0x00b82840 190*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET 0x00b82880 191*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET 0x00b828c0 192*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET 0x00b82900 193*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET 0x00b8299c 194*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH3_OFFSET 0x00b83000 195*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_CH3_OFFSET 0x00b83080 196*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET 0x00b830c0 197*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH3_OFFSET 0x00b83340 198*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET 0x00b833bc 199*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_CH3_OFFSET 0x00b83400 200*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET 0x00b83800 201*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET 0x00b83840 202*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET 0x00b83880 203*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET 0x00b838c0 204*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET 0x00b83900 205*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET 0x00b8399c 206*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000 207*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080 208*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 209*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 210*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_OFFSET 0x00b8d400 211*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET 0x00b8d800 212*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET 0x00b8d840 213*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET 0x00b8d880 214*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET 0x00b8d8c0 215*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_RO_OFFSET 0x00b8d900 216*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_BBCLKGEN_OFFSET 0x00b8d99c 217*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_ICIC_CTRL_OFFSET 0x00b8d9a4 218*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 219*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000 220*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100 221*5113495bSYour Name #define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 222*5113495bSYour Name #define SEQ_WCSS_DBG_OFFSET 0x00b90000 223*5113495bSYour Name #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 224*5113495bSYour Name #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 225*5113495bSYour Name #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 226*5113495bSYour Name #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 227*5113495bSYour Name #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 228*5113495bSYour Name #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 229*5113495bSYour Name #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 230*5113495bSYour Name #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 231*5113495bSYour Name #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 232*5113495bSYour Name #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 233*5113495bSYour Name #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 234*5113495bSYour Name #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 235*5113495bSYour Name #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 236*5113495bSYour Name #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 237*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 238*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 239*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 240*5113495bSYour Name #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 241*5113495bSYour Name #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 242*5113495bSYour Name #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 243*5113495bSYour Name #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 244*5113495bSYour Name #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 245*5113495bSYour Name #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 246*5113495bSYour Name #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 247*5113495bSYour Name #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 248*5113495bSYour Name #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 249*5113495bSYour Name #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 250*5113495bSYour Name #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 251*5113495bSYour Name #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 252*5113495bSYour Name #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 253*5113495bSYour Name #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 254*5113495bSYour Name #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 255*5113495bSYour Name #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 256*5113495bSYour Name #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 257*5113495bSYour Name #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 258*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 259*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 260*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 261*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 262*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 263*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 264*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 265*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 266*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 267*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 268*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 269*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 270*5113495bSYour Name #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 271*5113495bSYour Name #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 272*5113495bSYour Name #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 273*5113495bSYour Name #define SEQ_WCSS_CC_OFFSET 0x00cb0000 274*5113495bSYour Name #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 275*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 276*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 277*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 278*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 279*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 280*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 281*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 282*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 283*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 284*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 285*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 286*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 287*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 288*5113495bSYour Name 289*5113495bSYour Name 290*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 291*5113495bSYour Name // Instance Relative Offsets from Block wfax_top 292*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 293*5113495bSYour Name 294*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 295*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 296*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 297*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 298*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 299*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 300*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 301*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER0_REG_MAP_OFFSET 0x00081800 302*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 303*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00082c00 304*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC6_REG_MAP_OFFSET 0x00083000 305*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER1_REG_MAP_OFFSET 0x00083400 306*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 307*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 308*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 309*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 310*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 311*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 312*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 313*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 314*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 315*5113495bSYour Name #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 316*5113495bSYour Name 317*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 318*5113495bSYour Name // Instance Relative Offsets from Block rfa_from_wsi 319*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 320*5113495bSYour Name 321*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 322*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 323*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 324*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 325*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 326*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 327*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 328*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 329*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 330*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 331*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 332*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 333*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 334*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 335*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 336*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 337*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 338*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 339*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 340*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 341*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016a00 342*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 343*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 344*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000 345*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000 346*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 347*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 348*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 349*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 350*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021000 351*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021300 352*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 353*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 354*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 355*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 356*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 357*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 358*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029000 359*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029300 360*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 361*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 362*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 363*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 364*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 365*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 366*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH2_OFFSET 0x00031000 367*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH2_OFFSET 0x00031300 368*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00031600 369*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH2_OFFSET 0x00031640 370*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 371*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 372*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 373*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 374*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH3_OFFSET 0x00039000 375*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH3_OFFSET 0x00039300 376*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00039600 377*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH3_OFFSET 0x00039640 378*5113495bSYour Name #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 379*5113495bSYour Name 380*5113495bSYour Name 381*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 382*5113495bSYour Name // Instance Relative Offsets from Block rfa_cmn 383*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 384*5113495bSYour Name 385*5113495bSYour Name #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 386*5113495bSYour Name #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 387*5113495bSYour Name #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 388*5113495bSYour Name #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 389*5113495bSYour Name #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 390*5113495bSYour Name #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 391*5113495bSYour Name #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 392*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 393*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 394*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 395*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 396*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 397*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 398*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 399*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 400*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 401*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 402*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 403*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 404*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002a00 405*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 406*5113495bSYour Name #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 407*5113495bSYour Name 408*5113495bSYour Name 409*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 410*5113495bSYour Name // Instance Relative Offsets from Block rfa_pmu 411*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 412*5113495bSYour Name 413*5113495bSYour Name #define SEQ_RFA_PMU_PMU_OFFSET 0x00000000 414*5113495bSYour Name 415*5113495bSYour Name 416*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 417*5113495bSYour Name // Instance Relative Offsets from Block rfa_wl 418*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 419*5113495bSYour Name 420*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 421*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 422*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 423*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001000 424*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001300 425*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 426*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 427*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 428*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 429*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 430*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 431*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009000 432*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009300 433*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 434*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 435*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 436*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 437*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 438*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 439*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET 0x00011000 440*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET 0x00011300 441*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00011600 442*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH2_OFFSET 0x00011640 443*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 444*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 445*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 446*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 447*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET 0x00019000 448*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET 0x00019300 449*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00019600 450*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH3_OFFSET 0x00019640 451*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 452*5113495bSYour Name 453*5113495bSYour Name 454*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 455*5113495bSYour Name // Instance Relative Offsets from Block umac_top_reg 456*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 457*5113495bSYour Name 458*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 459*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 460*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 461*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 462*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 463*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 464*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 465*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 466*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 467*5113495bSYour Name #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 468*5113495bSYour Name #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 469*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 470*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 471*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 472*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_CCE_TCL_REG_OFFSET 0x0004a000 473*5113495bSYour Name 474*5113495bSYour Name 475*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 476*5113495bSYour Name // Instance Relative Offsets from Block cxc_top_reg 477*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 478*5113495bSYour Name 479*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 480*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 481*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 482*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 483*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 484*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 485*5113495bSYour Name 486*5113495bSYour Name 487*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 488*5113495bSYour Name // Instance Relative Offsets from Block wmac_top_reg 489*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 490*5113495bSYour Name 491*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 492*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 493*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 494*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 495*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 496*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 497*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 498*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 499*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 500*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 501*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 502*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 503*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 504*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 505*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 506*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 507*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 508*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 509*5113495bSYour Name 510*5113495bSYour Name 511*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 512*5113495bSYour Name // Instance Relative Offsets from Block msip 513*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 514*5113495bSYour Name 515*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 516*5113495bSYour Name #define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000080 517*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x000000c0 518*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00000340 519*5113495bSYour Name #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000003bc 520*5113495bSYour Name #define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 521*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00000800 522*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00000840 523*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00000880 524*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x000008c0 525*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00000900 526*5113495bSYour Name #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0000099c 527*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000 528*5113495bSYour Name #define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001080 529*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x000010c0 530*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00001340 531*5113495bSYour Name #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000013bc 532*5113495bSYour Name #define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400 533*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00001800 534*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00001840 535*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00001880 536*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x000018c0 537*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00001900 538*5113495bSYour Name #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0000199c 539*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_CH2_OFFSET 0x00002000 540*5113495bSYour Name #define SEQ_MSIP_WL_DAC_CH2_OFFSET 0x00002080 541*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET 0x000020c0 542*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_CH2_OFFSET 0x00002340 543*5113495bSYour Name #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET 0x000023bc 544*5113495bSYour Name #define SEQ_MSIP_WL_ADC_CH2_OFFSET 0x00002400 545*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET 0x00002800 546*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET 0x00002840 547*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET 0x00002880 548*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET 0x000028c0 549*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET 0x00002900 550*5113495bSYour Name #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET 0x0000299c 551*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_CH3_OFFSET 0x00003000 552*5113495bSYour Name #define SEQ_MSIP_WL_DAC_CH3_OFFSET 0x00003080 553*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET 0x000030c0 554*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_CH3_OFFSET 0x00003340 555*5113495bSYour Name #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET 0x000033bc 556*5113495bSYour Name #define SEQ_MSIP_WL_ADC_CH3_OFFSET 0x00003400 557*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET 0x00003800 558*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET 0x00003840 559*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET 0x00003880 560*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET 0x000038c0 561*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET 0x00003900 562*5113495bSYour Name #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET 0x0000399c 563*5113495bSYour Name #define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000 564*5113495bSYour Name #define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 565*5113495bSYour Name #define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 566*5113495bSYour Name #define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 567*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_OFFSET 0x0000d400 568*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET 0x0000d800 569*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET 0x0000d840 570*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET 0x0000d880 571*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET 0x0000d8c0 572*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_POSTPROC_RO_OFFSET 0x0000d900 573*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_BBCLKGEN_OFFSET 0x0000d99c 574*5113495bSYour Name #define SEQ_MSIP_WL_ICIC_CTRL_OFFSET 0x0000d9a4 575*5113495bSYour Name #define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 576*5113495bSYour Name #define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 577*5113495bSYour Name #define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100 578*5113495bSYour Name #define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 579*5113495bSYour Name 580*5113495bSYour Name 581*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 582*5113495bSYour Name // Instance Relative Offsets from Block wcssdbg 583*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 584*5113495bSYour Name 585*5113495bSYour Name #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 586*5113495bSYour Name #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 587*5113495bSYour Name #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 588*5113495bSYour Name #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 589*5113495bSYour Name #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 590*5113495bSYour Name #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 591*5113495bSYour Name #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 592*5113495bSYour Name #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 593*5113495bSYour Name #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 594*5113495bSYour Name #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 595*5113495bSYour Name #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 596*5113495bSYour Name #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 597*5113495bSYour Name #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 598*5113495bSYour Name #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 599*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 600*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 601*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 602*5113495bSYour Name #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 603*5113495bSYour Name #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 604*5113495bSYour Name #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 605*5113495bSYour Name #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 606*5113495bSYour Name #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 607*5113495bSYour Name #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 608*5113495bSYour Name #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 609*5113495bSYour Name #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 610*5113495bSYour Name #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 611*5113495bSYour Name #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 612*5113495bSYour Name #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 613*5113495bSYour Name #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 614*5113495bSYour Name #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 615*5113495bSYour Name #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 616*5113495bSYour Name #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 617*5113495bSYour Name #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 618*5113495bSYour Name #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 619*5113495bSYour Name #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 620*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 621*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 622*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 623*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 624*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 625*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 626*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 627*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 628*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 629*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 630*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 631*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 632*5113495bSYour Name #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 633*5113495bSYour Name 634*5113495bSYour Name 635*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 636*5113495bSYour Name // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 637*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 638*5113495bSYour Name 639*5113495bSYour Name #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 640*5113495bSYour Name #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 641*5113495bSYour Name 642*5113495bSYour Name 643*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 644*5113495bSYour Name // Instance Relative Offsets from Block tpdm_atb128_cmb64 645*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 646*5113495bSYour Name 647*5113495bSYour Name #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 648*5113495bSYour Name #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 649*5113495bSYour Name 650*5113495bSYour Name 651*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 652*5113495bSYour Name // Instance Relative Offsets from Block phya_dbg 653*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 654*5113495bSYour Name 655*5113495bSYour Name #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 656*5113495bSYour Name #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 657*5113495bSYour Name #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 658*5113495bSYour Name #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 659*5113495bSYour Name #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 660*5113495bSYour Name #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 661*5113495bSYour Name #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 662*5113495bSYour Name #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 663*5113495bSYour Name #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 664*5113495bSYour Name #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 665*5113495bSYour Name #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 666*5113495bSYour Name 667*5113495bSYour Name 668*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 669*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_wlan_pine 670*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 671*5113495bSYour Name 672*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_OFFSET 0x00000000 673*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 674*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 675*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 676*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 677*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 678*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 679*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 680*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 681*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 682*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 683*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 684*5113495bSYour Name 685*5113495bSYour Name 686*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 687*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss 688*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 689*5113495bSYour Name 690*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 691*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 692*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 693*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 694*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 695*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 696*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 697*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 698*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 699*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 700*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 701*5113495bSYour Name 702*5113495bSYour Name 703*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 704*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_public 705*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 706*5113495bSYour Name 707*5113495bSYour Name #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 708*5113495bSYour Name 709*5113495bSYour Name 710*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 711*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_private 712*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 713*5113495bSYour Name 714*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 715*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 716*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 717*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 718*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 719*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 720*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 721*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 722*5113495bSYour Name 723*5113495bSYour Name 724*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 725*5113495bSYour Name // Instance Relative Offsets from Block q6ss_rscc 726*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 727*5113495bSYour Name 728*5113495bSYour Name #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 729*5113495bSYour Name 730*5113495bSYour Name 731*5113495bSYour Name #endif 732*5113495bSYour Name 733