1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WCSS_SEQ_BASE_H__ 18 #define __WCSS_SEQ_BASE_H__ 19 20 #ifdef SCALE_INCLUDES 21 #include "HALhwio.h" 22 #else 23 #include "msmhwio.h" 24 #endif 25 26 27 #include "wcss_seq_hwiobase_ext.h" 28 #define SOC_WCSS_BASE_ADDR 0x00000000 29 /////////////////////////////////////////////////////////////////////////////////////////////// 30 // Instance Relative Offsets from Block wcss 31 /////////////////////////////////////////////////////////////////////////////////////////////// 32 33 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 34 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 35 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 36 #define SEQ_WCSS_PHYA_OFFSET 0x00300000 37 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 38 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 39 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 40 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 41 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 42 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 43 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 44 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER0_REG_MAP_OFFSET 0x00381800 45 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 46 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00382c00 47 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC6_REG_MAP_OFFSET 0x00383000 48 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER1_REG_MAP_OFFSET 0x00383400 49 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 50 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 51 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 52 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 53 #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 54 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 55 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 56 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 57 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 58 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 59 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 60 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 61 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 62 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 63 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 64 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 65 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 66 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 67 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 68 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 69 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 70 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 71 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 72 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 73 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 74 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 75 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 76 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 77 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 78 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 79 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6a00 80 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 81 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 82 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x005da000 83 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x005da000 84 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 85 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 86 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 87 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 88 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1000 89 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1300 90 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x005e1600 91 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x005e1640 92 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 93 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 94 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 95 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 96 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9000 97 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9300 98 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x005e9600 99 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x005e9640 100 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 101 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 102 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 103 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 104 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x005f1000 105 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x005f1300 106 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x005f1600 107 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x005f1640 108 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 109 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 110 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 111 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 112 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x005f9000 113 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x005f9300 114 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x005f9600 115 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x005f9640 116 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 117 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 118 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 119 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 120 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 121 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 122 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 123 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 124 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 125 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 126 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 127 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 128 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 129 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 130 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 131 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 132 #define SEQ_WCSS_UMAC_MAC_CCE_TCL_REG_OFFSET 0x00a4a000 133 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 134 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 135 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 136 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 137 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 138 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 139 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 140 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 141 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 142 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 143 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 144 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 145 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 146 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 147 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 148 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 149 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 150 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 151 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 152 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 153 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 154 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 155 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 156 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 157 #define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000 158 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 159 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80080 160 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x00b800c0 161 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00b80340 162 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b803bc 163 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 164 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00b80800 165 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00b80840 166 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00b80880 167 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x00b808c0 168 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00b80900 169 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b8099c 170 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000 171 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81080 172 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x00b810c0 173 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00b81340 174 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b813bc 175 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400 176 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00b81800 177 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00b81840 178 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00b81880 179 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x00b818c0 180 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00b81900 181 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b8199c 182 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH2_OFFSET 0x00b82000 183 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH2_OFFSET 0x00b82080 184 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET 0x00b820c0 185 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH2_OFFSET 0x00b82340 186 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET 0x00b823bc 187 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH2_OFFSET 0x00b82400 188 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET 0x00b82800 189 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET 0x00b82840 190 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET 0x00b82880 191 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET 0x00b828c0 192 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET 0x00b82900 193 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET 0x00b8299c 194 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH3_OFFSET 0x00b83000 195 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH3_OFFSET 0x00b83080 196 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET 0x00b830c0 197 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH3_OFFSET 0x00b83340 198 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET 0x00b833bc 199 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH3_OFFSET 0x00b83400 200 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET 0x00b83800 201 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET 0x00b83840 202 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET 0x00b83880 203 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET 0x00b838c0 204 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET 0x00b83900 205 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET 0x00b8399c 206 #define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000 207 #define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080 208 #define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 209 #define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 210 #define SEQ_WCSS_WL_MSIP_WL_ICIC_OFFSET 0x00b8d400 211 #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET 0x00b8d800 212 #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET 0x00b8d840 213 #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET 0x00b8d880 214 #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET 0x00b8d8c0 215 #define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_RO_OFFSET 0x00b8d900 216 #define SEQ_WCSS_WL_MSIP_WL_ICIC_BBCLKGEN_OFFSET 0x00b8d99c 217 #define SEQ_WCSS_WL_MSIP_WL_ICIC_CTRL_OFFSET 0x00b8d9a4 218 #define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 219 #define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000 220 #define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100 221 #define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 222 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 223 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 224 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 225 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 226 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 227 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 228 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 229 #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 230 #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 231 #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 232 #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 233 #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 234 #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 235 #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 236 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 237 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 238 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 239 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 240 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 241 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 242 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 243 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 244 #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 245 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 246 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 247 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 248 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 249 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 250 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 251 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 252 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 253 #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 254 #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 255 #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 256 #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 257 #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 258 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 259 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 260 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 261 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 262 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 263 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 264 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 265 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 266 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 267 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 268 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 269 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 270 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 271 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 272 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 273 #define SEQ_WCSS_CC_OFFSET 0x00cb0000 274 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 275 #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 276 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 277 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 278 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 279 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 280 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 281 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 282 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 283 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 284 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 285 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 286 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 287 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 288 289 290 /////////////////////////////////////////////////////////////////////////////////////////////// 291 // Instance Relative Offsets from Block wfax_top 292 /////////////////////////////////////////////////////////////////////////////////////////////// 293 294 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 295 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 296 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 297 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 298 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 299 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 300 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 301 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER0_REG_MAP_OFFSET 0x00081800 302 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 303 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC5_REG_MAP_OFFSET 0x00082c00 304 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC6_REG_MAP_OFFSET 0x00083000 305 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER1_REG_MAP_OFFSET 0x00083400 306 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 307 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 308 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 309 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 310 #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 311 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 312 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 313 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 314 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 315 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 316 317 /////////////////////////////////////////////////////////////////////////////////////////////// 318 // Instance Relative Offsets from Block rfa_from_wsi 319 /////////////////////////////////////////////////////////////////////////////////////////////// 320 321 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 322 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 323 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 324 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 325 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 326 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 327 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 328 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 329 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 330 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 331 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 332 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 333 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 334 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 335 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 336 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 337 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 338 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 339 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 340 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 341 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016a00 342 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 343 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 344 #define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000 345 #define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000 346 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 347 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 348 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 349 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 350 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021000 351 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021300 352 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 353 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 354 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 355 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 356 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 357 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 358 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029000 359 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029300 360 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 361 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 362 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 363 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 364 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 365 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 366 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH2_OFFSET 0x00031000 367 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH2_OFFSET 0x00031300 368 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00031600 369 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH2_OFFSET 0x00031640 370 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 371 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 372 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 373 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 374 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH3_OFFSET 0x00039000 375 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH3_OFFSET 0x00039300 376 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00039600 377 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH3_OFFSET 0x00039640 378 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 379 380 381 /////////////////////////////////////////////////////////////////////////////////////////////// 382 // Instance Relative Offsets from Block rfa_cmn 383 /////////////////////////////////////////////////////////////////////////////////////////////// 384 385 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 386 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 387 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 388 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 389 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 390 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 391 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 392 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 393 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 394 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 395 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 396 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 397 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 398 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 399 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 400 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 401 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 402 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 403 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 404 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002a00 405 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 406 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 407 408 409 /////////////////////////////////////////////////////////////////////////////////////////////// 410 // Instance Relative Offsets from Block rfa_pmu 411 /////////////////////////////////////////////////////////////////////////////////////////////// 412 413 #define SEQ_RFA_PMU_PMU_OFFSET 0x00000000 414 415 416 /////////////////////////////////////////////////////////////////////////////////////////////// 417 // Instance Relative Offsets from Block rfa_wl 418 /////////////////////////////////////////////////////////////////////////////////////////////// 419 420 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 421 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 422 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 423 #define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001000 424 #define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001300 425 #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 426 #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 427 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 428 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 429 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 430 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 431 #define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009000 432 #define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009300 433 #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 434 #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 435 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 436 #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 437 #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 438 #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 439 #define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET 0x00011000 440 #define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET 0x00011300 441 #define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00011600 442 #define SEQ_RFA_WL_WL_LO_CH2_OFFSET 0x00011640 443 #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 444 #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 445 #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 446 #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 447 #define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET 0x00019000 448 #define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET 0x00019300 449 #define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00019600 450 #define SEQ_RFA_WL_WL_LO_CH3_OFFSET 0x00019640 451 #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 452 453 454 /////////////////////////////////////////////////////////////////////////////////////////////// 455 // Instance Relative Offsets from Block umac_top_reg 456 /////////////////////////////////////////////////////////////////////////////////////////////// 457 458 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 459 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 460 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 461 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 462 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 463 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 464 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 465 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 466 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 467 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 468 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 469 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 470 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 471 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 472 #define SEQ_UMAC_TOP_REG_MAC_CCE_TCL_REG_OFFSET 0x0004a000 473 474 475 /////////////////////////////////////////////////////////////////////////////////////////////// 476 // Instance Relative Offsets from Block cxc_top_reg 477 /////////////////////////////////////////////////////////////////////////////////////////////// 478 479 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 480 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 481 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 482 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 483 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 484 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 485 486 487 /////////////////////////////////////////////////////////////////////////////////////////////// 488 // Instance Relative Offsets from Block wmac_top_reg 489 /////////////////////////////////////////////////////////////////////////////////////////////// 490 491 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 492 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 493 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 494 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 495 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 496 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 497 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 498 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 499 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 500 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 501 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 502 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 503 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 504 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 505 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 506 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 507 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 508 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 509 510 511 /////////////////////////////////////////////////////////////////////////////////////////////// 512 // Instance Relative Offsets from Block msip 513 /////////////////////////////////////////////////////////////////////////////////////////////// 514 515 #define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 516 #define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000080 517 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x000000c0 518 #define SEQ_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00000340 519 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000003bc 520 #define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 521 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00000800 522 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00000840 523 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00000880 524 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x000008c0 525 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00000900 526 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0000099c 527 #define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000 528 #define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001080 529 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x000010c0 530 #define SEQ_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00001340 531 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000013bc 532 #define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400 533 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00001800 534 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00001840 535 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00001880 536 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x000018c0 537 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00001900 538 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0000199c 539 #define SEQ_MSIP_RBIST_TX_CH2_OFFSET 0x00002000 540 #define SEQ_MSIP_WL_DAC_CH2_OFFSET 0x00002080 541 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET 0x000020c0 542 #define SEQ_MSIP_WL_DAC_MISC_CH2_OFFSET 0x00002340 543 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET 0x000023bc 544 #define SEQ_MSIP_WL_ADC_CH2_OFFSET 0x00002400 545 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET 0x00002800 546 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET 0x00002840 547 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET 0x00002880 548 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET 0x000028c0 549 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET 0x00002900 550 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET 0x0000299c 551 #define SEQ_MSIP_RBIST_TX_CH3_OFFSET 0x00003000 552 #define SEQ_MSIP_WL_DAC_CH3_OFFSET 0x00003080 553 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET 0x000030c0 554 #define SEQ_MSIP_WL_DAC_MISC_CH3_OFFSET 0x00003340 555 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET 0x000033bc 556 #define SEQ_MSIP_WL_ADC_CH3_OFFSET 0x00003400 557 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET 0x00003800 558 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET 0x00003840 559 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET 0x00003880 560 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET 0x000038c0 561 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET 0x00003900 562 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET 0x0000399c 563 #define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000 564 #define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 565 #define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 566 #define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 567 #define SEQ_MSIP_WL_ICIC_OFFSET 0x0000d400 568 #define SEQ_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET 0x0000d800 569 #define SEQ_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET 0x0000d840 570 #define SEQ_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET 0x0000d880 571 #define SEQ_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET 0x0000d8c0 572 #define SEQ_MSIP_WL_ICIC_POSTPROC_RO_OFFSET 0x0000d900 573 #define SEQ_MSIP_WL_ICIC_BBCLKGEN_OFFSET 0x0000d99c 574 #define SEQ_MSIP_WL_ICIC_CTRL_OFFSET 0x0000d9a4 575 #define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 576 #define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 577 #define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100 578 #define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 579 580 581 /////////////////////////////////////////////////////////////////////////////////////////////// 582 // Instance Relative Offsets from Block wcssdbg 583 /////////////////////////////////////////////////////////////////////////////////////////////// 584 585 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 586 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 587 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 588 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 589 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 590 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 591 #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 592 #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 593 #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 594 #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 595 #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 596 #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 597 #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 598 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 599 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 600 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 601 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 602 #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 603 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 604 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 605 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 606 #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 607 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 608 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 609 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 610 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 611 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 612 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 613 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 614 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 615 #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 616 #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 617 #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 618 #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 619 #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 620 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 621 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 622 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 623 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 624 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 625 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 626 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 627 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 628 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 629 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 630 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 631 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 632 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 633 634 635 /////////////////////////////////////////////////////////////////////////////////////////////// 636 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 637 /////////////////////////////////////////////////////////////////////////////////////////////// 638 639 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 640 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 641 642 643 /////////////////////////////////////////////////////////////////////////////////////////////// 644 // Instance Relative Offsets from Block tpdm_atb128_cmb64 645 /////////////////////////////////////////////////////////////////////////////////////////////// 646 647 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 648 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 649 650 651 /////////////////////////////////////////////////////////////////////////////////////////////// 652 // Instance Relative Offsets from Block phya_dbg 653 /////////////////////////////////////////////////////////////////////////////////////////////// 654 655 #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 656 #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 657 #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 658 #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 659 #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 660 #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 661 #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 662 #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 663 #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 664 #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 665 #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 666 667 668 /////////////////////////////////////////////////////////////////////////////////////////////// 669 // Instance Relative Offsets from Block qdsp6v67ss_wlan_pine 670 /////////////////////////////////////////////////////////////////////////////////////////////// 671 672 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_OFFSET 0x00000000 673 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 674 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 675 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 676 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 677 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 678 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 679 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 680 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 681 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 682 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 683 #define SEQ_QDSP6V67SS_WLAN_PINE_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 684 685 686 /////////////////////////////////////////////////////////////////////////////////////////////// 687 // Instance Relative Offsets from Block qdsp6v67ss 688 /////////////////////////////////////////////////////////////////////////////////////////////// 689 690 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 691 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 692 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 693 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 694 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 695 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 696 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 697 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 698 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 699 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 700 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 701 702 703 /////////////////////////////////////////////////////////////////////////////////////////////// 704 // Instance Relative Offsets from Block qdsp6v67ss_public 705 /////////////////////////////////////////////////////////////////////////////////////////////// 706 707 #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 708 709 710 /////////////////////////////////////////////////////////////////////////////////////////////// 711 // Instance Relative Offsets from Block qdsp6v67ss_private 712 /////////////////////////////////////////////////////////////////////////////////////////////// 713 714 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 715 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 716 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 717 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 718 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 719 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 720 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 721 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 722 723 724 /////////////////////////////////////////////////////////////////////////////////////////////// 725 // Instance Relative Offsets from Block q6ss_rscc 726 /////////////////////////////////////////////////////////////////////////////////////////////// 727 728 #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 729 730 731 #endif 732 733