1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _COEX_TX_STATUS_H_ 27 #define _COEX_TX_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_COEX_TX_STATUS 4 32 33 #define NUM_OF_QWORDS_COEX_TX_STATUS 2 34 35 36 struct coex_tx_status { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t reserved_0a : 7, 39 tx_bw : 3, 40 tx_status_reason : 3, 41 tx_wait_ack : 1, 42 fes_tx_is_gen_frame : 1, 43 sch_tx_burst_ongoing : 1, 44 current_tx_duration : 16; 45 uint32_t next_rx_active_time : 16, 46 remaining_fes_time : 16; 47 uint32_t tx_antenna_mask : 8, 48 shared_ant_tx_pwr : 8, 49 other_ant_tx_pwr : 8, 50 reserved_2 : 8; 51 uint32_t tlv64_padding : 32; 52 #else 53 uint32_t current_tx_duration : 16, 54 sch_tx_burst_ongoing : 1, 55 fes_tx_is_gen_frame : 1, 56 tx_wait_ack : 1, 57 tx_status_reason : 3, 58 tx_bw : 3, 59 reserved_0a : 7; 60 uint32_t remaining_fes_time : 16, 61 next_rx_active_time : 16; 62 uint32_t reserved_2 : 8, 63 other_ant_tx_pwr : 8, 64 shared_ant_tx_pwr : 8, 65 tx_antenna_mask : 8; 66 uint32_t tlv64_padding : 32; 67 #endif 68 }; 69 70 71 72 73 #define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 74 #define COEX_TX_STATUS_RESERVED_0A_LSB 0 75 #define COEX_TX_STATUS_RESERVED_0A_MSB 6 76 #define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f 77 78 79 80 81 #define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 82 #define COEX_TX_STATUS_TX_BW_LSB 7 83 #define COEX_TX_STATUS_TX_BW_MSB 9 84 #define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 85 86 87 88 89 #define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 90 #define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 91 #define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 92 #define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 93 94 95 96 97 #define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 98 #define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 99 #define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 100 #define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 101 102 103 104 105 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 106 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 107 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 108 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 109 110 111 112 113 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 114 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 115 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 116 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 117 118 119 120 121 #define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 122 #define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 123 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 124 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 125 126 127 128 129 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 130 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 131 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 132 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 133 134 135 136 137 #define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 138 #define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 139 #define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 140 #define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 141 142 143 144 145 #define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 146 #define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 147 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 148 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff 149 150 151 152 153 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 154 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 155 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 156 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 157 158 159 160 161 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 162 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 163 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 164 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 165 166 167 168 169 #define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 170 #define COEX_TX_STATUS_RESERVED_2_LSB 24 171 #define COEX_TX_STATUS_RESERVED_2_MSB 31 172 #define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 173 174 175 176 177 #define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 178 #define COEX_TX_STATUS_TLV64_PADDING_LSB 32 179 #define COEX_TX_STATUS_TLV64_PADDING_MSB 63 180 #define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 181 182 183 184 #endif 185