1 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 21 22 23 24 25 26 27 #ifndef _EHT_SIG_USR_OFDMA_INFO_H_ 28 #define _EHT_SIG_USR_OFDMA_INFO_H_ 29 #if !defined(__ASSEMBLER__) 30 #endif 31 32 #define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 33 34 35 struct eht_sig_usr_ofdma_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t sta_id : 11, // [10:0] 38 sta_mcs : 4, // [14:11] 39 validate_0a : 1, // [15:15] 40 nss : 4, // [19:16] 41 txbf : 1, // [20:20] 42 sta_coding : 1, // [21:21] 43 reserved_0b : 1, // [22:22] 44 rx_integrity_check_passed : 1, // [23:23] 45 subband80_cc_mask : 8; // [31:24] 46 uint32_t user_order_subband80_0 : 8, // [7:0] 47 user_order_subband80_1 : 8, // [15:8] 48 user_order_subband80_2 : 8, // [23:16] 49 user_order_subband80_3 : 8; // [31:24] 50 #else 51 uint32_t subband80_cc_mask : 8, // [31:24] 52 rx_integrity_check_passed : 1, // [23:23] 53 reserved_0b : 1, // [22:22] 54 sta_coding : 1, // [21:21] 55 txbf : 1, // [20:20] 56 nss : 4, // [19:16] 57 validate_0a : 1, // [15:15] 58 sta_mcs : 4, // [14:11] 59 sta_id : 11; // [10:0] 60 uint32_t user_order_subband80_3 : 8, // [31:24] 61 user_order_subband80_2 : 8, // [23:16] 62 user_order_subband80_1 : 8, // [15:8] 63 user_order_subband80_0 : 8; // [7:0] 64 #endif 65 }; 66 67 68 69 70 #define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 71 #define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 72 #define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 73 #define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff 74 75 76 77 78 #define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 79 #define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 80 #define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 81 #define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 82 83 84 85 86 #define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 87 #define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 88 #define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 89 #define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 90 91 92 93 94 #define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 95 #define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 96 #define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 97 #define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 98 99 100 101 102 #define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 103 #define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 104 #define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 105 #define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 106 107 108 109 110 #define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 111 #define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 112 #define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 113 #define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 114 115 116 117 118 #define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 119 #define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 120 #define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 121 #define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 122 123 124 125 126 #define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 127 #define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 128 #define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 129 #define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 130 131 132 133 134 #define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 135 #define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 136 #define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 137 #define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 138 139 140 141 142 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 143 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 144 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 145 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff 146 147 148 149 150 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 151 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 152 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 153 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 154 155 156 157 158 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 159 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 160 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 161 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 162 163 164 165 166 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 167 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 168 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 169 #define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 170 171 172 173 174 #endif 175