1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _HE_SIG_B2_OFDMA_INFO_H_ 27 #define _HE_SIG_B2_OFDMA_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 32 33 34 struct he_sig_b2_ofdma_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t sta_id : 11, 37 nsts : 3, 38 txbf : 1, 39 sta_mcs : 4, 40 sta_dcm : 1, 41 sta_coding : 1, 42 reserved_0 : 10, 43 rx_integrity_check_passed : 1; 44 uint32_t user_order : 8, 45 cc_mask : 8, 46 reserved_1a : 16; 47 #else 48 uint32_t rx_integrity_check_passed : 1, 49 reserved_0 : 10, 50 sta_coding : 1, 51 sta_dcm : 1, 52 sta_mcs : 4, 53 txbf : 1, 54 nsts : 3, 55 sta_id : 11; 56 uint32_t reserved_1a : 16, 57 cc_mask : 8, 58 user_order : 8; 59 #endif 60 }; 61 62 63 64 65 #define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 66 #define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 67 #define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 68 #define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff 69 70 71 72 73 #define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 74 #define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 75 #define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 76 #define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 77 78 79 80 81 #define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 82 #define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 83 #define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 84 #define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 85 86 87 88 89 #define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 90 #define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 91 #define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 92 #define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 93 94 95 96 97 #define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 98 #define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 99 #define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 100 #define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 101 102 103 104 105 #define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 106 #define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 107 #define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 108 #define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 109 110 111 112 113 #define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 114 #define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 115 #define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 116 #define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 117 118 119 120 121 #define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 122 #define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 123 #define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 124 #define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 125 126 127 128 129 #define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 130 #define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 131 #define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 132 #define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff 133 134 135 136 137 #define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 138 #define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 139 #define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 140 #define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 141 142 143 144 145 #define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 146 #define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 147 #define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 148 #define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 149 150 151 152 #endif 153