xref: /wlan-driver/fw-api/hw/qcn9224/v1/mactx_he_sig_b1_mu.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
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2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _MACTX_HE_SIG_B1_MU_H_
27 #define _MACTX_HE_SIG_B1_MU_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "he_sig_b1_mu_info.h"
32 #define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
33 
34 #define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
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36 
37 struct mactx_he_sig_b1_mu {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
40              uint32_t tlv64_padding                                           : 32;
41 #else
42              struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
43              uint32_t tlv64_padding                                           : 32;
44 #endif
45 };
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53 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
54 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
55 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
56 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
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61 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
62 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
63 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
64 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
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69 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
70 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
71 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
72 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
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77 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
78 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
79 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
80 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
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83 
84 #endif
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