xref: /wlan-driver/fw-api/hw/qcn9224/v1/mactx_phy_desc.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name 
20*5113495bSYour Name 
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name 
24*5113495bSYour Name 
25*5113495bSYour Name 
26*5113495bSYour Name #ifndef _MACTX_PHY_DESC_H_
27*5113495bSYour Name #define _MACTX_PHY_DESC_H_
28*5113495bSYour Name #if !defined(__ASSEMBLER__)
29*5113495bSYour Name #endif
30*5113495bSYour Name 
31*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_PHY_DESC 4
32*5113495bSYour Name 
33*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_PHY_DESC 2
34*5113495bSYour Name 
35*5113495bSYour Name 
36*5113495bSYour Name struct mactx_phy_desc {
37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
38*5113495bSYour Name              uint32_t reserved_0a                                             : 16,
39*5113495bSYour Name                       bf_type                                                 :  2,
40*5113495bSYour Name                       wait_sifs                                               :  2,
41*5113495bSYour Name                       dot11b_preamble_type                                    :  1,
42*5113495bSYour Name                       pkt_type                                                :  4,
43*5113495bSYour Name                       su_or_mu                                                :  2,
44*5113495bSYour Name                       mu_type                                                 :  1,
45*5113495bSYour Name                       bandwidth                                               :  3,
46*5113495bSYour Name                       channel_capture                                         :  1;
47*5113495bSYour Name              uint32_t mcs                                                     :  4,
48*5113495bSYour Name                       global_ofdma_mimo_enable                                :  1,
49*5113495bSYour Name                       reserved_1a                                             :  1,
50*5113495bSYour Name                       stbc                                                    :  1,
51*5113495bSYour Name                       dot11ax_su_extended                                     :  1,
52*5113495bSYour Name                       dot11ax_trigger_frame_embedded                          :  1,
53*5113495bSYour Name                       tx_pwr_shared                                           :  8,
54*5113495bSYour Name                       tx_pwr_unshared                                         :  8,
55*5113495bSYour Name                       measure_power                                           :  1,
56*5113495bSYour Name                       tpc_glut_self_cal                                       :  1,
57*5113495bSYour Name                       back_to_back_transmission_expected                      :  1,
58*5113495bSYour Name                       heavy_clip_nss                                          :  3,
59*5113495bSYour Name                       txbf_per_packet_no_csd_no_walsh                         :  1;
60*5113495bSYour Name              uint32_t ndp                                                     :  2,
61*5113495bSYour Name                       ul_flag                                                 :  1,
62*5113495bSYour Name                       triggered                                               :  1,
63*5113495bSYour Name                       ap_pkt_bw                                               :  3,
64*5113495bSYour Name                       ru_position_start                                       :  8,
65*5113495bSYour Name                       pcu_ppdu_setup_start_reason                             :  3,
66*5113495bSYour Name                       tlv_source                                              :  1,
67*5113495bSYour Name                       reserved_2a                                             :  2,
68*5113495bSYour Name                       nss                                                     :  3,
69*5113495bSYour Name                       stream_offset                                           :  3,
70*5113495bSYour Name                       reserved_2b                                             :  2,
71*5113495bSYour Name                       clpc_enable                                             :  1,
72*5113495bSYour Name                       mu_ndp                                                  :  1,
73*5113495bSYour Name                       response_expected                                       :  1;
74*5113495bSYour Name              uint32_t rx_chain_mask                                           :  8,
75*5113495bSYour Name                       rx_chain_mask_valid                                     :  1,
76*5113495bSYour Name                       ant_sel_valid                                           :  1,
77*5113495bSYour Name                       ant_sel                                                 :  1,
78*5113495bSYour Name                       cp_setting                                              :  2,
79*5113495bSYour Name                       he_ppdu_subtype                                         :  2,
80*5113495bSYour Name                       active_channel                                          :  3,
81*5113495bSYour Name                       generate_phyrx_tx_start_timing                          :  1,
82*5113495bSYour Name                       ltf_size                                                :  2,
83*5113495bSYour Name                       ru_size_updated_v2                                      :  4,
84*5113495bSYour Name                       reserved_3c                                             :  1,
85*5113495bSYour Name                       u_sig_puncture_pattern_encoding                         :  6;
86*5113495bSYour Name #else
87*5113495bSYour Name              uint32_t channel_capture                                         :  1,
88*5113495bSYour Name                       bandwidth                                               :  3,
89*5113495bSYour Name                       mu_type                                                 :  1,
90*5113495bSYour Name                       su_or_mu                                                :  2,
91*5113495bSYour Name                       pkt_type                                                :  4,
92*5113495bSYour Name                       dot11b_preamble_type                                    :  1,
93*5113495bSYour Name                       wait_sifs                                               :  2,
94*5113495bSYour Name                       bf_type                                                 :  2,
95*5113495bSYour Name                       reserved_0a                                             : 16;
96*5113495bSYour Name              uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
97*5113495bSYour Name                       heavy_clip_nss                                          :  3,
98*5113495bSYour Name                       back_to_back_transmission_expected                      :  1,
99*5113495bSYour Name                       tpc_glut_self_cal                                       :  1,
100*5113495bSYour Name                       measure_power                                           :  1,
101*5113495bSYour Name                       tx_pwr_unshared                                         :  8,
102*5113495bSYour Name                       tx_pwr_shared                                           :  8,
103*5113495bSYour Name                       dot11ax_trigger_frame_embedded                          :  1,
104*5113495bSYour Name                       dot11ax_su_extended                                     :  1,
105*5113495bSYour Name                       stbc                                                    :  1,
106*5113495bSYour Name                       reserved_1a                                             :  1,
107*5113495bSYour Name                       global_ofdma_mimo_enable                                :  1,
108*5113495bSYour Name                       mcs                                                     :  4;
109*5113495bSYour Name              uint32_t response_expected                                       :  1,
110*5113495bSYour Name                       mu_ndp                                                  :  1,
111*5113495bSYour Name                       clpc_enable                                             :  1,
112*5113495bSYour Name                       reserved_2b                                             :  2,
113*5113495bSYour Name                       stream_offset                                           :  3,
114*5113495bSYour Name                       nss                                                     :  3,
115*5113495bSYour Name                       reserved_2a                                             :  2,
116*5113495bSYour Name                       tlv_source                                              :  1,
117*5113495bSYour Name                       pcu_ppdu_setup_start_reason                             :  3,
118*5113495bSYour Name                       ru_position_start                                       :  8,
119*5113495bSYour Name                       ap_pkt_bw                                               :  3,
120*5113495bSYour Name                       triggered                                               :  1,
121*5113495bSYour Name                       ul_flag                                                 :  1,
122*5113495bSYour Name                       ndp                                                     :  2;
123*5113495bSYour Name              uint32_t u_sig_puncture_pattern_encoding                         :  6,
124*5113495bSYour Name                       reserved_3c                                             :  1,
125*5113495bSYour Name                       ru_size_updated_v2                                      :  4,
126*5113495bSYour Name                       ltf_size                                                :  2,
127*5113495bSYour Name                       generate_phyrx_tx_start_timing                          :  1,
128*5113495bSYour Name                       active_channel                                          :  3,
129*5113495bSYour Name                       he_ppdu_subtype                                         :  2,
130*5113495bSYour Name                       cp_setting                                              :  2,
131*5113495bSYour Name                       ant_sel                                                 :  1,
132*5113495bSYour Name                       ant_sel_valid                                           :  1,
133*5113495bSYour Name                       rx_chain_mask_valid                                     :  1,
134*5113495bSYour Name                       rx_chain_mask                                           :  8;
135*5113495bSYour Name #endif
136*5113495bSYour Name };
137*5113495bSYour Name 
138*5113495bSYour Name 
139*5113495bSYour Name 
140*5113495bSYour Name 
141*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x0000000000000000
142*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
143*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
144*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x000000000000ffff
145*5113495bSYour Name 
146*5113495bSYour Name 
147*5113495bSYour Name 
148*5113495bSYour Name 
149*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x0000000000000000
150*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
151*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
152*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x0000000000030000
153*5113495bSYour Name 
154*5113495bSYour Name 
155*5113495bSYour Name 
156*5113495bSYour Name 
157*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x0000000000000000
158*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
159*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
160*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x00000000000c0000
161*5113495bSYour Name 
162*5113495bSYour Name 
163*5113495bSYour Name 
164*5113495bSYour Name 
165*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x0000000000000000
166*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
167*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
168*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x0000000000100000
169*5113495bSYour Name 
170*5113495bSYour Name 
171*5113495bSYour Name 
172*5113495bSYour Name 
173*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x0000000000000000
174*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
175*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
176*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x0000000001e00000
177*5113495bSYour Name 
178*5113495bSYour Name 
179*5113495bSYour Name 
180*5113495bSYour Name 
181*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x0000000000000000
182*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
183*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
184*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x0000000006000000
185*5113495bSYour Name 
186*5113495bSYour Name 
187*5113495bSYour Name 
188*5113495bSYour Name 
189*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x0000000000000000
190*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
191*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
192*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x0000000008000000
193*5113495bSYour Name 
194*5113495bSYour Name 
195*5113495bSYour Name 
196*5113495bSYour Name 
197*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x0000000000000000
198*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
199*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
200*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x0000000070000000
201*5113495bSYour Name 
202*5113495bSYour Name 
203*5113495bSYour Name 
204*5113495bSYour Name 
205*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x0000000000000000
206*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
207*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
208*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x0000000080000000
209*5113495bSYour Name 
210*5113495bSYour Name 
211*5113495bSYour Name 
212*5113495bSYour Name 
213*5113495bSYour Name #define MACTX_PHY_DESC_MCS_OFFSET                                                   0x0000000000000000
214*5113495bSYour Name #define MACTX_PHY_DESC_MCS_LSB                                                      32
215*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MSB                                                      35
216*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MASK                                                     0x0000000f00000000
217*5113495bSYour Name 
218*5113495bSYour Name 
219*5113495bSYour Name 
220*5113495bSYour Name 
221*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x0000000000000000
222*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 36
223*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 36
224*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x0000001000000000
225*5113495bSYour Name 
226*5113495bSYour Name 
227*5113495bSYour Name 
228*5113495bSYour Name 
229*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_OFFSET                                           0x0000000000000000
230*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_LSB                                              37
231*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MSB                                              37
232*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MASK                                             0x0000002000000000
233*5113495bSYour Name 
234*5113495bSYour Name 
235*5113495bSYour Name 
236*5113495bSYour Name 
237*5113495bSYour Name #define MACTX_PHY_DESC_STBC_OFFSET                                                  0x0000000000000000
238*5113495bSYour Name #define MACTX_PHY_DESC_STBC_LSB                                                     38
239*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MSB                                                     38
240*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MASK                                                    0x0000004000000000
241*5113495bSYour Name 
242*5113495bSYour Name 
243*5113495bSYour Name 
244*5113495bSYour Name 
245*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x0000000000000000
246*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      39
247*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      39
248*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x0000008000000000
249*5113495bSYour Name 
250*5113495bSYour Name 
251*5113495bSYour Name 
252*5113495bSYour Name 
253*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x0000000000000000
254*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           40
255*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           40
256*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x0000010000000000
257*5113495bSYour Name 
258*5113495bSYour Name 
259*5113495bSYour Name 
260*5113495bSYour Name 
261*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x0000000000000000
262*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            41
263*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            48
264*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe0000000000
265*5113495bSYour Name 
266*5113495bSYour Name 
267*5113495bSYour Name 
268*5113495bSYour Name 
269*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x0000000000000000
270*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          49
271*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          56
272*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe000000000000
273*5113495bSYour Name 
274*5113495bSYour Name 
275*5113495bSYour Name 
276*5113495bSYour Name 
277*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x0000000000000000
278*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            57
279*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            57
280*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x0200000000000000
281*5113495bSYour Name 
282*5113495bSYour Name 
283*5113495bSYour Name 
284*5113495bSYour Name 
285*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x0000000000000000
286*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        58
287*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        58
288*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x0400000000000000
289*5113495bSYour Name 
290*5113495bSYour Name 
291*5113495bSYour Name 
292*5113495bSYour Name 
293*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x0000000000000000
294*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       59
295*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       59
296*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x0800000000000000
297*5113495bSYour Name 
298*5113495bSYour Name 
299*5113495bSYour Name 
300*5113495bSYour Name 
301*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x0000000000000000
302*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           60
303*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           62
304*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x7000000000000000
305*5113495bSYour Name 
306*5113495bSYour Name 
307*5113495bSYour Name 
308*5113495bSYour Name 
309*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x0000000000000000
310*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          63
311*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          63
312*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x8000000000000000
313*5113495bSYour Name 
314*5113495bSYour Name 
315*5113495bSYour Name 
316*5113495bSYour Name 
317*5113495bSYour Name #define MACTX_PHY_DESC_NDP_OFFSET                                                   0x0000000000000008
318*5113495bSYour Name #define MACTX_PHY_DESC_NDP_LSB                                                      0
319*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MSB                                                      1
320*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MASK                                                     0x0000000000000003
321*5113495bSYour Name 
322*5113495bSYour Name 
323*5113495bSYour Name 
324*5113495bSYour Name 
325*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x0000000000000008
326*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_LSB                                                  2
327*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MSB                                                  2
328*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x0000000000000004
329*5113495bSYour Name 
330*5113495bSYour Name 
331*5113495bSYour Name 
332*5113495bSYour Name 
333*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x0000000000000008
334*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_LSB                                                3
335*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MSB                                                3
336*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x0000000000000008
337*5113495bSYour Name 
338*5113495bSYour Name 
339*5113495bSYour Name 
340*5113495bSYour Name 
341*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x0000000000000008
342*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                4
343*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                6
344*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x0000000000000070
345*5113495bSYour Name 
346*5113495bSYour Name 
347*5113495bSYour Name 
348*5113495bSYour Name 
349*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x0000000000000008
350*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        7
351*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        14
352*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x0000000000007f80
353*5113495bSYour Name 
354*5113495bSYour Name 
355*5113495bSYour Name 
356*5113495bSYour Name 
357*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x0000000000000008
358*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              15
359*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              17
360*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x0000000000038000
361*5113495bSYour Name 
362*5113495bSYour Name 
363*5113495bSYour Name 
364*5113495bSYour Name 
365*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x0000000000000008
366*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               18
367*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               18
368*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x0000000000040000
369*5113495bSYour Name 
370*5113495bSYour Name 
371*5113495bSYour Name 
372*5113495bSYour Name 
373*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x0000000000000008
374*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_LSB                                              19
375*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
376*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x0000000000180000
377*5113495bSYour Name 
378*5113495bSYour Name 
379*5113495bSYour Name 
380*5113495bSYour Name 
381*5113495bSYour Name #define MACTX_PHY_DESC_NSS_OFFSET                                                   0x0000000000000008
382*5113495bSYour Name #define MACTX_PHY_DESC_NSS_LSB                                                      21
383*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MSB                                                      23
384*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MASK                                                     0x0000000000e00000
385*5113495bSYour Name 
386*5113495bSYour Name 
387*5113495bSYour Name 
388*5113495bSYour Name 
389*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x0000000000000008
390*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
391*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
392*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x0000000007000000
393*5113495bSYour Name 
394*5113495bSYour Name 
395*5113495bSYour Name 
396*5113495bSYour Name 
397*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x0000000000000008
398*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
399*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
400*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x0000000018000000
401*5113495bSYour Name 
402*5113495bSYour Name 
403*5113495bSYour Name 
404*5113495bSYour Name 
405*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x0000000000000008
406*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
407*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
408*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x0000000020000000
409*5113495bSYour Name 
410*5113495bSYour Name 
411*5113495bSYour Name 
412*5113495bSYour Name 
413*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x0000000000000008
414*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
415*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
416*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x0000000040000000
417*5113495bSYour Name 
418*5113495bSYour Name 
419*5113495bSYour Name 
420*5113495bSYour Name 
421*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x0000000000000008
422*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
423*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
424*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x0000000080000000
425*5113495bSYour Name 
426*5113495bSYour Name 
427*5113495bSYour Name 
428*5113495bSYour Name 
429*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000000000008
430*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            32
431*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            39
432*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff00000000
433*5113495bSYour Name 
434*5113495bSYour Name 
435*5113495bSYour Name 
436*5113495bSYour Name 
437*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000000000008
438*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      40
439*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      40
440*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x0000010000000000
441*5113495bSYour Name 
442*5113495bSYour Name 
443*5113495bSYour Name 
444*5113495bSYour Name 
445*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000000000008
446*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            41
447*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            41
448*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x0000020000000000
449*5113495bSYour Name 
450*5113495bSYour Name 
451*5113495bSYour Name 
452*5113495bSYour Name 
453*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000000000008
454*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_LSB                                                  42
455*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MSB                                                  42
456*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x0000040000000000
457*5113495bSYour Name 
458*5113495bSYour Name 
459*5113495bSYour Name 
460*5113495bSYour Name 
461*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000000000008
462*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_LSB                                               43
463*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MSB                                               44
464*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x0000180000000000
465*5113495bSYour Name 
466*5113495bSYour Name 
467*5113495bSYour Name 
468*5113495bSYour Name 
469*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000000000008
470*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          45
471*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          46
472*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x0000600000000000
473*5113495bSYour Name 
474*5113495bSYour Name 
475*5113495bSYour Name 
476*5113495bSYour Name 
477*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000000000008
478*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           47
479*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           49
480*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x0003800000000000
481*5113495bSYour Name 
482*5113495bSYour Name 
483*5113495bSYour Name 
484*5113495bSYour Name 
485*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000000000008
486*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           50
487*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           50
488*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x0004000000000000
489*5113495bSYour Name 
490*5113495bSYour Name 
491*5113495bSYour Name 
492*5113495bSYour Name 
493*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000000000008
494*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 51
495*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 52
496*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x0018000000000000
497*5113495bSYour Name 
498*5113495bSYour Name 
499*5113495bSYour Name 
500*5113495bSYour Name 
501*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000000000008
502*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       53
503*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       56
504*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e0000000000000
505*5113495bSYour Name 
506*5113495bSYour Name 
507*5113495bSYour Name 
508*5113495bSYour Name 
509*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000000000008
510*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_LSB                                              57
511*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MSB                                              57
512*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x0200000000000000
513*5113495bSYour Name 
514*5113495bSYour Name 
515*5113495bSYour Name 
516*5113495bSYour Name 
517*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000000000008
518*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          58
519*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          63
520*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc00000000000000
521*5113495bSYour Name 
522*5113495bSYour Name 
523*5113495bSYour Name 
524*5113495bSYour Name #endif
525