1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MACTX_USER_DESC_COMMON_H_ 27 #define _MACTX_USER_DESC_COMMON_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "unallocated_ru_160_info.h" 32 #include "ru_allocation_160_info.h" 33 #define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 34 35 #define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 36 37 38 struct mactx_user_desc_common { 39 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 40 uint32_t num_users : 6, 41 reserved_0b : 5, 42 ltf_size : 2, 43 reserved_0c : 3, 44 he_stf_long : 1, 45 reserved_0d : 7, 46 num_users_he_sigb_band0 : 8; 47 uint32_t num_ltf_symbols : 3, 48 reserved_1a : 5, 49 num_users_he_sigb_band1 : 8, 50 reserved_1b : 16; 51 uint32_t packet_extension_a_factor : 2, 52 packet_extension_pe_disambiguity : 1, 53 packet_extension : 3, 54 reserved : 2, 55 he_sigb_dcm : 1, 56 reserved_2b : 7, 57 he_sigb_compression : 1, 58 reserved_2c : 15; 59 uint32_t he_sigb_0_mcs : 3, 60 reserved_3a : 13, 61 num_he_sigb_sym : 5, 62 center_ru_0 : 1, 63 center_ru_1 : 1, 64 reserved_3b : 1, 65 ftm_en : 1, 66 pe_nss : 3, 67 pe_ltf_size : 2, 68 pe_content : 1, 69 pe_chain_csd_en : 1; 70 struct ru_allocation_160_info ru_allocation_0123_details; 71 struct ru_allocation_160_info ru_allocation_4567_details; 72 struct unallocated_ru_160_info ru_allocation_160_0_details; 73 struct unallocated_ru_160_info ru_allocation_160_1_details; 74 uint32_t num_data_symbols : 16, 75 ndp_ru_tone_set_index : 7, 76 ndp_feedback_status : 1, 77 doppler_indication : 1, 78 reserved_14a : 7; 79 uint32_t spatial_reuse : 16, 80 reserved_15a : 16; 81 #else 82 uint32_t num_users_he_sigb_band0 : 8, 83 reserved_0d : 7, 84 he_stf_long : 1, 85 reserved_0c : 3, 86 ltf_size : 2, 87 reserved_0b : 5, 88 num_users : 6; 89 uint32_t reserved_1b : 16, 90 num_users_he_sigb_band1 : 8, 91 reserved_1a : 5, 92 num_ltf_symbols : 3; 93 uint32_t reserved_2c : 15, 94 he_sigb_compression : 1, 95 reserved_2b : 7, 96 he_sigb_dcm : 1, 97 reserved : 2, 98 packet_extension : 3, 99 packet_extension_pe_disambiguity : 1, 100 packet_extension_a_factor : 2; 101 uint32_t pe_chain_csd_en : 1, 102 pe_content : 1, 103 pe_ltf_size : 2, 104 pe_nss : 3, 105 ftm_en : 1, 106 reserved_3b : 1, 107 center_ru_1 : 1, 108 center_ru_0 : 1, 109 num_he_sigb_sym : 5, 110 reserved_3a : 13, 111 he_sigb_0_mcs : 3; 112 struct ru_allocation_160_info ru_allocation_0123_details; 113 struct ru_allocation_160_info ru_allocation_4567_details; 114 struct unallocated_ru_160_info ru_allocation_160_0_details; 115 struct unallocated_ru_160_info ru_allocation_160_1_details; 116 uint32_t reserved_14a : 7, 117 doppler_indication : 1, 118 ndp_feedback_status : 1, 119 ndp_ru_tone_set_index : 7, 120 num_data_symbols : 16; 121 uint32_t reserved_15a : 16, 122 spatial_reuse : 16; 123 #endif 124 }; 125 126 127 128 129 #define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 130 #define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 131 #define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 132 #define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f 133 134 135 136 137 #define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 138 #define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 139 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 140 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 141 142 143 144 145 #define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 146 #define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 147 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 148 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 149 150 151 152 153 #define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 154 #define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 155 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 156 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 157 158 159 160 161 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 162 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 163 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 164 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 165 166 167 168 169 #define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 170 #define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 171 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 172 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 173 174 175 176 177 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 178 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 179 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 180 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 181 182 183 184 185 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 186 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 187 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 188 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 189 190 191 192 193 #define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 194 #define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 195 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 196 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 197 198 199 200 201 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 202 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 203 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 204 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 205 206 207 208 209 #define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 210 #define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 211 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 212 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 213 214 215 216 217 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 218 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 219 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 220 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 221 222 223 224 225 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 226 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 227 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 228 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 229 230 231 232 233 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 234 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 235 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 236 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 237 238 239 240 241 #define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 242 #define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 243 #define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 244 #define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 245 246 247 248 249 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 250 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 251 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 252 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 253 254 255 256 257 #define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 258 #define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 259 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 260 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 261 262 263 264 265 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 266 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 267 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 268 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 269 270 271 272 273 #define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 274 #define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 275 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 276 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 277 278 279 280 281 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 282 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 283 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 284 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 285 286 287 288 289 #define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 290 #define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 291 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 292 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 293 294 295 296 297 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 298 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 299 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 300 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 301 302 303 304 305 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 306 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 307 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 308 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 309 310 311 312 313 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 314 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 315 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 316 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 317 318 319 320 321 #define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 322 #define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 323 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 324 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 325 326 327 328 329 #define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 330 #define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 331 #define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 332 #define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 333 334 335 336 337 #define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 338 #define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 339 #define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 340 #define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 341 342 343 344 345 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 346 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 347 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 348 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 349 350 351 352 353 #define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 354 #define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 355 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 356 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 357 358 359 360 361 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 362 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 363 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 364 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 365 366 367 368 369 370 371 372 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 373 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 374 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 375 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 376 377 378 379 380 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 381 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 382 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 383 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 384 385 386 387 388 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 389 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 390 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 391 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 392 393 394 395 396 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 397 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 398 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 399 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 400 401 402 403 404 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 405 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 406 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 407 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 408 409 410 411 412 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 413 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 414 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 415 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 416 417 418 419 420 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 421 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 422 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 423 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 424 425 426 427 428 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 429 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 430 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 431 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 432 433 434 435 436 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 437 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 438 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 439 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 440 441 442 443 444 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 445 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 446 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 447 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 448 449 450 451 452 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 453 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 454 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 455 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 456 457 458 459 460 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 461 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 462 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 463 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 464 465 466 467 468 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 469 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 470 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 471 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 472 473 474 475 476 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 477 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 478 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 479 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 480 481 482 483 484 485 486 487 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 488 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 489 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 490 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 491 492 493 494 495 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 496 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 497 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 498 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 499 500 501 502 503 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 504 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 505 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 506 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 507 508 509 510 511 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 512 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 513 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 514 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 515 516 517 518 519 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 520 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 521 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 522 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 523 524 525 526 527 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 528 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 529 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 530 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 531 532 533 534 535 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 536 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 537 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 538 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 539 540 541 542 543 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 544 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 545 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 546 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 547 548 549 550 551 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 552 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 553 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 554 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 555 556 557 558 559 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 560 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 561 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 562 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 563 564 565 566 567 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 568 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 569 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 570 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 571 572 573 574 575 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 576 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 577 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 578 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 579 580 581 582 583 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 584 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 585 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 586 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 587 588 589 590 591 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 592 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 593 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 594 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 595 596 597 598 599 600 601 602 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 603 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 604 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 605 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff 606 607 608 609 610 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 611 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 612 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 613 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 614 615 616 617 618 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 619 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 620 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 621 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 622 623 624 625 626 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 627 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 628 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 629 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 630 631 632 633 634 635 636 637 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 638 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 639 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 640 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 641 642 643 644 645 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 646 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 647 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 648 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 649 650 651 652 653 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 654 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 655 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 656 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 657 658 659 660 661 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 662 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 663 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 664 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 665 666 667 668 669 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 670 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 671 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 672 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff 673 674 675 676 677 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 678 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 679 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 680 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 681 682 683 684 685 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 686 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 687 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 688 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 689 690 691 692 693 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 694 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 695 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 696 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 697 698 699 700 701 #define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 702 #define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 703 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 704 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 705 706 707 708 709 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 710 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 711 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 712 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 713 714 715 716 717 #define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 718 #define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 719 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 720 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 721 722 723 724 #endif 725