1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MON_INGRESS_RING_H_ 27 #define _MON_INGRESS_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_MON_INGRESS_RING 4 33 34 35 struct mon_ingress_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info buffer_addr_info_details; 38 uint32_t buffer_virt_addr_31_0 : 32; 39 uint32_t buffer_virt_addr_63_32 : 32; 40 #else 41 struct buffer_addr_info buffer_addr_info_details; 42 uint32_t buffer_virt_addr_31_0 : 32; 43 uint32_t buffer_virt_addr_63_32 : 32; 44 #endif 45 }; 46 47 48 49 50 51 52 53 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 54 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 55 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 56 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 57 58 59 60 61 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 62 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 63 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 64 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 65 66 67 68 69 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 70 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 71 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 72 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 73 74 75 76 77 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 78 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 79 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 80 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 81 82 83 84 85 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 86 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 87 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 88 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 89 90 91 92 93 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 94 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 95 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 96 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 97 98 99 100 #endif 101