1 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 21 22 23 24 25 26 27 #ifndef _PDG_RESPONSE_RATE_SETTING_H_ 28 #define _PDG_RESPONSE_RATE_SETTING_H_ 29 #if !defined(__ASSEMBLER__) 30 #endif 31 32 #include "mlo_sta_id_details.h" 33 #define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 34 35 36 struct pdg_response_rate_setting { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t reserved_0a : 1, // [0:0] 39 tx_antenna_sector_ctrl : 24, // [24:1] 40 pkt_type : 4, // [28:25] 41 smoothing : 1, // [29:29] 42 ldpc : 1, // [30:30] 43 stbc : 1; // [31:31] 44 uint32_t alt_tx_pwr : 8, // [7:0] 45 alt_min_tx_pwr : 8, // [15:8] 46 alt_nss : 3, // [18:16] 47 alt_tx_chain_mask : 8, // [26:19] 48 alt_bw : 3, // [29:27] 49 stf_ltf_3db_boost : 1, // [30:30] 50 force_extra_symbol : 1; // [31:31] 51 uint32_t alt_rate_mcs : 4, // [3:0] 52 nss : 3, // [6:4] 53 dpd_enable : 1, // [7:7] 54 tx_pwr : 8, // [15:8] 55 min_tx_pwr : 8, // [23:16] 56 tx_chain_mask : 8; // [31:24] 57 uint32_t reserved_3a : 8, // [7:0] 58 sgi : 2, // [9:8] 59 rate_mcs : 4, // [13:10] 60 reserved_3b : 2, // [15:14] 61 tx_pwr_1 : 8, // [23:16] 62 alt_tx_pwr_1 : 8; // [31:24] 63 uint32_t aggregation : 1, // [0:0] 64 dot11ax_bss_color_id : 6, // [6:1] 65 dot11ax_spatial_reuse : 4, // [10:7] 66 dot11ax_cp_ltf_size : 2, // [12:11] 67 dot11ax_dcm : 1, // [13:13] 68 dot11ax_doppler_indication : 1, // [14:14] 69 dot11ax_su_extended : 1, // [15:15] 70 dot11ax_min_packet_extension : 2, // [17:16] 71 dot11ax_pe_nss : 3, // [20:18] 72 dot11ax_pe_content : 1, // [21:21] 73 dot11ax_pe_ltf_size : 2, // [23:22] 74 dot11ax_chain_csd_en : 1, // [24:24] 75 dot11ax_pe_chain_csd_en : 1, // [25:25] 76 dot11ax_dl_ul_flag : 1, // [26:26] 77 reserved_4a : 5; // [31:27] 78 uint32_t dot11ax_ext_ru_start_index : 4, // [3:0] 79 dot11ax_ext_ru_size : 4, // [7:4] 80 eht_duplicate_mode : 2, // [9:8] 81 he_sigb_dcm : 1, // [10:10] 82 he_sigb_0_mcs : 3, // [13:11] 83 num_he_sigb_sym : 5, // [18:14] 84 required_response_time_source : 1, // [19:19] 85 reserved_5a : 6, // [25:20] 86 u_sig_puncture_pattern_encoding : 6; // [31:26] 87 struct mlo_sta_id_details mlo_sta_id_details_rx; 88 uint16_t required_response_time : 12, // [27:16] 89 dot11be_params_placeholder : 4; // [31:28] 90 #else 91 uint32_t stbc : 1, // [31:31] 92 ldpc : 1, // [30:30] 93 smoothing : 1, // [29:29] 94 pkt_type : 4, // [28:25] 95 tx_antenna_sector_ctrl : 24, // [24:1] 96 reserved_0a : 1; // [0:0] 97 uint32_t force_extra_symbol : 1, // [31:31] 98 stf_ltf_3db_boost : 1, // [30:30] 99 alt_bw : 3, // [29:27] 100 alt_tx_chain_mask : 8, // [26:19] 101 alt_nss : 3, // [18:16] 102 alt_min_tx_pwr : 8, // [15:8] 103 alt_tx_pwr : 8; // [7:0] 104 uint32_t tx_chain_mask : 8, // [31:24] 105 min_tx_pwr : 8, // [23:16] 106 tx_pwr : 8, // [15:8] 107 dpd_enable : 1, // [7:7] 108 nss : 3, // [6:4] 109 alt_rate_mcs : 4; // [3:0] 110 uint32_t alt_tx_pwr_1 : 8, // [31:24] 111 tx_pwr_1 : 8, // [23:16] 112 reserved_3b : 2, // [15:14] 113 rate_mcs : 4, // [13:10] 114 sgi : 2, // [9:8] 115 reserved_3a : 8; // [7:0] 116 uint32_t reserved_4a : 5, // [31:27] 117 dot11ax_dl_ul_flag : 1, // [26:26] 118 dot11ax_pe_chain_csd_en : 1, // [25:25] 119 dot11ax_chain_csd_en : 1, // [24:24] 120 dot11ax_pe_ltf_size : 2, // [23:22] 121 dot11ax_pe_content : 1, // [21:21] 122 dot11ax_pe_nss : 3, // [20:18] 123 dot11ax_min_packet_extension : 2, // [17:16] 124 dot11ax_su_extended : 1, // [15:15] 125 dot11ax_doppler_indication : 1, // [14:14] 126 dot11ax_dcm : 1, // [13:13] 127 dot11ax_cp_ltf_size : 2, // [12:11] 128 dot11ax_spatial_reuse : 4, // [10:7] 129 dot11ax_bss_color_id : 6, // [6:1] 130 aggregation : 1; // [0:0] 131 uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] 132 reserved_5a : 6, // [25:20] 133 required_response_time_source : 1, // [19:19] 134 num_he_sigb_sym : 5, // [18:14] 135 he_sigb_0_mcs : 3, // [13:11] 136 he_sigb_dcm : 1, // [10:10] 137 eht_duplicate_mode : 2, // [9:8] 138 dot11ax_ext_ru_size : 4, // [7:4] 139 dot11ax_ext_ru_start_index : 4; // [3:0] 140 uint32_t dot11be_params_placeholder : 4, // [31:28] 141 required_response_time : 12; // [27:16] 142 struct mlo_sta_id_details mlo_sta_id_details_rx; 143 #endif 144 }; 145 146 147 148 149 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 150 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 151 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 152 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 153 154 155 156 157 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 158 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 159 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 160 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe 161 162 163 164 165 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 166 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 167 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 168 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 169 170 171 172 173 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 174 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 175 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 176 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 177 178 179 180 181 #define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 182 #define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 183 #define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 184 #define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 185 186 187 188 189 #define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 190 #define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 191 #define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 192 #define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 193 194 195 196 197 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 198 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 199 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 200 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff 201 202 203 204 205 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 206 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 207 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 208 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 209 210 211 212 213 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 214 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 215 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 216 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 217 218 219 220 221 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 222 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 223 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 224 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 225 226 227 228 229 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 230 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 231 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 232 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 233 234 235 236 237 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 238 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 239 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 240 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 241 242 243 244 245 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 246 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 247 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 248 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 249 250 251 252 253 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 254 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 255 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 256 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f 257 258 259 260 261 #define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 262 #define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 263 #define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 264 #define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 265 266 267 268 269 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 270 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 271 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 272 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 273 274 275 276 277 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 278 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 279 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 280 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 281 282 283 284 285 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 286 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 287 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 288 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 289 290 291 292 293 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 294 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 295 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 296 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 297 298 299 300 301 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c 302 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 303 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 304 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff 305 306 307 308 309 #define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c 310 #define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 311 #define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 312 #define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 313 314 315 316 317 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c 318 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 319 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 320 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 321 322 323 324 325 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c 326 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 327 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 328 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 329 330 331 332 333 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c 334 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 335 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 336 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 337 338 339 340 341 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c 342 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 343 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 344 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 345 346 347 348 349 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 350 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 351 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 352 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 353 354 355 356 357 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 358 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 359 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 360 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e 361 362 363 364 365 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 366 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 367 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 368 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 369 370 371 372 373 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 374 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 375 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 376 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 377 378 379 380 381 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 382 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 383 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 384 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 385 386 387 388 389 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 390 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 391 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 392 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 393 394 395 396 397 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 398 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 399 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 400 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 401 402 403 404 405 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 406 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 407 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 408 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 409 410 411 412 413 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 414 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 415 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 416 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 417 418 419 420 421 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 422 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 423 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 424 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 425 426 427 428 429 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 430 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 431 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 432 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 433 434 435 436 437 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 438 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 439 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 440 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 441 442 443 444 445 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 446 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 447 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 448 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 449 450 451 452 453 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 454 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 455 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 456 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 457 458 459 460 461 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 462 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 463 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 464 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 465 466 467 468 469 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 470 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 471 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 472 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f 473 474 475 476 477 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 478 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 479 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 480 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 481 482 483 484 485 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 486 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 487 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 488 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 489 490 491 492 493 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 494 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 495 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 496 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 497 498 499 500 501 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 502 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 503 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 504 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 505 506 507 508 509 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 510 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 511 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 512 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 513 514 515 516 517 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 518 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 519 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 520 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 521 522 523 524 525 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 526 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 527 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 528 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 529 530 531 532 533 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 534 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 535 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 536 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 537 538 539 540 541 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 542 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 543 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 544 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff 545 546 547 548 549 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 550 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 551 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 552 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 553 554 555 556 557 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 558 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 559 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 560 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 561 562 563 564 565 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 566 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 567 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 568 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 569 570 571 572 573 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 574 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 575 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 576 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 577 578 579 580 581 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 582 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 583 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 584 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 585 586 587 588 589 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 590 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 591 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 592 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 593 594 595 596 597 #endif 598