1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_CACHE_H_ 27 #define _REO_FLUSH_CACHE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 33 34 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 35 36 37 struct reo_flush_cache { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t flush_addr_31_0 : 32; 41 uint32_t flush_addr_39_32 : 8, 42 forward_all_mpdus_in_queue : 1, 43 release_cache_block_index : 1, 44 cache_block_resource_index : 2, 45 flush_without_invalidate : 1, 46 block_cache_usage_after_flush : 1, 47 flush_entire_cache : 1, 48 flush_queue_1k_desc : 1, 49 reserved_2b : 16; 50 uint32_t reserved_3a : 32; 51 uint32_t reserved_4a : 32; 52 uint32_t reserved_5a : 32; 53 uint32_t reserved_6a : 32; 54 uint32_t reserved_7a : 32; 55 uint32_t reserved_8a : 32; 56 uint32_t tlv64_padding : 32; 57 #else 58 struct uniform_reo_cmd_header cmd_header; 59 uint32_t flush_addr_31_0 : 32; 60 uint32_t reserved_2b : 16, 61 flush_queue_1k_desc : 1, 62 flush_entire_cache : 1, 63 block_cache_usage_after_flush : 1, 64 flush_without_invalidate : 1, 65 cache_block_resource_index : 2, 66 release_cache_block_index : 1, 67 forward_all_mpdus_in_queue : 1, 68 flush_addr_39_32 : 8; 69 uint32_t reserved_3a : 32; 70 uint32_t reserved_4a : 32; 71 uint32_t reserved_5a : 32; 72 uint32_t reserved_6a : 32; 73 uint32_t reserved_7a : 32; 74 uint32_t reserved_8a : 32; 75 uint32_t tlv64_padding : 32; 76 #endif 77 }; 78 79 80 81 82 83 84 85 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 86 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 87 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 88 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 89 90 91 92 93 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 94 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 95 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 96 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 97 98 99 100 101 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 102 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 103 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 104 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 105 106 107 108 109 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 110 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 111 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 112 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 113 114 115 116 117 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 118 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 119 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 120 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 121 122 123 124 125 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 126 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 127 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 128 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 129 130 131 132 133 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 134 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 135 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 136 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 137 138 139 140 141 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 142 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 143 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 144 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 145 146 147 148 149 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 150 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 151 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 152 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 153 154 155 156 157 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 158 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 159 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 160 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 161 162 163 164 165 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 166 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 167 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 168 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 169 170 171 172 173 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 174 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 175 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 176 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 177 178 179 180 181 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 182 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 183 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 184 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 185 186 187 188 189 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 190 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 191 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 192 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 193 194 195 196 197 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 198 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 199 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 200 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 201 202 203 204 205 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 206 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 207 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 208 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 209 210 211 212 213 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 214 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 215 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 216 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 217 218 219 220 221 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 222 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 223 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 224 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 225 226 227 228 229 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 230 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 231 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 232 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 233 234 235 236 237 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 238 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 239 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 240 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 241 242 243 244 #endif 245