1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_QUEUE_STATUS_H_ 27 #define _REO_FLUSH_QUEUE_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 35 36 37 struct reo_flush_queue_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, 41 reserved_2a : 31; 42 uint32_t reserved_3a : 32; 43 uint32_t reserved_4a : 32; 44 uint32_t reserved_5a : 32; 45 uint32_t reserved_6a : 32; 46 uint32_t reserved_7a : 32; 47 uint32_t reserved_8a : 32; 48 uint32_t reserved_9a : 32; 49 uint32_t reserved_10a : 32; 50 uint32_t reserved_11a : 32; 51 uint32_t reserved_12a : 32; 52 uint32_t reserved_13a : 32; 53 uint32_t reserved_14a : 32; 54 uint32_t reserved_15a : 32; 55 uint32_t reserved_16a : 32; 56 uint32_t reserved_17a : 32; 57 uint32_t reserved_18a : 32; 58 uint32_t reserved_19a : 32; 59 uint32_t reserved_20a : 32; 60 uint32_t reserved_21a : 32; 61 uint32_t reserved_22a : 32; 62 uint32_t reserved_23a : 32; 63 uint32_t reserved_24a : 32; 64 uint32_t reserved_25a : 28, 65 looping_count : 4; 66 #else 67 struct uniform_reo_status_header status_header; 68 uint32_t reserved_2a : 31, 69 error_detected : 1; 70 uint32_t reserved_3a : 32; 71 uint32_t reserved_4a : 32; 72 uint32_t reserved_5a : 32; 73 uint32_t reserved_6a : 32; 74 uint32_t reserved_7a : 32; 75 uint32_t reserved_8a : 32; 76 uint32_t reserved_9a : 32; 77 uint32_t reserved_10a : 32; 78 uint32_t reserved_11a : 32; 79 uint32_t reserved_12a : 32; 80 uint32_t reserved_13a : 32; 81 uint32_t reserved_14a : 32; 82 uint32_t reserved_15a : 32; 83 uint32_t reserved_16a : 32; 84 uint32_t reserved_17a : 32; 85 uint32_t reserved_18a : 32; 86 uint32_t reserved_19a : 32; 87 uint32_t reserved_20a : 32; 88 uint32_t reserved_21a : 32; 89 uint32_t reserved_22a : 32; 90 uint32_t reserved_23a : 32; 91 uint32_t reserved_24a : 32; 92 uint32_t looping_count : 4, 93 reserved_25a : 28; 94 #endif 95 }; 96 97 98 99 100 101 102 103 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 104 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 105 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 106 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 107 108 109 110 111 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 112 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 113 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 114 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 115 116 117 118 119 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 120 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 121 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 122 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 123 124 125 126 127 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 128 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 129 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 130 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 131 132 133 134 135 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 136 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 137 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 138 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 139 140 141 142 143 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 144 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 145 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 146 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 147 148 149 150 151 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 152 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 153 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 154 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe 155 156 157 158 159 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 160 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 161 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 162 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 163 164 165 166 167 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 168 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 169 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 170 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 171 172 173 174 175 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 176 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 177 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 178 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 179 180 181 182 183 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 184 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 185 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 186 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 187 188 189 190 191 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 192 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 193 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 194 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 195 196 197 198 199 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 200 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 201 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 202 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 203 204 205 206 207 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 208 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 209 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 210 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 211 212 213 214 215 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 216 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 217 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 218 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 219 220 221 222 223 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 224 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 225 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 226 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 227 228 229 230 231 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 232 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 233 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 234 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 235 236 237 238 239 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 240 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 241 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 242 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 243 244 245 246 247 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 248 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 249 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 250 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 251 252 253 254 255 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 256 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 257 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 258 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 259 260 261 262 263 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 264 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 265 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 266 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 267 268 269 270 271 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 272 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 273 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 274 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 275 276 277 278 279 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 280 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 281 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 282 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 283 284 285 286 287 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 288 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 289 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 290 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 291 292 293 294 295 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 296 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 297 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 298 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 299 300 301 302 303 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 304 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 305 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 306 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 307 308 309 310 311 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 312 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 313 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 314 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 315 316 317 318 319 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 320 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 321 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 322 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 323 324 325 326 327 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 328 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 329 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 330 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 331 332 333 334 335 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 336 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 337 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 338 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 339 340 341 342 343 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 344 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 345 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 346 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 347 348 349 350 #endif 351