1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 27 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 35 36 37 struct reo_flush_timeout_list_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, 41 timout_list_empty : 1, 42 reserved_2a : 30; 43 uint32_t release_desc_count : 16, 44 forward_buf_count : 16; 45 uint32_t reserved_4a : 32; 46 uint32_t reserved_5a : 32; 47 uint32_t reserved_6a : 32; 48 uint32_t reserved_7a : 32; 49 uint32_t reserved_8a : 32; 50 uint32_t reserved_9a : 32; 51 uint32_t reserved_10a : 32; 52 uint32_t reserved_11a : 32; 53 uint32_t reserved_12a : 32; 54 uint32_t reserved_13a : 32; 55 uint32_t reserved_14a : 32; 56 uint32_t reserved_15a : 32; 57 uint32_t reserved_16a : 32; 58 uint32_t reserved_17a : 32; 59 uint32_t reserved_18a : 32; 60 uint32_t reserved_19a : 32; 61 uint32_t reserved_20a : 32; 62 uint32_t reserved_21a : 32; 63 uint32_t reserved_22a : 32; 64 uint32_t reserved_23a : 32; 65 uint32_t reserved_24a : 32; 66 uint32_t reserved_25a : 28, 67 looping_count : 4; 68 #else 69 struct uniform_reo_status_header status_header; 70 uint32_t reserved_2a : 30, 71 timout_list_empty : 1, 72 error_detected : 1; 73 uint32_t forward_buf_count : 16, 74 release_desc_count : 16; 75 uint32_t reserved_4a : 32; 76 uint32_t reserved_5a : 32; 77 uint32_t reserved_6a : 32; 78 uint32_t reserved_7a : 32; 79 uint32_t reserved_8a : 32; 80 uint32_t reserved_9a : 32; 81 uint32_t reserved_10a : 32; 82 uint32_t reserved_11a : 32; 83 uint32_t reserved_12a : 32; 84 uint32_t reserved_13a : 32; 85 uint32_t reserved_14a : 32; 86 uint32_t reserved_15a : 32; 87 uint32_t reserved_16a : 32; 88 uint32_t reserved_17a : 32; 89 uint32_t reserved_18a : 32; 90 uint32_t reserved_19a : 32; 91 uint32_t reserved_20a : 32; 92 uint32_t reserved_21a : 32; 93 uint32_t reserved_22a : 32; 94 uint32_t reserved_23a : 32; 95 uint32_t reserved_24a : 32; 96 uint32_t looping_count : 4, 97 reserved_25a : 28; 98 #endif 99 }; 100 101 102 103 104 105 106 107 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 108 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 109 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 110 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 111 112 113 114 115 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 116 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 117 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 118 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 119 120 121 122 123 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 124 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 125 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 126 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 127 128 129 130 131 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 132 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 133 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 134 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 135 136 137 138 139 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 140 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 141 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 142 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 143 144 145 146 147 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 148 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 149 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 150 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 151 152 153 154 155 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 156 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 157 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 158 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 159 160 161 162 163 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 164 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 165 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 166 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 167 168 169 170 171 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 172 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 173 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 174 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 175 176 177 178 179 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 180 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 182 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 183 184 185 186 187 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 188 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 189 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 190 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 191 192 193 194 195 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 196 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 197 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 198 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 199 200 201 202 203 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 204 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 205 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 206 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 207 208 209 210 211 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 212 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 213 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 214 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 215 216 217 218 219 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 220 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 221 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 222 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 223 224 225 226 227 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 228 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 229 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 230 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 231 232 233 234 235 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 237 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 238 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 239 240 241 242 243 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 244 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 245 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 246 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 247 248 249 250 251 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 252 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 253 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 254 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 255 256 257 258 259 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 260 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 261 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 262 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 263 264 265 266 267 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 268 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 269 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 270 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 271 272 273 274 275 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 276 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 277 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 278 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 279 280 281 282 283 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 284 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 285 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 286 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 287 288 289 290 291 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 292 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 293 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 294 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 295 296 297 298 299 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 300 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 301 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 302 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 303 304 305 306 307 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 308 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 309 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 310 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 311 312 313 314 315 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 316 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 317 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 318 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 319 320 321 322 323 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 324 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 325 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 326 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 327 328 329 330 331 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 332 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 333 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 334 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 335 336 337 338 339 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 340 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 341 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 342 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 343 344 345 346 347 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 348 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 349 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 350 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 351 352 353 354 355 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 356 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 357 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 358 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 359 360 361 362 363 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 364 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 365 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 366 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 367 368 369 370 #endif 371