1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_GET_QUEUE_STATS_H_ 27 #define _REO_GET_QUEUE_STATS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 33 34 #define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 35 36 37 struct reo_get_queue_stats { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 41 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 42 clear_stats : 1, 43 reserved_2a : 23; 44 uint32_t reserved_3a : 32; 45 uint32_t reserved_4a : 32; 46 uint32_t reserved_5a : 32; 47 uint32_t reserved_6a : 32; 48 uint32_t reserved_7a : 32; 49 uint32_t reserved_8a : 32; 50 uint32_t tlv64_padding : 32; 51 #else 52 struct uniform_reo_cmd_header cmd_header; 53 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 54 uint32_t reserved_2a : 23, 55 clear_stats : 1, 56 rx_reo_queue_desc_addr_39_32 : 8; 57 uint32_t reserved_3a : 32; 58 uint32_t reserved_4a : 32; 59 uint32_t reserved_5a : 32; 60 uint32_t reserved_6a : 32; 61 uint32_t reserved_7a : 32; 62 uint32_t reserved_8a : 32; 63 uint32_t tlv64_padding : 32; 64 #endif 65 }; 66 67 68 69 70 71 72 73 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 74 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 75 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 76 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 77 78 79 80 81 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 82 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 83 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 84 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 85 86 87 88 89 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 90 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 91 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 92 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 93 94 95 96 97 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 98 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 99 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 100 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 101 102 103 104 105 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 106 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 107 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 108 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 109 110 111 112 113 #define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 114 #define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 115 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 116 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 117 118 119 120 121 #define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 122 #define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 123 #define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 124 #define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 125 126 127 128 129 #define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 130 #define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 131 #define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 132 #define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 133 134 135 136 137 #define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 138 #define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 139 #define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 140 #define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff 141 142 143 144 145 #define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 146 #define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 147 #define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 148 #define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 149 150 151 152 153 #define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 154 #define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 155 #define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 156 #define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff 157 158 159 160 161 #define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 162 #define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 163 #define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 164 #define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 165 166 167 168 169 #define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 170 #define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 171 #define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 172 #define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff 173 174 175 176 177 #define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 178 #define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 179 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 180 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 181 182 183 184 #endif 185