xref: /wlan-driver/fw-api/hw/qcn9224/v1/reo_unblock_cache_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _REO_UNBLOCK_CACHE_STATUS_H_
27 #define _REO_UNBLOCK_CACHE_STATUS_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "uniform_reo_status_header.h"
32 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
33 
34 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
35 
36 
37 struct reo_unblock_cache_status {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   uniform_reo_status_header                                 status_header;
40              uint32_t error_detected                                          :  1,
41                       unblock_type                                            :  1,
42                       reserved_2a                                             : 30;
43              uint32_t reserved_3a                                             : 32;
44              uint32_t reserved_4a                                             : 32;
45              uint32_t reserved_5a                                             : 32;
46              uint32_t reserved_6a                                             : 32;
47              uint32_t reserved_7a                                             : 32;
48              uint32_t reserved_8a                                             : 32;
49              uint32_t reserved_9a                                             : 32;
50              uint32_t reserved_10a                                            : 32;
51              uint32_t reserved_11a                                            : 32;
52              uint32_t reserved_12a                                            : 32;
53              uint32_t reserved_13a                                            : 32;
54              uint32_t reserved_14a                                            : 32;
55              uint32_t reserved_15a                                            : 32;
56              uint32_t reserved_16a                                            : 32;
57              uint32_t reserved_17a                                            : 32;
58              uint32_t reserved_18a                                            : 32;
59              uint32_t reserved_19a                                            : 32;
60              uint32_t reserved_20a                                            : 32;
61              uint32_t reserved_21a                                            : 32;
62              uint32_t reserved_22a                                            : 32;
63              uint32_t reserved_23a                                            : 32;
64              uint32_t reserved_24a                                            : 32;
65              uint32_t reserved_25a                                            : 28,
66                       looping_count                                           :  4;
67 #else
68              struct   uniform_reo_status_header                                 status_header;
69              uint32_t reserved_2a                                             : 30,
70                       unblock_type                                            :  1,
71                       error_detected                                          :  1;
72              uint32_t reserved_3a                                             : 32;
73              uint32_t reserved_4a                                             : 32;
74              uint32_t reserved_5a                                             : 32;
75              uint32_t reserved_6a                                             : 32;
76              uint32_t reserved_7a                                             : 32;
77              uint32_t reserved_8a                                             : 32;
78              uint32_t reserved_9a                                             : 32;
79              uint32_t reserved_10a                                            : 32;
80              uint32_t reserved_11a                                            : 32;
81              uint32_t reserved_12a                                            : 32;
82              uint32_t reserved_13a                                            : 32;
83              uint32_t reserved_14a                                            : 32;
84              uint32_t reserved_15a                                            : 32;
85              uint32_t reserved_16a                                            : 32;
86              uint32_t reserved_17a                                            : 32;
87              uint32_t reserved_18a                                            : 32;
88              uint32_t reserved_19a                                            : 32;
89              uint32_t reserved_20a                                            : 32;
90              uint32_t reserved_21a                                            : 32;
91              uint32_t reserved_22a                                            : 32;
92              uint32_t reserved_23a                                            : 32;
93              uint32_t reserved_24a                                            : 32;
94              uint32_t looping_count                                           :  4,
95                       reserved_25a                                            : 28;
96 #endif
97 };
98 
99 
100 
101 
102 
103 
104 
105 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET             0x0000000000000000
106 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                0
107 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                15
108 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK               0x000000000000ffff
109 
110 
111 
112 
113 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET            0x0000000000000000
114 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB               16
115 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB               25
116 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK              0x0000000003ff0000
117 
118 
119 
120 
121 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET      0x0000000000000000
122 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB         26
123 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB         27
124 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK        0x000000000c000000
125 
126 
127 
128 
129 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                   0x0000000000000000
130 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                      28
131 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                      31
132 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                     0x00000000f0000000
133 
134 
135 
136 
137 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                     0x0000000000000000
138 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                        32
139 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                        63
140 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                       0xffffffff00000000
141 
142 
143 
144 
145 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET                              0x0000000000000008
146 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB                                 0
147 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB                                 0
148 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK                                0x0000000000000001
149 
150 
151 
152 
153 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET                                0x0000000000000008
154 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB                                   1
155 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB                                   1
156 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK                                  0x0000000000000002
157 
158 
159 
160 
161 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET                                 0x0000000000000008
162 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB                                    2
163 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB                                    31
164 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK                                   0x00000000fffffffc
165 
166 
167 
168 
169 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET                                 0x0000000000000008
170 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB                                    32
171 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB                                    63
172 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK                                   0xffffffff00000000
173 
174 
175 
176 
177 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET                                 0x0000000000000010
178 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB                                    0
179 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB                                    31
180 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK                                   0x00000000ffffffff
181 
182 
183 
184 
185 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET                                 0x0000000000000010
186 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB                                    32
187 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB                                    63
188 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK                                   0xffffffff00000000
189 
190 
191 
192 
193 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET                                 0x0000000000000018
194 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB                                    0
195 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB                                    31
196 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK                                   0x00000000ffffffff
197 
198 
199 
200 
201 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET                                 0x0000000000000018
202 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB                                    32
203 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB                                    63
204 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK                                   0xffffffff00000000
205 
206 
207 
208 
209 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET                                 0x0000000000000020
210 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB                                    0
211 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB                                    31
212 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK                                   0x00000000ffffffff
213 
214 
215 
216 
217 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET                                 0x0000000000000020
218 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB                                    32
219 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB                                    63
220 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK                                   0xffffffff00000000
221 
222 
223 
224 
225 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET                                0x0000000000000028
226 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB                                   0
227 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB                                   31
228 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK                                  0x00000000ffffffff
229 
230 
231 
232 
233 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET                                0x0000000000000028
234 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB                                   32
235 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB                                   63
236 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK                                  0xffffffff00000000
237 
238 
239 
240 
241 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET                                0x0000000000000030
242 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB                                   0
243 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB                                   31
244 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK                                  0x00000000ffffffff
245 
246 
247 
248 
249 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET                                0x0000000000000030
250 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB                                   32
251 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB                                   63
252 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK                                  0xffffffff00000000
253 
254 
255 
256 
257 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET                                0x0000000000000038
258 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB                                   0
259 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB                                   31
260 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK                                  0x00000000ffffffff
261 
262 
263 
264 
265 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET                                0x0000000000000038
266 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB                                   32
267 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB                                   63
268 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK                                  0xffffffff00000000
269 
270 
271 
272 
273 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET                                0x0000000000000040
274 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB                                   0
275 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB                                   31
276 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK                                  0x00000000ffffffff
277 
278 
279 
280 
281 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET                                0x0000000000000040
282 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB                                   32
283 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB                                   63
284 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK                                  0xffffffff00000000
285 
286 
287 
288 
289 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET                                0x0000000000000048
290 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB                                   0
291 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB                                   31
292 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK                                  0x00000000ffffffff
293 
294 
295 
296 
297 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET                                0x0000000000000048
298 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB                                   32
299 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB                                   63
300 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK                                  0xffffffff00000000
301 
302 
303 
304 
305 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET                                0x0000000000000050
306 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB                                   0
307 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB                                   31
308 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK                                  0x00000000ffffffff
309 
310 
311 
312 
313 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET                                0x0000000000000050
314 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB                                   32
315 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB                                   63
316 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK                                  0xffffffff00000000
317 
318 
319 
320 
321 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET                                0x0000000000000058
322 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB                                   0
323 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB                                   31
324 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK                                  0x00000000ffffffff
325 
326 
327 
328 
329 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET                                0x0000000000000058
330 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB                                   32
331 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB                                   63
332 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK                                  0xffffffff00000000
333 
334 
335 
336 
337 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET                                0x0000000000000060
338 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB                                   0
339 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB                                   31
340 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK                                  0x00000000ffffffff
341 
342 
343 
344 
345 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET                                0x0000000000000060
346 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB                                   32
347 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB                                   59
348 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK                                  0x0fffffff00000000
349 
350 
351 
352 
353 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET                               0x0000000000000060
354 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB                                  60
355 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB                                  63
356 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK                                 0xf000000000000000
357 
358 
359 
360 #endif
361