1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RESPONSE_START_STATUS_H_ 27 #define _RESPONSE_START_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 32 33 #define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 34 35 36 struct response_start_status { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t generated_response : 3, 39 ftm_tm : 2, 40 trig_response_related : 1, 41 response_sta_count : 7, 42 reserved : 19; 43 uint32_t phy_ppdu_id : 16, 44 sw_peer_id : 16; 45 #else 46 uint32_t reserved : 19, 47 response_sta_count : 7, 48 trig_response_related : 1, 49 ftm_tm : 2, 50 generated_response : 3; 51 uint32_t sw_peer_id : 16, 52 phy_ppdu_id : 16; 53 #endif 54 }; 55 56 57 58 59 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 60 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 61 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 62 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 63 64 65 66 67 #define RESPONSE_START_STATUS_FTM_TM_OFFSET 0x0000000000000000 68 #define RESPONSE_START_STATUS_FTM_TM_LSB 3 69 #define RESPONSE_START_STATUS_FTM_TM_MSB 4 70 #define RESPONSE_START_STATUS_FTM_TM_MASK 0x0000000000000018 71 72 73 74 75 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 76 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 77 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 78 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 79 80 81 82 83 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 84 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 85 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 86 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 87 88 89 90 91 #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 92 #define RESPONSE_START_STATUS_RESERVED_LSB 13 93 #define RESPONSE_START_STATUS_RESERVED_MSB 31 94 #define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 95 96 97 98 99 #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 100 #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 101 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 102 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 103 104 105 106 107 #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 108 #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 109 #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 110 #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 111 112 113 114 #endif 115