1 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 21 22 23 24 25 26 27 #ifndef _RU_ALLOCATION_160_INFO_H_ 28 #define _RU_ALLOCATION_160_INFO_H_ 29 #if !defined(__ASSEMBLER__) 30 #endif 31 32 #define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 33 34 35 struct ru_allocation_160_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t ru_allocation_band0_0 : 9, // [8:0] 38 ru_allocation_band0_1 : 9, // [17:9] 39 reserved_0a : 6, // [23:18] 40 ru_allocations_01_subband80_mask : 4, // [27:24] 41 ru_allocations_23_subband80_mask : 4; // [31:28] 42 uint32_t ru_allocation_band0_2 : 9, // [8:0] 43 ru_allocation_band0_3 : 9, // [17:9] 44 reserved_1a : 14; // [31:18] 45 uint32_t ru_allocation_band1_0 : 9, // [8:0] 46 ru_allocation_band1_1 : 9, // [17:9] 47 reserved_2a : 14; // [31:18] 48 uint32_t ru_allocation_band1_2 : 9, // [8:0] 49 ru_allocation_band1_3 : 9, // [17:9] 50 reserved_3a : 14; // [31:18] 51 #else 52 uint32_t ru_allocations_23_subband80_mask : 4, // [31:28] 53 ru_allocations_01_subband80_mask : 4, // [27:24] 54 reserved_0a : 6, // [23:18] 55 ru_allocation_band0_1 : 9, // [17:9] 56 ru_allocation_band0_0 : 9; // [8:0] 57 uint32_t reserved_1a : 14, // [31:18] 58 ru_allocation_band0_3 : 9, // [17:9] 59 ru_allocation_band0_2 : 9; // [8:0] 60 uint32_t reserved_2a : 14, // [31:18] 61 ru_allocation_band1_1 : 9, // [17:9] 62 ru_allocation_band1_0 : 9; // [8:0] 63 uint32_t reserved_3a : 14, // [31:18] 64 ru_allocation_band1_3 : 9, // [17:9] 65 ru_allocation_band1_2 : 9; // [8:0] 66 #endif 67 }; 68 69 70 71 72 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 73 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 74 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 75 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff 76 77 78 79 80 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 81 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 82 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 83 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 84 85 86 87 88 #define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 89 #define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 90 #define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 91 #define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 92 93 94 95 96 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 97 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 98 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 99 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 100 101 102 103 104 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 105 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 106 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 107 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 108 109 110 111 112 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 113 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 114 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 115 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff 116 117 118 119 120 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 121 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 122 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 123 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 124 125 126 127 128 #define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 129 #define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 130 #define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 131 #define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 132 133 134 135 136 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 137 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 138 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 139 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff 140 141 142 143 144 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 145 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 146 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 147 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 148 149 150 151 152 #define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 153 #define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 154 #define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 155 #define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 156 157 158 159 160 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c 161 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 162 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 163 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff 164 165 166 167 168 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c 169 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 170 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 171 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 172 173 174 175 176 #define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c 177 #define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 178 #define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 179 #define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 180 181 182 183 #endif 184