1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_END_H_ 27 #define _RX_MPDU_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MPDU_END 4 32 33 #define NUM_OF_QWORDS_RX_MPDU_END 2 34 35 36 struct rx_mpdu_end { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, 39 sw_frame_group_id : 7, 40 reserved_0 : 7, 41 phy_ppdu_id : 16; 42 uint32_t reserved_1a : 11, 43 unsup_ktype_short_frame : 1, 44 rx_in_tx_decrypt_byp : 1, 45 overflow_err : 1, 46 mpdu_length_err : 1, 47 tkip_mic_err : 1, 48 decrypt_err : 1, 49 unencrypted_frame_err : 1, 50 pn_fields_contain_valid_info : 1, 51 fcs_err : 1, 52 msdu_length_err : 1, 53 rxdma0_destination_ring : 3, 54 rxdma1_destination_ring : 3, 55 decrypt_status_code : 3, 56 rx_bitmap_not_updated : 1, 57 reserved_1b : 1; 58 uint32_t reserved_2a : 15, 59 rxpcu_mgmt_sequence_nr_valid : 1, 60 rxpcu_mgmt_sequence_nr : 16; 61 uint32_t rxframe_assert_mlo_timestamp : 32; 62 #else 63 uint32_t phy_ppdu_id : 16, 64 reserved_0 : 7, 65 sw_frame_group_id : 7, 66 rxpcu_mpdu_filter_in_category : 2; 67 uint32_t reserved_1b : 1, 68 rx_bitmap_not_updated : 1, 69 decrypt_status_code : 3, 70 rxdma1_destination_ring : 3, 71 rxdma0_destination_ring : 3, 72 msdu_length_err : 1, 73 fcs_err : 1, 74 pn_fields_contain_valid_info : 1, 75 unencrypted_frame_err : 1, 76 decrypt_err : 1, 77 tkip_mic_err : 1, 78 mpdu_length_err : 1, 79 overflow_err : 1, 80 rx_in_tx_decrypt_byp : 1, 81 unsup_ktype_short_frame : 1, 82 reserved_1a : 11; 83 uint32_t rxpcu_mgmt_sequence_nr : 16, 84 rxpcu_mgmt_sequence_nr_valid : 1, 85 reserved_2a : 15; 86 uint32_t rxframe_assert_mlo_timestamp : 32; 87 #endif 88 }; 89 90 91 92 93 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 94 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 95 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 96 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 97 98 99 100 101 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 102 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 103 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 104 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 105 106 107 108 109 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 110 #define RX_MPDU_END_RESERVED_0_LSB 9 111 #define RX_MPDU_END_RESERVED_0_MSB 15 112 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 113 114 115 116 117 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 118 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 119 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 120 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 121 122 123 124 125 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 126 #define RX_MPDU_END_RESERVED_1A_LSB 32 127 #define RX_MPDU_END_RESERVED_1A_MSB 42 128 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 129 130 131 132 133 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 134 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 135 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 136 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 137 138 139 140 141 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 142 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 143 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 144 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 145 146 147 148 149 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 150 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 151 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 152 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 153 154 155 156 157 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 158 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 159 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 160 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 161 162 163 164 165 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 166 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 167 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 168 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 169 170 171 172 173 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 174 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 175 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 176 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 177 178 179 180 181 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 182 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 183 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 184 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 185 186 187 188 189 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 190 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 191 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 192 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 193 194 195 196 197 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 198 #define RX_MPDU_END_FCS_ERR_LSB 51 199 #define RX_MPDU_END_FCS_ERR_MSB 51 200 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 201 202 203 204 205 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 206 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 207 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 208 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 209 210 211 212 213 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 214 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 215 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 216 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 217 218 219 220 221 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 222 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 223 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 224 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 225 226 227 228 229 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 230 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 231 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 232 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 233 234 235 236 237 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 238 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 239 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 240 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 241 242 243 244 245 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 246 #define RX_MPDU_END_RESERVED_1B_LSB 63 247 #define RX_MPDU_END_RESERVED_1B_MSB 63 248 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 249 250 251 252 253 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 254 #define RX_MPDU_END_RESERVED_2A_LSB 0 255 #define RX_MPDU_END_RESERVED_2A_MSB 14 256 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 257 258 259 260 261 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 262 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 263 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 264 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 265 266 267 268 269 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 270 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 271 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 272 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 273 274 275 276 277 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 278 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 279 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 280 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 281 282 283 284 #endif 285