1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_DESC_INFO_H_ 27 #define _RX_MSDU_DESC_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 32 33 34 struct rx_msdu_desc_info { 35 #ifndef BIG_ENDIAN_HOST 36 uint32_t first_msdu_in_mpdu_flag : 1, 37 last_msdu_in_mpdu_flag : 1, 38 msdu_continuation : 1, 39 msdu_length : 14, 40 msdu_drop : 1, 41 sa_is_valid : 1, 42 da_is_valid : 1, 43 da_is_mcbc : 1, 44 l3_header_padding_msb : 1, 45 tcp_udp_chksum_fail : 1, 46 ip_chksum_fail : 1, 47 fr_ds : 1, 48 to_ds : 1, 49 intra_bss : 1, 50 dest_chip_id : 2, 51 decap_format : 2, 52 reserved_0a : 1; 53 #else 54 uint32_t reserved_0a : 1, 55 decap_format : 2, 56 dest_chip_id : 2, 57 intra_bss : 1, 58 to_ds : 1, 59 fr_ds : 1, 60 ip_chksum_fail : 1, 61 tcp_udp_chksum_fail : 1, 62 l3_header_padding_msb : 1, 63 da_is_mcbc : 1, 64 da_is_valid : 1, 65 sa_is_valid : 1, 66 msdu_drop : 1, 67 msdu_length : 14, 68 msdu_continuation : 1, 69 last_msdu_in_mpdu_flag : 1, 70 first_msdu_in_mpdu_flag : 1; 71 #endif 72 }; 73 74 75 76 77 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 78 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 79 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 80 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 81 82 83 84 85 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 86 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 87 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 88 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 89 90 91 92 93 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 94 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 95 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 96 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 97 98 99 100 101 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 102 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 103 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 104 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 105 106 107 108 109 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 110 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 111 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 112 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 113 114 115 116 117 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 118 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 119 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 120 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 121 122 123 124 125 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 126 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 127 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 128 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 129 130 131 132 133 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 134 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 135 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 136 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 137 138 139 140 141 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 142 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 143 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 144 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 145 146 147 148 149 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 150 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 151 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 152 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 153 154 155 156 157 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 158 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 159 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 160 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 161 162 163 164 165 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 166 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 167 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 168 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 169 170 171 172 173 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 174 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 175 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 176 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 177 178 179 180 181 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 182 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 183 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 184 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 185 186 187 188 189 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 190 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 191 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 192 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 193 194 195 196 197 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 198 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 199 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 200 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 201 202 203 204 205 #define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 206 #define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 31 207 #define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31 208 #define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0x80000000 209 210 211 212 #endif 213