1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _RX_PPDU_START_H_ 27*5113495bSYour Name #define _RX_PPDU_START_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #define NUM_OF_DWORDS_RX_PPDU_START 6 32*5113495bSYour Name 33*5113495bSYour Name #define NUM_OF_QWORDS_RX_PPDU_START 3 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct rx_ppdu_start { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name uint32_t phy_ppdu_id : 16, 39*5113495bSYour Name preamble_time_to_rxframe : 8, 40*5113495bSYour Name reserved_0a : 8; 41*5113495bSYour Name uint32_t sw_phy_meta_data : 32; 42*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; 43*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; 44*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; 45*5113495bSYour Name uint32_t tlv64_padding : 32; 46*5113495bSYour Name #else 47*5113495bSYour Name uint32_t reserved_0a : 8, 48*5113495bSYour Name preamble_time_to_rxframe : 8, 49*5113495bSYour Name phy_ppdu_id : 16; 50*5113495bSYour Name uint32_t sw_phy_meta_data : 32; 51*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; 52*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; 53*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; 54*5113495bSYour Name uint32_t tlv64_padding : 32; 55*5113495bSYour Name #endif 56*5113495bSYour Name }; 57*5113495bSYour Name 58*5113495bSYour Name 59*5113495bSYour Name 60*5113495bSYour Name 61*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 62*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 63*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 64*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 65*5113495bSYour Name 66*5113495bSYour Name 67*5113495bSYour Name 68*5113495bSYour Name 69*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 70*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 71*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 72*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 73*5113495bSYour Name 74*5113495bSYour Name 75*5113495bSYour Name 76*5113495bSYour Name 77*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 78*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_LSB 24 79*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MSB 31 80*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 81*5113495bSYour Name 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name 85*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 86*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 87*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 88*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 89*5113495bSYour Name 90*5113495bSYour Name 91*5113495bSYour Name 92*5113495bSYour Name 93*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 94*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 95*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 96*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 97*5113495bSYour Name 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name 101*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 102*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 103*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 104*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 105*5113495bSYour Name 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name 109*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 110*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 111*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 112*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 113*5113495bSYour Name 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name 117*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 118*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_LSB 32 119*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_MSB 63 120*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 121*5113495bSYour Name 122*5113495bSYour Name 123*5113495bSYour Name 124*5113495bSYour Name #endif 125