1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_1K_H_ 18 #define _RX_REO_QUEUE_1K_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 24 25 26 struct rx_reo_queue_1k { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct uniform_descriptor_header descriptor_header; 29 uint32_t rx_bitmap_319_288 : 32; 30 uint32_t rx_bitmap_351_320 : 32; 31 uint32_t rx_bitmap_383_352 : 32; 32 uint32_t rx_bitmap_415_384 : 32; 33 uint32_t rx_bitmap_447_416 : 32; 34 uint32_t rx_bitmap_479_448 : 32; 35 uint32_t rx_bitmap_511_480 : 32; 36 uint32_t rx_bitmap_543_512 : 32; 37 uint32_t rx_bitmap_575_544 : 32; 38 uint32_t rx_bitmap_607_576 : 32; 39 uint32_t rx_bitmap_639_608 : 32; 40 uint32_t rx_bitmap_671_640 : 32; 41 uint32_t rx_bitmap_703_672 : 32; 42 uint32_t rx_bitmap_735_704 : 32; 43 uint32_t rx_bitmap_767_736 : 32; 44 uint32_t rx_bitmap_799_768 : 32; 45 uint32_t rx_bitmap_831_800 : 32; 46 uint32_t rx_bitmap_863_832 : 32; 47 uint32_t rx_bitmap_895_864 : 32; 48 uint32_t rx_bitmap_927_896 : 32; 49 uint32_t rx_bitmap_959_928 : 32; 50 uint32_t rx_bitmap_991_960 : 32; 51 uint32_t rx_bitmap_1023_992 : 32; 52 uint32_t reserved_24 : 32; 53 uint32_t reserved_25 : 32; 54 uint32_t reserved_26 : 32; 55 uint32_t reserved_27 : 32; 56 uint32_t reserved_28 : 32; 57 uint32_t reserved_29 : 32; 58 uint32_t reserved_30 : 32; 59 uint32_t reserved_31 : 32; 60 #else 61 struct uniform_descriptor_header descriptor_header; 62 uint32_t rx_bitmap_319_288 : 32; 63 uint32_t rx_bitmap_351_320 : 32; 64 uint32_t rx_bitmap_383_352 : 32; 65 uint32_t rx_bitmap_415_384 : 32; 66 uint32_t rx_bitmap_447_416 : 32; 67 uint32_t rx_bitmap_479_448 : 32; 68 uint32_t rx_bitmap_511_480 : 32; 69 uint32_t rx_bitmap_543_512 : 32; 70 uint32_t rx_bitmap_575_544 : 32; 71 uint32_t rx_bitmap_607_576 : 32; 72 uint32_t rx_bitmap_639_608 : 32; 73 uint32_t rx_bitmap_671_640 : 32; 74 uint32_t rx_bitmap_703_672 : 32; 75 uint32_t rx_bitmap_735_704 : 32; 76 uint32_t rx_bitmap_767_736 : 32; 77 uint32_t rx_bitmap_799_768 : 32; 78 uint32_t rx_bitmap_831_800 : 32; 79 uint32_t rx_bitmap_863_832 : 32; 80 uint32_t rx_bitmap_895_864 : 32; 81 uint32_t rx_bitmap_927_896 : 32; 82 uint32_t rx_bitmap_959_928 : 32; 83 uint32_t rx_bitmap_991_960 : 32; 84 uint32_t rx_bitmap_1023_992 : 32; 85 uint32_t reserved_24 : 32; 86 uint32_t reserved_25 : 32; 87 uint32_t reserved_26 : 32; 88 uint32_t reserved_27 : 32; 89 uint32_t reserved_28 : 32; 90 uint32_t reserved_29 : 32; 91 uint32_t reserved_30 : 32; 92 uint32_t reserved_31 : 32; 93 #endif 94 }; 95 96 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 97 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 98 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 99 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 100 101 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 102 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 103 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 104 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 105 106 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 107 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 108 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 109 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 110 111 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 112 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 113 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 114 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 115 116 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 117 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 118 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 119 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 120 121 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 122 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 123 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 124 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 125 126 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 127 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 128 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 129 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 130 131 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 132 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 133 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 134 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 135 136 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 137 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 138 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 139 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 140 141 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 142 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 143 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 144 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 145 146 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 147 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 148 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 149 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 150 151 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 152 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 153 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 154 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 155 156 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 157 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 158 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 159 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 160 161 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 162 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 163 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 164 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 165 166 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 167 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 168 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 169 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 170 171 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 172 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 173 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 174 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 175 176 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 177 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 178 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 179 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 180 181 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 182 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 183 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 184 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 185 186 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 187 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 188 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 189 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 190 191 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 192 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 193 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 194 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 195 196 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 197 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 198 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 199 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 200 201 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 202 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 203 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 204 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 205 206 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 207 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 208 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 209 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 210 211 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 212 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 213 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 214 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 215 216 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 217 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 218 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 219 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 220 221 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 222 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 223 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 224 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 225 226 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 227 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 228 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 229 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 230 231 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 232 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 233 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 234 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 235 236 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 237 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 238 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 239 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 240 241 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 242 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 243 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 244 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 245 246 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 247 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 248 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 249 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 250 251 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 252 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 253 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 254 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 255 256 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 257 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 258 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 259 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 260 261 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 262 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 263 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 264 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 265 266 #endif 267