xref: /wlan-driver/fw-api/hw/qcn9224/v1/rx_timing_offset_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _RX_TIMING_OFFSET_INFO_H_
27 #define _RX_TIMING_OFFSET_INFO_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
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33 
34 struct rx_timing_offset_info {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t residual_phase_offset                                   : 12,
37                       reserved                                                : 20;
38 #else
39              uint32_t reserved                                                : 20,
40                       residual_phase_offset                                   : 12;
41 #endif
42 };
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46 
47 #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                          0x00000000
48 #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB                             0
49 #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB                             11
50 #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK                            0x00000fff
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55 #define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET                                       0x00000000
56 #define RX_TIMING_OFFSET_INFO_RESERVED_LSB                                          12
57 #define RX_TIMING_OFFSET_INFO_RESERVED_MSB                                          31
58 #define RX_TIMING_OFFSET_INFO_RESERVED_MASK                                         0xfffff000
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61 
62 #endif
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