1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_GSE_CMD_H_ 27 #define _TCL_GSE_CMD_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 32 33 34 struct tcl_gse_cmd { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t control_buffer_addr_31_0 : 32; 37 uint32_t control_buffer_addr_39_32 : 8, 38 gse_ctrl : 4, 39 gse_sel : 1, 40 status_destination_ring_id : 1, 41 swap : 1, 42 index_search_en : 1, 43 cache_set_num : 4, 44 reserved_1a : 12; 45 uint32_t tcl_cmd_type : 1, 46 reserved_2a : 31; 47 uint32_t cmd_meta_data_31_0 : 32; 48 uint32_t cmd_meta_data_63_32 : 32; 49 uint32_t reserved_5a : 32; 50 uint32_t reserved_6a : 32; 51 uint32_t reserved_7a : 20, 52 ring_id : 8, 53 looping_count : 4; 54 #else 55 uint32_t control_buffer_addr_31_0 : 32; 56 uint32_t reserved_1a : 12, 57 cache_set_num : 4, 58 index_search_en : 1, 59 swap : 1, 60 status_destination_ring_id : 1, 61 gse_sel : 1, 62 gse_ctrl : 4, 63 control_buffer_addr_39_32 : 8; 64 uint32_t reserved_2a : 31, 65 tcl_cmd_type : 1; 66 uint32_t cmd_meta_data_31_0 : 32; 67 uint32_t cmd_meta_data_63_32 : 32; 68 uint32_t reserved_5a : 32; 69 uint32_t reserved_6a : 32; 70 uint32_t looping_count : 4, 71 ring_id : 8, 72 reserved_7a : 20; 73 #endif 74 }; 75 76 77 78 79 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 80 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 81 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 82 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 83 84 85 86 87 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 88 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 89 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 90 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 91 92 93 94 95 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 96 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 97 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 98 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 99 100 101 102 103 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 104 #define TCL_GSE_CMD_GSE_SEL_LSB 12 105 #define TCL_GSE_CMD_GSE_SEL_MSB 12 106 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 107 108 109 110 111 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 112 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 113 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 114 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 115 116 117 118 119 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 120 #define TCL_GSE_CMD_SWAP_LSB 14 121 #define TCL_GSE_CMD_SWAP_MSB 14 122 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 123 124 125 126 127 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 128 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 129 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 130 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 131 132 133 134 135 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 136 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 137 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 138 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 139 140 141 142 143 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 144 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 145 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 146 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 147 148 149 150 151 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 152 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 153 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 154 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 155 156 157 158 159 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 160 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 161 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 162 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 163 164 165 166 167 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 168 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 169 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 170 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 171 172 173 174 175 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 176 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 177 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 178 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 179 180 181 182 183 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 184 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 185 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 186 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 187 188 189 190 191 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 192 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 193 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 194 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 195 196 197 198 199 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 200 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 201 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 202 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 203 204 205 206 207 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 208 #define TCL_GSE_CMD_RING_ID_LSB 20 209 #define TCL_GSE_CMD_RING_ID_MSB 27 210 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 211 212 213 214 215 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 216 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 217 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 218 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 219 220 221 222 #endif 223