1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_SETUP_H_ 27 #define _TX_FES_SETUP_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_FES_SETUP 10 32 33 #define NUM_OF_QWORDS_TX_FES_SETUP 5 34 35 36 struct tx_fes_setup { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t schedule_id : 32; 39 uint32_t fes_in_11ax_trigger_response_config : 1, 40 bo_based_tid_aggregation_limit : 4, 41 ranging : 1, 42 expect_i2r_lmr : 1, 43 transmit_start_reason : 3, 44 use_alt_power_sr : 1, 45 static_2_pwr_mode_status : 1, 46 obss_srg_opport_transmit_status : 1, 47 srp_based_transmit_status : 1, 48 obss_pd_based_transmit_status : 1, 49 puncture_from_all_allowed_modes : 1, 50 schedule_cmd_ring_id : 5, 51 fes_control_mode : 2, 52 number_of_users : 6, 53 mu_type : 1, 54 ofdma_triggered_response : 1, 55 response_to_response_cmd : 1; 56 uint32_t schedule_try : 4, 57 ndp_frame : 2, 58 txbf : 1, 59 allow_txop_exceed_in_1st_pkt : 1, 60 ignore_bw_available : 1, 61 ignore_tbtt : 1, 62 static_bandwidth : 3, 63 set_txop_duration_all_ones : 1, 64 transmission_contains_mu_rts : 1, 65 bw_restricted_frames_embedded : 1, 66 ast_index : 16; 67 uint32_t cv_id : 8, 68 trigger_resp_txpdu_ppdu_boundary : 2, 69 rxpcu_setup_complete_present : 1, 70 rbo_must_have_data_user_limit : 4, 71 mu_ndp : 1, 72 bf_type : 2, 73 cbf_nc_index_mask : 1, 74 cbf_nc_index : 3, 75 cbf_nr_index_mask : 1, 76 cbf_nr_index : 3, 77 secure_ranging_ista : 1, 78 ndpa : 1, 79 wait_sifs : 2, 80 cbf_feedback_type_mask : 1, 81 cbf_feedback_type : 1; 82 uint32_t cbf_sounding_token : 6, 83 cbf_sounding_token_mask : 1, 84 cbf_bw_mask : 1, 85 cbf_bw : 3, 86 use_static_bw : 1, 87 coex_nack_count : 5, 88 sch_tx_burst_ongoing : 1, 89 gen_tqm_update_mpdu_count_tlv : 1, 90 transmit_vif : 4, 91 optimal_bw_retry_count : 4, 92 fes_continuation_ratio_threshold : 5; 93 uint32_t transmit_cca_bitmap : 32; 94 uint32_t tb_ranging : 1, 95 ranging_trigger_subtype : 4, 96 min_cts2self_count : 4, 97 max_cts2self_count : 4, 98 wifi_radar_enable : 1, 99 reserved_6a : 18; 100 uint32_t monitor_override_sta_31_0 : 32; 101 uint32_t monitor_override_sta_36_32 : 5, 102 reserved_8a : 27; 103 uint32_t fw2sw_info : 32; 104 #else 105 uint32_t schedule_id : 32; 106 uint32_t response_to_response_cmd : 1, 107 ofdma_triggered_response : 1, 108 mu_type : 1, 109 number_of_users : 6, 110 fes_control_mode : 2, 111 schedule_cmd_ring_id : 5, 112 puncture_from_all_allowed_modes : 1, 113 obss_pd_based_transmit_status : 1, 114 srp_based_transmit_status : 1, 115 obss_srg_opport_transmit_status : 1, 116 static_2_pwr_mode_status : 1, 117 use_alt_power_sr : 1, 118 transmit_start_reason : 3, 119 expect_i2r_lmr : 1, 120 ranging : 1, 121 bo_based_tid_aggregation_limit : 4, 122 fes_in_11ax_trigger_response_config : 1; 123 uint32_t ast_index : 16, 124 bw_restricted_frames_embedded : 1, 125 transmission_contains_mu_rts : 1, 126 set_txop_duration_all_ones : 1, 127 static_bandwidth : 3, 128 ignore_tbtt : 1, 129 ignore_bw_available : 1, 130 allow_txop_exceed_in_1st_pkt : 1, 131 txbf : 1, 132 ndp_frame : 2, 133 schedule_try : 4; 134 uint32_t cbf_feedback_type : 1, 135 cbf_feedback_type_mask : 1, 136 wait_sifs : 2, 137 ndpa : 1, 138 secure_ranging_ista : 1, 139 cbf_nr_index : 3, 140 cbf_nr_index_mask : 1, 141 cbf_nc_index : 3, 142 cbf_nc_index_mask : 1, 143 bf_type : 2, 144 mu_ndp : 1, 145 rbo_must_have_data_user_limit : 4, 146 rxpcu_setup_complete_present : 1, 147 trigger_resp_txpdu_ppdu_boundary : 2, 148 cv_id : 8; 149 uint32_t fes_continuation_ratio_threshold : 5, 150 optimal_bw_retry_count : 4, 151 transmit_vif : 4, 152 gen_tqm_update_mpdu_count_tlv : 1, 153 sch_tx_burst_ongoing : 1, 154 coex_nack_count : 5, 155 use_static_bw : 1, 156 cbf_bw : 3, 157 cbf_bw_mask : 1, 158 cbf_sounding_token_mask : 1, 159 cbf_sounding_token : 6; 160 uint32_t transmit_cca_bitmap : 32; 161 uint32_t reserved_6a : 18, 162 wifi_radar_enable : 1, 163 max_cts2self_count : 4, 164 min_cts2self_count : 4, 165 ranging_trigger_subtype : 4, 166 tb_ranging : 1; 167 uint32_t monitor_override_sta_31_0 : 32; 168 uint32_t reserved_8a : 27, 169 monitor_override_sta_36_32 : 5; 170 uint32_t fw2sw_info : 32; 171 #endif 172 }; 173 174 175 176 177 #define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 178 #define TX_FES_SETUP_SCHEDULE_ID_LSB 0 179 #define TX_FES_SETUP_SCHEDULE_ID_MSB 31 180 #define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff 181 182 183 184 185 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 186 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 187 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 188 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 189 190 191 192 193 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 194 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 195 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 196 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 197 198 199 200 201 #define TX_FES_SETUP_RANGING_OFFSET 0x0000000000000000 202 #define TX_FES_SETUP_RANGING_LSB 37 203 #define TX_FES_SETUP_RANGING_MSB 37 204 #define TX_FES_SETUP_RANGING_MASK 0x0000002000000000 205 206 207 208 209 #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 210 #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 211 #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 212 #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 213 214 215 216 217 #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 218 #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 219 #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 220 #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 221 222 223 224 225 #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 226 #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 227 #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 228 #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 229 230 231 232 233 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 234 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 235 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 236 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 237 238 239 240 241 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 242 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 243 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 244 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 245 246 247 248 249 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 250 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 251 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 252 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 253 254 255 256 257 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 258 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 259 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 260 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 261 262 263 264 265 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 266 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 267 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 268 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 269 270 271 272 273 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 274 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 275 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 276 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 277 278 279 280 281 #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 282 #define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 283 #define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 284 #define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 285 286 287 288 289 #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 290 #define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 291 #define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 292 #define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 293 294 295 296 297 #define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 298 #define TX_FES_SETUP_MU_TYPE_LSB 61 299 #define TX_FES_SETUP_MU_TYPE_MSB 61 300 #define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 301 302 303 304 305 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 306 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 307 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 308 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 309 310 311 312 313 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 314 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 315 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 316 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 317 318 319 320 321 #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 322 #define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 323 #define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 324 #define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f 325 326 327 328 329 #define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 330 #define TX_FES_SETUP_NDP_FRAME_LSB 4 331 #define TX_FES_SETUP_NDP_FRAME_MSB 5 332 #define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 333 334 335 336 337 #define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 338 #define TX_FES_SETUP_TXBF_LSB 6 339 #define TX_FES_SETUP_TXBF_MSB 6 340 #define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 341 342 343 344 345 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 346 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 347 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 348 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 349 350 351 352 353 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 354 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 355 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 356 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 357 358 359 360 361 #define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 362 #define TX_FES_SETUP_IGNORE_TBTT_LSB 9 363 #define TX_FES_SETUP_IGNORE_TBTT_MSB 9 364 #define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 365 366 367 368 369 #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 370 #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 371 #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 372 #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 373 374 375 376 377 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 378 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 379 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 380 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 381 382 383 384 385 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 386 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 387 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 388 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 389 390 391 392 393 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 394 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 395 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 396 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 397 398 399 400 401 #define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 402 #define TX_FES_SETUP_AST_INDEX_LSB 16 403 #define TX_FES_SETUP_AST_INDEX_MSB 31 404 #define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 405 406 407 408 409 #define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 410 #define TX_FES_SETUP_CV_ID_LSB 32 411 #define TX_FES_SETUP_CV_ID_MSB 39 412 #define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 413 414 415 416 417 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 418 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 419 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 420 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 421 422 423 424 425 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 426 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 427 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 428 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 429 430 431 432 433 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 434 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 435 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 436 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 437 438 439 440 441 #define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 442 #define TX_FES_SETUP_MU_NDP_LSB 47 443 #define TX_FES_SETUP_MU_NDP_MSB 47 444 #define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 445 446 447 448 449 #define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 450 #define TX_FES_SETUP_BF_TYPE_LSB 48 451 #define TX_FES_SETUP_BF_TYPE_MSB 49 452 #define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 453 454 455 456 457 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 458 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 459 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 460 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 461 462 463 464 465 #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 466 #define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 467 #define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 468 #define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 469 470 471 472 473 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 474 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 475 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 476 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 477 478 479 480 481 #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 482 #define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 483 #define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 484 #define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 485 486 487 488 489 #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 490 #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 491 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 492 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 493 494 495 496 497 #define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 498 #define TX_FES_SETUP_NDPA_LSB 59 499 #define TX_FES_SETUP_NDPA_MSB 59 500 #define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 501 502 503 504 505 #define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 506 #define TX_FES_SETUP_WAIT_SIFS_LSB 60 507 #define TX_FES_SETUP_WAIT_SIFS_MSB 61 508 #define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 509 510 511 512 513 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 514 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 515 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 516 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 517 518 519 520 521 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 522 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 523 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 524 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 525 526 527 528 529 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 530 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 531 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 532 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f 533 534 535 536 537 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 538 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 539 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 540 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 541 542 543 544 545 #define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 546 #define TX_FES_SETUP_CBF_BW_MASK_LSB 7 547 #define TX_FES_SETUP_CBF_BW_MASK_MSB 7 548 #define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 549 550 551 552 553 #define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 554 #define TX_FES_SETUP_CBF_BW_LSB 8 555 #define TX_FES_SETUP_CBF_BW_MSB 10 556 #define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 557 558 559 560 561 #define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 562 #define TX_FES_SETUP_USE_STATIC_BW_LSB 11 563 #define TX_FES_SETUP_USE_STATIC_BW_MSB 11 564 #define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 565 566 567 568 569 #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 570 #define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 571 #define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 572 #define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 573 574 575 576 577 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 578 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 579 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 580 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 581 582 583 584 585 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 586 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 587 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 588 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 589 590 591 592 593 #define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 594 #define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 595 #define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 596 #define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 597 598 599 600 601 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 602 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 603 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 604 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 605 606 607 608 609 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 610 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 611 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 612 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 613 614 615 616 617 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 618 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 619 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 620 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 621 622 623 624 625 #define TX_FES_SETUP_TB_RANGING_OFFSET 0x0000000000000018 626 #define TX_FES_SETUP_TB_RANGING_LSB 0 627 #define TX_FES_SETUP_TB_RANGING_MSB 0 628 #define TX_FES_SETUP_TB_RANGING_MASK 0x0000000000000001 629 630 631 632 633 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 634 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 635 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 636 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e 637 638 639 640 641 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 642 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 643 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 644 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 645 646 647 648 649 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 650 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 651 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 652 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 653 654 655 656 657 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 658 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 659 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 660 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 661 662 663 664 665 #define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 666 #define TX_FES_SETUP_RESERVED_6A_LSB 14 667 #define TX_FES_SETUP_RESERVED_6A_MSB 31 668 #define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 669 670 671 672 673 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 674 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 675 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 676 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 677 678 679 680 681 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 682 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 683 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 684 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f 685 686 687 688 689 #define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 690 #define TX_FES_SETUP_RESERVED_8A_LSB 5 691 #define TX_FES_SETUP_RESERVED_8A_MSB 31 692 #define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 693 694 695 696 697 #define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 698 #define TX_FES_SETUP_FW2SW_INFO_LSB 32 699 #define TX_FES_SETUP_FW2SW_INFO_MSB 63 700 #define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 701 702 703 704 #endif 705