1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_1K_BA_H_ 27 #define _TX_FES_STATUS_1K_BA_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 32 33 #define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 34 35 36 struct tx_fes_status_1k_ba { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t ack_ba_status_type : 1, 39 ba_type : 1, 40 ba_tid : 4, 41 unexpected_ack_or_ba : 1, 42 response_timeout : 1, 43 ack_frame_rssi : 8, 44 ssn : 12, 45 reserved_0b : 4; 46 uint32_t sw_peer_id : 16, 47 reserved_1a : 16; 48 uint32_t ba_bitmap_31_0 : 32; 49 uint32_t ba_bitmap_63_32 : 32; 50 uint32_t ba_bitmap_95_64 : 32; 51 uint32_t ba_bitmap_127_96 : 32; 52 uint32_t ba_bitmap_159_128 : 32; 53 uint32_t ba_bitmap_191_160 : 32; 54 uint32_t ba_bitmap_223_192 : 32; 55 uint32_t ba_bitmap_255_224 : 32; 56 uint32_t ba_bitmap_287_256 : 32; 57 uint32_t ba_bitmap_319_288 : 32; 58 uint32_t ba_bitmap_351_320 : 32; 59 uint32_t ba_bitmap_383_352 : 32; 60 uint32_t ba_bitmap_415_384 : 32; 61 uint32_t ba_bitmap_447_416 : 32; 62 uint32_t ba_bitmap_479_448 : 32; 63 uint32_t ba_bitmap_511_480 : 32; 64 uint32_t ba_bitmap_543_512 : 32; 65 uint32_t ba_bitmap_575_544 : 32; 66 uint32_t ba_bitmap_607_576 : 32; 67 uint32_t ba_bitmap_639_608 : 32; 68 uint32_t ba_bitmap_671_640 : 32; 69 uint32_t ba_bitmap_703_672 : 32; 70 uint32_t ba_bitmap_735_704 : 32; 71 uint32_t ba_bitmap_767_736 : 32; 72 uint32_t ba_bitmap_799_768 : 32; 73 uint32_t ba_bitmap_831_800 : 32; 74 uint32_t ba_bitmap_863_832 : 32; 75 uint32_t ba_bitmap_895_864 : 32; 76 uint32_t ba_bitmap_927_896 : 32; 77 uint32_t ba_bitmap_959_928 : 32; 78 uint32_t ba_bitmap_991_960 : 32; 79 uint32_t ba_bitmap_1023_992 : 32; 80 #else 81 uint32_t reserved_0b : 4, 82 ssn : 12, 83 ack_frame_rssi : 8, 84 response_timeout : 1, 85 unexpected_ack_or_ba : 1, 86 ba_tid : 4, 87 ba_type : 1, 88 ack_ba_status_type : 1; 89 uint32_t reserved_1a : 16, 90 sw_peer_id : 16; 91 uint32_t ba_bitmap_31_0 : 32; 92 uint32_t ba_bitmap_63_32 : 32; 93 uint32_t ba_bitmap_95_64 : 32; 94 uint32_t ba_bitmap_127_96 : 32; 95 uint32_t ba_bitmap_159_128 : 32; 96 uint32_t ba_bitmap_191_160 : 32; 97 uint32_t ba_bitmap_223_192 : 32; 98 uint32_t ba_bitmap_255_224 : 32; 99 uint32_t ba_bitmap_287_256 : 32; 100 uint32_t ba_bitmap_319_288 : 32; 101 uint32_t ba_bitmap_351_320 : 32; 102 uint32_t ba_bitmap_383_352 : 32; 103 uint32_t ba_bitmap_415_384 : 32; 104 uint32_t ba_bitmap_447_416 : 32; 105 uint32_t ba_bitmap_479_448 : 32; 106 uint32_t ba_bitmap_511_480 : 32; 107 uint32_t ba_bitmap_543_512 : 32; 108 uint32_t ba_bitmap_575_544 : 32; 109 uint32_t ba_bitmap_607_576 : 32; 110 uint32_t ba_bitmap_639_608 : 32; 111 uint32_t ba_bitmap_671_640 : 32; 112 uint32_t ba_bitmap_703_672 : 32; 113 uint32_t ba_bitmap_735_704 : 32; 114 uint32_t ba_bitmap_767_736 : 32; 115 uint32_t ba_bitmap_799_768 : 32; 116 uint32_t ba_bitmap_831_800 : 32; 117 uint32_t ba_bitmap_863_832 : 32; 118 uint32_t ba_bitmap_895_864 : 32; 119 uint32_t ba_bitmap_927_896 : 32; 120 uint32_t ba_bitmap_959_928 : 32; 121 uint32_t ba_bitmap_991_960 : 32; 122 uint32_t ba_bitmap_1023_992 : 32; 123 #endif 124 }; 125 126 127 128 129 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 130 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 131 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 132 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 133 134 135 136 137 #define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 138 #define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 139 #define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 140 #define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 141 142 143 144 145 #define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 146 #define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 147 #define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 148 #define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c 149 150 151 152 153 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 154 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 155 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 156 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 157 158 159 160 161 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 162 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 163 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 164 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 165 166 167 168 169 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 170 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 171 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 172 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 173 174 175 176 177 #define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 178 #define TX_FES_STATUS_1K_BA_SSN_LSB 16 179 #define TX_FES_STATUS_1K_BA_SSN_MSB 27 180 #define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 181 182 183 184 185 #define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 186 #define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 187 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 188 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 189 190 191 192 193 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 194 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 195 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 196 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 197 198 199 200 201 #define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 202 #define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 203 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 204 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 205 206 207 208 209 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 210 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 211 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 212 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 213 214 215 216 217 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 218 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 219 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 220 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 221 222 223 224 225 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 226 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 227 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 228 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 229 230 231 232 233 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 234 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 235 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 236 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 237 238 239 240 241 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 242 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 243 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 244 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 245 246 247 248 249 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 250 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 251 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 252 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 253 254 255 256 257 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 258 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 259 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 260 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 261 262 263 264 265 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 266 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 267 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 268 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 269 270 271 272 273 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 274 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 275 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 276 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff 277 278 279 280 281 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 282 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 283 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 284 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 285 286 287 288 289 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 290 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 291 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 292 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff 293 294 295 296 297 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 298 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 299 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 300 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 301 302 303 304 305 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 306 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 307 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 308 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff 309 310 311 312 313 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 314 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 315 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 316 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 317 318 319 320 321 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 322 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 323 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 324 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff 325 326 327 328 329 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 330 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 331 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 332 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 333 334 335 336 337 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 338 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 339 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 340 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff 341 342 343 344 345 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 346 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 347 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 348 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 349 350 351 352 353 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 354 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 355 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 356 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff 357 358 359 360 361 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 362 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 363 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 364 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 365 366 367 368 369 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 370 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 371 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 372 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff 373 374 375 376 377 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 378 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 379 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 380 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 381 382 383 384 385 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 386 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 387 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 388 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff 389 390 391 392 393 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 394 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 395 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 396 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 397 398 399 400 401 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 402 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 403 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 404 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff 405 406 407 408 409 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 410 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 411 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 412 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 413 414 415 416 417 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 418 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 419 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 420 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff 421 422 423 424 425 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 426 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 427 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 428 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 429 430 431 432 433 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 434 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 435 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 436 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff 437 438 439 440 441 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 442 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 443 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 444 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 445 446 447 448 449 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 450 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 451 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 452 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff 453 454 455 456 457 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 458 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 459 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 460 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 461 462 463 464 #endif 465