xref: /wlan-driver/fw-api/hw/qcn9224/v1/tx_fes_status_end.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _TX_FES_STATUS_END_H_
27 #define _TX_FES_STATUS_END_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "phytx_abort_request_info.h"
32 #define NUM_OF_DWORDS_TX_FES_STATUS_END 22
33 
34 #define NUM_OF_QWORDS_TX_FES_STATUS_END 11
35 
36 
37 struct tx_fes_status_end {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              uint32_t prot_coex_bt_tx_while_wlan_tx                           :  1,
40                       prot_coex_bt_tx_while_wlan_rx                           :  1,
41                       prot_coex_wan_tx_while_wlan_tx                          :  1,
42                       prot_coex_wan_tx_while_wlan_rx                          :  1,
43                       prot_coex_wlan_tx_while_wlan_tx                         :  1,
44                       prot_coex_wlan_tx_while_wlan_rx                         :  1,
45                       coex_bt_tx_while_wlan_tx                                :  1,
46                       coex_bt_tx_while_wlan_rx                                :  1,
47                       coex_wan_tx_while_wlan_tx                               :  1,
48                       coex_wan_tx_while_wlan_rx                               :  1,
49                       coex_wlan_tx_while_wlan_tx                              :  1,
50                       coex_wlan_tx_while_wlan_rx                              :  1,
51                       global_data_underflow_warning                           :  1,
52                       global_fes_transmit_result                              :  4,
53                       cbf_bw_received_valid                                   :  1,
54                       cbf_bw_received                                         :  3,
55                       actual_received_ack_type                                :  4,
56                       sta_response_count                                      :  6,
57                       dpdtrain_done                                           :  1;
58              struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
59              uint16_t reserved_after_struct16                                 :  4,
60                       brp_info_valid                                          :  1,
61                       reserved_1a                                             :  6,
62                       phytx_pkt_end_info_valid                                :  1,
63                       phytx_abort_request_info_valid                          :  1,
64                       fes_in_11ax_trigger_response_config                     :  1,
65                       null_delim_inserted_before_mpdus                        :  1,
66                       only_null_delim_sent                                    :  1;
67              uint32_t start_of_frame_timestamp_15_0                           : 16,
68                       start_of_frame_timestamp_31_16                          : 16;
69              uint32_t end_of_frame_timestamp_15_0                             : 16,
70                       end_of_frame_timestamp_31_16                            : 16;
71              uint32_t terminate_ranging_sequence                              :  1,
72                       reserved_4a                                             :  7,
73                       timing_status                                           :  2,
74                       response_type                                           :  5,
75                       r2r_end_status_to_follow                                :  1,
76                       transmit_delay                                          : 16;
77              uint32_t tx_group_delay                                          : 12,
78                       reserved_5a                                             :  4,
79                       tpc_dbg_info_cmn_15_0                                   : 16;
80              uint32_t tpc_dbg_info_cmn_31_16                                  : 16,
81                       tpc_dbg_info_47_32                                      : 16;
82              uint32_t tpc_dbg_info_chn1_15_0                                  : 16,
83                       tpc_dbg_info_chn1_31_16                                 : 16;
84              uint32_t tpc_dbg_info_chn1_47_32                                 : 16,
85                       tpc_dbg_info_chn1_63_48                                 : 16;
86              uint32_t tpc_dbg_info_chn1_79_64                                 : 16,
87                       tpc_dbg_info_chn2_15_0                                  : 16;
88              uint32_t tpc_dbg_info_chn2_31_16                                 : 16,
89                       tpc_dbg_info_chn2_47_32                                 : 16;
90              uint32_t tpc_dbg_info_chn2_63_48                                 : 16,
91                       tpc_dbg_info_chn2_79_64                                 : 16;
92              uint32_t phytx_tx_end_sw_info_15_0                               : 16,
93                       phytx_tx_end_sw_info_31_16                              : 16;
94              uint32_t phytx_tx_end_sw_info_47_32                              : 16,
95                       phytx_tx_end_sw_info_63_48                              : 16;
96              uint32_t beamform_masked_user_bitmap_15_0                        : 16,
97                       beamform_masked_user_bitmap_31_16                       : 16;
98              uint32_t cbf_segment_request_mask                                :  8,
99                       cbf_segment_sent_mask                                   :  8,
100                       highest_achieved_data_null_ratio                        :  5,
101                       use_alt_power_sr                                        :  1,
102                       static_2_pwr_mode_status                                :  1,
103                       obss_srg_opport_transmit_status                         :  1,
104                       srp_based_transmit_status                               :  1,
105                       obss_pd_based_transmit_status                           :  1,
106                       beamform_masked_user_bitmap_36_32                       :  5,
107                       pdg_mpdu_ready                                          :  1;
108              uint32_t pdg_mpdu_count                                          : 16,
109                       pdg_est_mpdu_tx_count                                   : 16;
110              uint32_t pdg_overview_length                                     : 24,
111                       txop_duration                                           :  7,
112                       pdg_dropped_mpdu_warning                                :  1;
113              uint32_t packet_extension_a_factor                               :  2,
114                       packet_extension_pe_disambiguity                        :  1,
115                       packet_extension                                        :  3,
116                       fec_type                                                :  1,
117                       stbc                                                    :  1,
118                       num_data_symbols                                        : 16,
119                       ru_size                                                 :  4,
120                       reserved_17a                                            :  4;
121              uint32_t num_ltf_symbols                                         :  3,
122                       ltf_size                                                :  2,
123                       cp_setting                                              :  2,
124                       reserved_18a                                            :  5,
125                       dcm                                                     :  1,
126                       ldpc_extra_symbol                                       :  1,
127                       force_extra_symbol                                      :  1,
128                       reserved_18b                                            :  1,
129                       tx_pwr_shared                                           :  8,
130                       tx_pwr_unshared                                         :  8;
131              uint32_t ranging_active_user_map                                 : 16,
132                       ranging_sent_dummy_tx                                   :  1,
133                       ranging_ftm_frame_sent                                  :  1,
134                       reserved_20a                                            :  6,
135                       cv_corr_status                                          :  8;
136              uint32_t current_tx_duration                                     : 16,
137                       reserved_21a                                            : 16;
138 #else
139              uint32_t dpdtrain_done                                           :  1,
140                       sta_response_count                                      :  6,
141                       actual_received_ack_type                                :  4,
142                       cbf_bw_received                                         :  3,
143                       cbf_bw_received_valid                                   :  1,
144                       global_fes_transmit_result                              :  4,
145                       global_data_underflow_warning                           :  1,
146                       coex_wlan_tx_while_wlan_rx                              :  1,
147                       coex_wlan_tx_while_wlan_tx                              :  1,
148                       coex_wan_tx_while_wlan_rx                               :  1,
149                       coex_wan_tx_while_wlan_tx                               :  1,
150                       coex_bt_tx_while_wlan_rx                                :  1,
151                       coex_bt_tx_while_wlan_tx                                :  1,
152                       prot_coex_wlan_tx_while_wlan_rx                         :  1,
153                       prot_coex_wlan_tx_while_wlan_tx                         :  1,
154                       prot_coex_wan_tx_while_wlan_rx                          :  1,
155                       prot_coex_wan_tx_while_wlan_tx                          :  1,
156                       prot_coex_bt_tx_while_wlan_rx                           :  1,
157                       prot_coex_bt_tx_while_wlan_tx                           :  1;
158              uint32_t only_null_delim_sent                                    :  1,
159                       null_delim_inserted_before_mpdus                        :  1,
160                       fes_in_11ax_trigger_response_config                     :  1,
161                       phytx_abort_request_info_valid                          :  1,
162                       phytx_pkt_end_info_valid                                :  1,
163                       reserved_1a                                             :  6,
164                       brp_info_valid                                          :  1,
165                       reserved_after_struct16                                 :  4;
166              struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
167              uint32_t start_of_frame_timestamp_31_16                          : 16,
168                       start_of_frame_timestamp_15_0                           : 16;
169              uint32_t end_of_frame_timestamp_31_16                            : 16,
170                       end_of_frame_timestamp_15_0                             : 16;
171              uint32_t transmit_delay                                          : 16,
172                       r2r_end_status_to_follow                                :  1,
173                       response_type                                           :  5,
174                       timing_status                                           :  2,
175                       reserved_4a                                             :  7,
176                       terminate_ranging_sequence                              :  1;
177              uint32_t tpc_dbg_info_cmn_15_0                                   : 16,
178                       reserved_5a                                             :  4,
179                       tx_group_delay                                          : 12;
180              uint32_t tpc_dbg_info_47_32                                      : 16,
181                       tpc_dbg_info_cmn_31_16                                  : 16;
182              uint32_t tpc_dbg_info_chn1_31_16                                 : 16,
183                       tpc_dbg_info_chn1_15_0                                  : 16;
184              uint32_t tpc_dbg_info_chn1_63_48                                 : 16,
185                       tpc_dbg_info_chn1_47_32                                 : 16;
186              uint32_t tpc_dbg_info_chn2_15_0                                  : 16,
187                       tpc_dbg_info_chn1_79_64                                 : 16;
188              uint32_t tpc_dbg_info_chn2_47_32                                 : 16,
189                       tpc_dbg_info_chn2_31_16                                 : 16;
190              uint32_t tpc_dbg_info_chn2_79_64                                 : 16,
191                       tpc_dbg_info_chn2_63_48                                 : 16;
192              uint32_t phytx_tx_end_sw_info_31_16                              : 16,
193                       phytx_tx_end_sw_info_15_0                               : 16;
194              uint32_t phytx_tx_end_sw_info_63_48                              : 16,
195                       phytx_tx_end_sw_info_47_32                              : 16;
196              uint32_t beamform_masked_user_bitmap_31_16                       : 16,
197                       beamform_masked_user_bitmap_15_0                        : 16;
198              uint32_t pdg_mpdu_ready                                          :  1,
199                       beamform_masked_user_bitmap_36_32                       :  5,
200                       obss_pd_based_transmit_status                           :  1,
201                       srp_based_transmit_status                               :  1,
202                       obss_srg_opport_transmit_status                         :  1,
203                       static_2_pwr_mode_status                                :  1,
204                       use_alt_power_sr                                        :  1,
205                       highest_achieved_data_null_ratio                        :  5,
206                       cbf_segment_sent_mask                                   :  8,
207                       cbf_segment_request_mask                                :  8;
208              uint32_t pdg_est_mpdu_tx_count                                   : 16,
209                       pdg_mpdu_count                                          : 16;
210              uint32_t pdg_dropped_mpdu_warning                                :  1,
211                       txop_duration                                           :  7,
212                       pdg_overview_length                                     : 24;
213              uint32_t reserved_17a                                            :  4,
214                       ru_size                                                 :  4,
215                       num_data_symbols                                        : 16,
216                       stbc                                                    :  1,
217                       fec_type                                                :  1,
218                       packet_extension                                        :  3,
219                       packet_extension_pe_disambiguity                        :  1,
220                       packet_extension_a_factor                               :  2;
221              uint32_t tx_pwr_unshared                                         :  8,
222                       tx_pwr_shared                                           :  8,
223                       reserved_18b                                            :  1,
224                       force_extra_symbol                                      :  1,
225                       ldpc_extra_symbol                                       :  1,
226                       dcm                                                     :  1,
227                       reserved_18a                                            :  5,
228                       cp_setting                                              :  2,
229                       ltf_size                                                :  2,
230                       num_ltf_symbols                                         :  3;
231              uint32_t cv_corr_status                                          :  8,
232                       reserved_20a                                            :  6,
233                       ranging_ftm_frame_sent                                  :  1,
234                       ranging_sent_dummy_tx                                   :  1,
235                       ranging_active_user_map                                 : 16;
236              uint32_t reserved_21a                                            : 16,
237                       current_tx_duration                                     : 16;
238 #endif
239 };
240 
241 
242 
243 
244 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET                      0x0000000000000000
245 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB                         0
246 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB                         0
247 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK                        0x0000000000000001
248 
249 
250 
251 
252 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET                      0x0000000000000000
253 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB                         1
254 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB                         1
255 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK                        0x0000000000000002
256 
257 
258 
259 
260 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET                     0x0000000000000000
261 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB                        2
262 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB                        2
263 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK                       0x0000000000000004
264 
265 
266 
267 
268 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET                     0x0000000000000000
269 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB                        3
270 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB                        3
271 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK                       0x0000000000000008
272 
273 
274 
275 
276 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET                    0x0000000000000000
277 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB                       4
278 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB                       4
279 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK                      0x0000000000000010
280 
281 
282 
283 
284 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET                    0x0000000000000000
285 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB                       5
286 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB                       5
287 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK                      0x0000000000000020
288 
289 
290 
291 
292 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET                           0x0000000000000000
293 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB                              6
294 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB                              6
295 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK                             0x0000000000000040
296 
297 
298 
299 
300 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET                           0x0000000000000000
301 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB                              7
302 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB                              7
303 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK                             0x0000000000000080
304 
305 
306 
307 
308 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET                          0x0000000000000000
309 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB                             8
310 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB                             8
311 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK                            0x0000000000000100
312 
313 
314 
315 
316 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET                          0x0000000000000000
317 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB                             9
318 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB                             9
319 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK                            0x0000000000000200
320 
321 
322 
323 
324 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET                         0x0000000000000000
325 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB                            10
326 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB                            10
327 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK                           0x0000000000000400
328 
329 
330 
331 
332 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET                         0x0000000000000000
333 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB                            11
334 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB                            11
335 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK                           0x0000000000000800
336 
337 
338 
339 
340 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                      0x0000000000000000
341 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                         12
342 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                         12
343 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                        0x0000000000001000
344 
345 
346 
347 
348 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET                         0x0000000000000000
349 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB                            13
350 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB                            16
351 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK                           0x000000000001e000
352 
353 
354 
355 
356 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET                              0x0000000000000000
357 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB                                 17
358 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB                                 17
359 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK                                0x0000000000020000
360 
361 
362 
363 
364 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET                                    0x0000000000000000
365 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB                                       18
366 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB                                       20
367 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK                                      0x00000000001c0000
368 
369 
370 
371 
372 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET                           0x0000000000000000
373 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB                              21
374 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB                              24
375 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK                             0x0000000001e00000
376 
377 
378 
379 
380 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET                                 0x0000000000000000
381 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB                                    25
382 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB                                    30
383 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK                                   0x000000007e000000
384 
385 
386 
387 
388 #define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET                                      0x0000000000000000
389 #define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB                                         31
390 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB                                         31
391 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK                                        0x0000000080000000
392 
393 
394 
395 
396 
397 
398 
399 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
400 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB   32
401 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB   39
402 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK  0x000000ff00000000
403 
404 
405 
406 
407 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET       0x0000000000000000
408 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB          40
409 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB          45
410 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK         0x00003f0000000000
411 
412 
413 
414 
415 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET          0x0000000000000000
416 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB             46
417 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB             47
418 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK            0x0000c00000000000
419 
420 
421 
422 
423 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET                            0x0000000000000000
424 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB                               48
425 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB                               51
426 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK                              0x000f000000000000
427 
428 
429 
430 
431 #define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET                                     0x0000000000000000
432 #define TX_FES_STATUS_END_BRP_INFO_VALID_LSB                                        52
433 #define TX_FES_STATUS_END_BRP_INFO_VALID_MSB                                        52
434 #define TX_FES_STATUS_END_BRP_INFO_VALID_MASK                                       0x0010000000000000
435 
436 
437 
438 
439 #define TX_FES_STATUS_END_RESERVED_1A_OFFSET                                        0x0000000000000000
440 #define TX_FES_STATUS_END_RESERVED_1A_LSB                                           53
441 #define TX_FES_STATUS_END_RESERVED_1A_MSB                                           58
442 #define TX_FES_STATUS_END_RESERVED_1A_MASK                                          0x07e0000000000000
443 
444 
445 
446 
447 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET                           0x0000000000000000
448 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB                              59
449 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB                              59
450 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK                             0x0800000000000000
451 
452 
453 
454 
455 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                     0x0000000000000000
456 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                        60
457 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                        60
458 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                       0x1000000000000000
459 
460 
461 
462 
463 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                0x0000000000000000
464 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                   61
465 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                   61
466 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                  0x2000000000000000
467 
468 
469 
470 
471 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET                   0x0000000000000000
472 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB                      62
473 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB                      62
474 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK                     0x4000000000000000
475 
476 
477 
478 
479 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET                               0x0000000000000000
480 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB                                  63
481 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB                                  63
482 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK                                 0x8000000000000000
483 
484 
485 
486 
487 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET                      0x0000000000000008
488 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB                         0
489 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB                         15
490 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK                        0x000000000000ffff
491 
492 
493 
494 
495 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET                     0x0000000000000008
496 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB                        16
497 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB                        31
498 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK                       0x00000000ffff0000
499 
500 
501 
502 
503 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET                        0x0000000000000008
504 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB                           32
505 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB                           47
506 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK                          0x0000ffff00000000
507 
508 
509 
510 
511 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET                       0x0000000000000008
512 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB                          48
513 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB                          63
514 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK                         0xffff000000000000
515 
516 
517 
518 
519 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET                         0x0000000000000010
520 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB                            0
521 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB                            0
522 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK                           0x0000000000000001
523 
524 
525 
526 
527 #define TX_FES_STATUS_END_RESERVED_4A_OFFSET                                        0x0000000000000010
528 #define TX_FES_STATUS_END_RESERVED_4A_LSB                                           1
529 #define TX_FES_STATUS_END_RESERVED_4A_MSB                                           7
530 #define TX_FES_STATUS_END_RESERVED_4A_MASK                                          0x00000000000000fe
531 
532 
533 
534 
535 #define TX_FES_STATUS_END_TIMING_STATUS_OFFSET                                      0x0000000000000010
536 #define TX_FES_STATUS_END_TIMING_STATUS_LSB                                         8
537 #define TX_FES_STATUS_END_TIMING_STATUS_MSB                                         9
538 #define TX_FES_STATUS_END_TIMING_STATUS_MASK                                        0x0000000000000300
539 
540 
541 
542 
543 #define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET                                      0x0000000000000010
544 #define TX_FES_STATUS_END_RESPONSE_TYPE_LSB                                         10
545 #define TX_FES_STATUS_END_RESPONSE_TYPE_MSB                                         14
546 #define TX_FES_STATUS_END_RESPONSE_TYPE_MASK                                        0x0000000000007c00
547 
548 
549 
550 
551 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET                           0x0000000000000010
552 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB                              15
553 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB                              15
554 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK                             0x0000000000008000
555 
556 
557 
558 
559 #define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET                                     0x0000000000000010
560 #define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB                                        16
561 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB                                        31
562 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK                                       0x00000000ffff0000
563 
564 
565 
566 
567 #define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET                                     0x0000000000000010
568 #define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB                                        32
569 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB                                        43
570 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK                                       0x00000fff00000000
571 
572 
573 
574 
575 #define TX_FES_STATUS_END_RESERVED_5A_OFFSET                                        0x0000000000000010
576 #define TX_FES_STATUS_END_RESERVED_5A_LSB                                           44
577 #define TX_FES_STATUS_END_RESERVED_5A_MSB                                           47
578 #define TX_FES_STATUS_END_RESERVED_5A_MASK                                          0x0000f00000000000
579 
580 
581 
582 
583 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET                              0x0000000000000010
584 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB                                 48
585 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB                                 63
586 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK                                0xffff000000000000
587 
588 
589 
590 
591 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET                             0x0000000000000018
592 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB                                0
593 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB                                15
594 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK                               0x000000000000ffff
595 
596 
597 
598 
599 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET                                 0x0000000000000018
600 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB                                    16
601 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB                                    31
602 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK                                   0x00000000ffff0000
603 
604 
605 
606 
607 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET                             0x0000000000000018
608 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB                                32
609 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB                                47
610 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK                               0x0000ffff00000000
611 
612 
613 
614 
615 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET                            0x0000000000000018
616 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB                               48
617 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB                               63
618 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK                              0xffff000000000000
619 
620 
621 
622 
623 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET                            0x0000000000000020
624 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB                               0
625 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB                               15
626 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK                              0x000000000000ffff
627 
628 
629 
630 
631 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET                            0x0000000000000020
632 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB                               16
633 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB                               31
634 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK                              0x00000000ffff0000
635 
636 
637 
638 
639 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET                            0x0000000000000020
640 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB                               32
641 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB                               47
642 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK                              0x0000ffff00000000
643 
644 
645 
646 
647 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET                             0x0000000000000020
648 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB                                48
649 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB                                63
650 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK                               0xffff000000000000
651 
652 
653 
654 
655 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET                            0x0000000000000028
656 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB                               0
657 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB                               15
658 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK                              0x000000000000ffff
659 
660 
661 
662 
663 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET                            0x0000000000000028
664 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB                               16
665 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB                               31
666 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK                              0x00000000ffff0000
667 
668 
669 
670 
671 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET                            0x0000000000000028
672 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB                               32
673 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB                               47
674 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK                              0x0000ffff00000000
675 
676 
677 
678 
679 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET                            0x0000000000000028
680 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB                               48
681 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB                               63
682 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK                              0xffff000000000000
683 
684 
685 
686 
687 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET                          0x0000000000000030
688 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB                             0
689 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB                             15
690 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK                            0x000000000000ffff
691 
692 
693 
694 
695 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET                         0x0000000000000030
696 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB                            16
697 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB                            31
698 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK                           0x00000000ffff0000
699 
700 
701 
702 
703 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET                         0x0000000000000030
704 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB                            32
705 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB                            47
706 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK                           0x0000ffff00000000
707 
708 
709 
710 
711 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET                         0x0000000000000030
712 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB                            48
713 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB                            63
714 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK                           0xffff000000000000
715 
716 
717 
718 
719 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                   0x0000000000000038
720 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                      0
721 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                      15
722 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                     0x000000000000ffff
723 
724 
725 
726 
727 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                  0x0000000000000038
728 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                     16
729 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                     31
730 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                    0x00000000ffff0000
731 
732 
733 
734 
735 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET                           0x0000000000000038
736 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB                              32
737 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB                              39
738 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK                             0x000000ff00000000
739 
740 
741 
742 
743 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET                              0x0000000000000038
744 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB                                 40
745 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB                                 47
746 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK                                0x0000ff0000000000
747 
748 
749 
750 
751 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET                   0x0000000000000038
752 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB                      48
753 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB                      52
754 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK                     0x001f000000000000
755 
756 
757 
758 
759 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET                                   0x0000000000000038
760 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB                                      53
761 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB                                      53
762 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK                                     0x0020000000000000
763 
764 
765 
766 
767 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET                           0x0000000000000038
768 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB                              54
769 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB                              54
770 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK                             0x0040000000000000
771 
772 
773 
774 
775 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                    0x0000000000000038
776 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                       55
777 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                       55
778 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                      0x0080000000000000
779 
780 
781 
782 
783 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET                          0x0000000000000038
784 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB                             56
785 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB                             56
786 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK                            0x0100000000000000
787 
788 
789 
790 
791 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                      0x0000000000000038
792 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                         57
793 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                         57
794 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                        0x0200000000000000
795 
796 
797 
798 
799 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                  0x0000000000000038
800 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                     58
801 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                     62
802 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                    0x7c00000000000000
803 
804 
805 
806 
807 #define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET                                     0x0000000000000038
808 #define TX_FES_STATUS_END_PDG_MPDU_READY_LSB                                        63
809 #define TX_FES_STATUS_END_PDG_MPDU_READY_MSB                                        63
810 #define TX_FES_STATUS_END_PDG_MPDU_READY_MASK                                       0x8000000000000000
811 
812 
813 
814 
815 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET                                     0x0000000000000040
816 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB                                        0
817 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB                                        15
818 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK                                       0x000000000000ffff
819 
820 
821 
822 
823 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET                              0x0000000000000040
824 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB                                 16
825 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB                                 31
826 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK                                0x00000000ffff0000
827 
828 
829 
830 
831 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET                                0x0000000000000040
832 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB                                   32
833 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB                                   55
834 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK                                  0x00ffffff00000000
835 
836 
837 
838 
839 #define TX_FES_STATUS_END_TXOP_DURATION_OFFSET                                      0x0000000000000040
840 #define TX_FES_STATUS_END_TXOP_DURATION_LSB                                         56
841 #define TX_FES_STATUS_END_TXOP_DURATION_MSB                                         62
842 #define TX_FES_STATUS_END_TXOP_DURATION_MASK                                        0x7f00000000000000
843 
844 
845 
846 
847 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET                           0x0000000000000040
848 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB                              63
849 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB                              63
850 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK                             0x8000000000000000
851 
852 
853 
854 
855 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET                          0x0000000000000048
856 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB                             0
857 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB                             1
858 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK                            0x0000000000000003
859 
860 
861 
862 
863 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                   0x0000000000000048
864 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                      2
865 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                      2
866 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                     0x0000000000000004
867 
868 
869 
870 
871 #define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET                                   0x0000000000000048
872 #define TX_FES_STATUS_END_PACKET_EXTENSION_LSB                                      3
873 #define TX_FES_STATUS_END_PACKET_EXTENSION_MSB                                      5
874 #define TX_FES_STATUS_END_PACKET_EXTENSION_MASK                                     0x0000000000000038
875 
876 
877 
878 
879 #define TX_FES_STATUS_END_FEC_TYPE_OFFSET                                           0x0000000000000048
880 #define TX_FES_STATUS_END_FEC_TYPE_LSB                                              6
881 #define TX_FES_STATUS_END_FEC_TYPE_MSB                                              6
882 #define TX_FES_STATUS_END_FEC_TYPE_MASK                                             0x0000000000000040
883 
884 
885 
886 
887 #define TX_FES_STATUS_END_STBC_OFFSET                                               0x0000000000000048
888 #define TX_FES_STATUS_END_STBC_LSB                                                  7
889 #define TX_FES_STATUS_END_STBC_MSB                                                  7
890 #define TX_FES_STATUS_END_STBC_MASK                                                 0x0000000000000080
891 
892 
893 
894 
895 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET                                   0x0000000000000048
896 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB                                      8
897 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB                                      23
898 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK                                     0x0000000000ffff00
899 
900 
901 
902 
903 #define TX_FES_STATUS_END_RU_SIZE_OFFSET                                            0x0000000000000048
904 #define TX_FES_STATUS_END_RU_SIZE_LSB                                               24
905 #define TX_FES_STATUS_END_RU_SIZE_MSB                                               27
906 #define TX_FES_STATUS_END_RU_SIZE_MASK                                              0x000000000f000000
907 
908 
909 
910 
911 #define TX_FES_STATUS_END_RESERVED_17A_OFFSET                                       0x0000000000000048
912 #define TX_FES_STATUS_END_RESERVED_17A_LSB                                          28
913 #define TX_FES_STATUS_END_RESERVED_17A_MSB                                          31
914 #define TX_FES_STATUS_END_RESERVED_17A_MASK                                         0x00000000f0000000
915 
916 
917 
918 
919 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET                                    0x0000000000000048
920 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB                                       32
921 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB                                       34
922 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK                                      0x0000000700000000
923 
924 
925 
926 
927 #define TX_FES_STATUS_END_LTF_SIZE_OFFSET                                           0x0000000000000048
928 #define TX_FES_STATUS_END_LTF_SIZE_LSB                                              35
929 #define TX_FES_STATUS_END_LTF_SIZE_MSB                                              36
930 #define TX_FES_STATUS_END_LTF_SIZE_MASK                                             0x0000001800000000
931 
932 
933 
934 
935 #define TX_FES_STATUS_END_CP_SETTING_OFFSET                                         0x0000000000000048
936 #define TX_FES_STATUS_END_CP_SETTING_LSB                                            37
937 #define TX_FES_STATUS_END_CP_SETTING_MSB                                            38
938 #define TX_FES_STATUS_END_CP_SETTING_MASK                                           0x0000006000000000
939 
940 
941 
942 
943 #define TX_FES_STATUS_END_RESERVED_18A_OFFSET                                       0x0000000000000048
944 #define TX_FES_STATUS_END_RESERVED_18A_LSB                                          39
945 #define TX_FES_STATUS_END_RESERVED_18A_MSB                                          43
946 #define TX_FES_STATUS_END_RESERVED_18A_MASK                                         0x00000f8000000000
947 
948 
949 
950 
951 #define TX_FES_STATUS_END_DCM_OFFSET                                                0x0000000000000048
952 #define TX_FES_STATUS_END_DCM_LSB                                                   44
953 #define TX_FES_STATUS_END_DCM_MSB                                                   44
954 #define TX_FES_STATUS_END_DCM_MASK                                                  0x0000100000000000
955 
956 
957 
958 
959 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET                                  0x0000000000000048
960 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB                                     45
961 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB                                     45
962 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK                                    0x0000200000000000
963 
964 
965 
966 
967 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET                                 0x0000000000000048
968 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB                                    46
969 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB                                    46
970 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK                                   0x0000400000000000
971 
972 
973 
974 
975 #define TX_FES_STATUS_END_RESERVED_18B_OFFSET                                       0x0000000000000048
976 #define TX_FES_STATUS_END_RESERVED_18B_LSB                                          47
977 #define TX_FES_STATUS_END_RESERVED_18B_MSB                                          47
978 #define TX_FES_STATUS_END_RESERVED_18B_MASK                                         0x0000800000000000
979 
980 
981 
982 
983 #define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET                                      0x0000000000000048
984 #define TX_FES_STATUS_END_TX_PWR_SHARED_LSB                                         48
985 #define TX_FES_STATUS_END_TX_PWR_SHARED_MSB                                         55
986 #define TX_FES_STATUS_END_TX_PWR_SHARED_MASK                                        0x00ff000000000000
987 
988 
989 
990 
991 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET                                    0x0000000000000048
992 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB                                       56
993 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB                                       63
994 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK                                      0xff00000000000000
995 
996 
997 
998 
999 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET                            0x0000000000000050
1000 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB                               0
1001 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB                               15
1002 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK                              0x000000000000ffff
1003 
1004 
1005 
1006 
1007 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET                              0x0000000000000050
1008 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB                                 16
1009 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB                                 16
1010 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK                                0x0000000000010000
1011 
1012 
1013 
1014 
1015 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET                             0x0000000000000050
1016 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB                                17
1017 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB                                17
1018 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK                               0x0000000000020000
1019 
1020 
1021 
1022 
1023 #define TX_FES_STATUS_END_RESERVED_20A_OFFSET                                       0x0000000000000050
1024 #define TX_FES_STATUS_END_RESERVED_20A_LSB                                          18
1025 #define TX_FES_STATUS_END_RESERVED_20A_MSB                                          23
1026 #define TX_FES_STATUS_END_RESERVED_20A_MASK                                         0x0000000000fc0000
1027 
1028 
1029 
1030 
1031 #define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET                                     0x0000000000000050
1032 #define TX_FES_STATUS_END_CV_CORR_STATUS_LSB                                        24
1033 #define TX_FES_STATUS_END_CV_CORR_STATUS_MSB                                        31
1034 #define TX_FES_STATUS_END_CV_CORR_STATUS_MASK                                       0x00000000ff000000
1035 
1036 
1037 
1038 
1039 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET                                0x0000000000000050
1040 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB                                   32
1041 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB                                   47
1042 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK                                  0x0000ffff00000000
1043 
1044 
1045 
1046 
1047 #define TX_FES_STATUS_END_RESERVED_21A_OFFSET                                       0x0000000000000050
1048 #define TX_FES_STATUS_END_RESERVED_21A_LSB                                          48
1049 #define TX_FES_STATUS_END_RESERVED_21A_MSB                                          63
1050 #define TX_FES_STATUS_END_RESERVED_21A_MASK                                         0xffff000000000000
1051 
1052 
1053 
1054 #endif
1055