1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_MSDU_EXTENSION_H_ 27 #define _TX_MSDU_EXTENSION_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 32 33 34 struct tx_msdu_extension { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t tso_enable : 1, 37 reserved_0a : 6, 38 tcp_flag : 9, 39 tcp_flag_mask : 9, 40 reserved_0b : 7; 41 uint32_t l2_length : 16, 42 ip_length : 16; 43 uint32_t tcp_seq_number : 32; 44 uint32_t ip_identification : 16, 45 udp_length : 16; 46 uint32_t checksum_offset : 14, 47 partial_checksum_en : 1, 48 reserved_4a : 1, 49 payload_start_offset : 14, 50 reserved_4b : 2; 51 uint32_t payload_end_offset : 14, 52 reserved_5a : 2, 53 wds : 1, 54 reserved_5b : 15; 55 uint32_t buf0_ptr_31_0 : 32; 56 uint32_t buf0_ptr_39_32 : 8, 57 extn_override : 1, 58 encap_type : 2, 59 encrypt_type : 4, 60 tqm_no_drop : 1, 61 buf0_len : 16; 62 uint32_t buf1_ptr_31_0 : 32; 63 uint32_t buf1_ptr_39_32 : 8, 64 epd : 1, 65 mesh_enable : 2, 66 reserved_9a : 5, 67 buf1_len : 16; 68 uint32_t buf2_ptr_31_0 : 32; 69 uint32_t buf2_ptr_39_32 : 8, 70 dscp_tid_table_num : 6, 71 reserved_11a : 2, 72 buf2_len : 16; 73 uint32_t buf3_ptr_31_0 : 32; 74 uint32_t buf3_ptr_39_32 : 8, 75 reserved_13a : 8, 76 buf3_len : 16; 77 uint32_t buf4_ptr_31_0 : 32; 78 uint32_t buf4_ptr_39_32 : 8, 79 reserved_15a : 8, 80 buf4_len : 16; 81 uint32_t buf5_ptr_31_0 : 32; 82 uint32_t buf5_ptr_39_32 : 8, 83 reserved_17a : 8, 84 buf5_len : 16; 85 #else 86 uint32_t reserved_0b : 7, 87 tcp_flag_mask : 9, 88 tcp_flag : 9, 89 reserved_0a : 6, 90 tso_enable : 1; 91 uint32_t ip_length : 16, 92 l2_length : 16; 93 uint32_t tcp_seq_number : 32; 94 uint32_t udp_length : 16, 95 ip_identification : 16; 96 uint32_t reserved_4b : 2, 97 payload_start_offset : 14, 98 reserved_4a : 1, 99 partial_checksum_en : 1, 100 checksum_offset : 14; 101 uint32_t reserved_5b : 15, 102 wds : 1, 103 reserved_5a : 2, 104 payload_end_offset : 14; 105 uint32_t buf0_ptr_31_0 : 32; 106 uint32_t buf0_len : 16, 107 tqm_no_drop : 1, 108 encrypt_type : 4, 109 encap_type : 2, 110 extn_override : 1, 111 buf0_ptr_39_32 : 8; 112 uint32_t buf1_ptr_31_0 : 32; 113 uint32_t buf1_len : 16, 114 reserved_9a : 5, 115 mesh_enable : 2, 116 epd : 1, 117 buf1_ptr_39_32 : 8; 118 uint32_t buf2_ptr_31_0 : 32; 119 uint32_t buf2_len : 16, 120 reserved_11a : 2, 121 dscp_tid_table_num : 6, 122 buf2_ptr_39_32 : 8; 123 uint32_t buf3_ptr_31_0 : 32; 124 uint32_t buf3_len : 16, 125 reserved_13a : 8, 126 buf3_ptr_39_32 : 8; 127 uint32_t buf4_ptr_31_0 : 32; 128 uint32_t buf4_len : 16, 129 reserved_15a : 8, 130 buf4_ptr_39_32 : 8; 131 uint32_t buf5_ptr_31_0 : 32; 132 uint32_t buf5_len : 16, 133 reserved_17a : 8, 134 buf5_ptr_39_32 : 8; 135 #endif 136 }; 137 138 139 140 141 #define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 142 #define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 143 #define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 144 #define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 145 146 147 148 149 #define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 150 #define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 151 #define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 152 #define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e 153 154 155 156 157 #define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 158 #define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 159 #define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 160 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 161 162 163 164 165 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 166 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 167 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 168 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 169 170 171 172 173 #define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 174 #define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 175 #define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 176 #define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 177 178 179 180 181 #define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 182 #define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 183 #define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 184 #define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff 185 186 187 188 189 #define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 190 #define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 191 #define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 192 #define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 193 194 195 196 197 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 198 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 199 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 200 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff 201 202 203 204 205 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c 206 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 207 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 208 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff 209 210 211 212 213 #define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c 214 #define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 215 #define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 216 #define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 217 218 219 220 221 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 222 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 223 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 224 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff 225 226 227 228 229 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 230 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 231 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 232 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 233 234 235 236 237 #define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 238 #define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 239 #define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 240 #define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 241 242 243 244 245 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 246 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 247 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 248 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 249 250 251 252 253 #define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 254 #define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 255 #define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 256 #define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 257 258 259 260 261 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 262 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 263 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 264 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff 265 266 267 268 269 #define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 270 #define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 271 #define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 272 #define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 273 274 275 276 277 #define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 278 #define TX_MSDU_EXTENSION_WDS_LSB 16 279 #define TX_MSDU_EXTENSION_WDS_MSB 16 280 #define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 281 282 283 284 285 #define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 286 #define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 287 #define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 288 #define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 289 290 291 292 293 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 294 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 295 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 296 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff 297 298 299 300 301 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c 302 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 303 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 304 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff 305 306 307 308 309 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c 310 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 311 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 312 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 313 314 315 316 317 #define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c 318 #define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 319 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 320 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 321 322 323 324 325 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c 326 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 327 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 328 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 329 330 331 332 333 #define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c 334 #define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 335 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 336 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 337 338 339 340 341 #define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c 342 #define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 343 #define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 344 #define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 345 346 347 348 349 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 350 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 351 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 352 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff 353 354 355 356 357 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 358 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 359 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 360 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff 361 362 363 364 365 #define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 366 #define TX_MSDU_EXTENSION_EPD_LSB 8 367 #define TX_MSDU_EXTENSION_EPD_MSB 8 368 #define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 369 370 371 372 373 #define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 374 #define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 375 #define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 376 #define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 377 378 379 380 381 #define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 382 #define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 383 #define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 384 #define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 385 386 387 388 389 #define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 390 #define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 391 #define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 392 #define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 393 394 395 396 397 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 398 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 399 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 400 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff 401 402 403 404 405 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c 406 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 407 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 408 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff 409 410 411 412 413 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c 414 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 415 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 416 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 417 418 419 420 421 #define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c 422 #define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 423 #define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 424 #define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 425 426 427 428 429 #define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c 430 #define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 431 #define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 432 #define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 433 434 435 436 437 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 438 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 439 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 440 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff 441 442 443 444 445 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 446 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 447 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 448 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff 449 450 451 452 453 #define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 454 #define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 455 #define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 456 #define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 457 458 459 460 461 #define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 462 #define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 463 #define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 464 #define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 465 466 467 468 469 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 470 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 471 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 472 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff 473 474 475 476 477 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c 478 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 479 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 480 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff 481 482 483 484 485 #define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c 486 #define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 487 #define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 488 #define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 489 490 491 492 493 #define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c 494 #define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 495 #define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 496 #define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 497 498 499 500 501 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 502 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 503 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 504 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff 505 506 507 508 509 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 510 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 511 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 512 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff 513 514 515 516 517 #define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 518 #define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 519 #define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 520 #define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 521 522 523 524 525 #define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 526 #define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 527 #define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 528 #define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 529 530 531 532 #endif 533