1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_QUEUE_EXTENSION_H_ 27 #define _TX_QUEUE_EXTENSION_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 32 33 #define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 34 35 36 struct tx_queue_extension { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t frame_ctl : 16, 39 qos_ctl : 16; 40 uint32_t ampdu_flag : 1, 41 tx_notify_no_htc_override : 1, 42 reserved_1a : 7, 43 checksum_tso_disable_for_frag : 1, 44 key_id : 8, 45 qos_buf_state_overwrite : 1, 46 buf_state_sta_id : 1, 47 buf_state_source : 1, 48 ht_control_overwrite_enable : 1, 49 ht_control_overwrite_source : 4, 50 reserved_1b : 6; 51 uint32_t ul_headroom_insertion_enable : 1, 52 ul_headroom_offset : 5, 53 bqrp_insertion_enable : 1, 54 bqrp_offset : 5, 55 ul_headroom_rsvd_7_6 : 2, 56 bqr_rsvd_9_8 : 2, 57 base_pn_63_48 : 16; 58 uint32_t base_pn_95_64 : 32; 59 uint32_t base_pn_127_96 : 32; 60 uint32_t ht_control_field_bw20 : 32; 61 uint32_t ht_control_field_bw40 : 32; 62 uint32_t ht_control_field_bw80 : 32; 63 uint32_t ht_control_field_bw160 : 32; 64 uint32_t ht_control_overwrite_mask : 32; 65 uint32_t cas_control_info : 8, 66 cas_offset : 5, 67 cas_insertion_enable : 1, 68 reserved_10a : 2, 69 ht_control_overwrite_source_for_srp : 4, 70 ht_control_overwrite_source_for_bsrp : 4, 71 reserved_10b : 6, 72 mpdu_hdr_len_override_en : 1, 73 bar_ssn_overwrite_enable : 1; 74 uint32_t bar_ssn_offset : 12, 75 mpdu_hdr_len_override_val : 9, 76 reserved_11a : 11; 77 uint32_t ht_control_field_bw320 : 32; 78 uint32_t fw2sw_info : 32; 79 #else 80 uint32_t qos_ctl : 16, 81 frame_ctl : 16; 82 uint32_t reserved_1b : 6, 83 ht_control_overwrite_source : 4, 84 ht_control_overwrite_enable : 1, 85 buf_state_source : 1, 86 buf_state_sta_id : 1, 87 qos_buf_state_overwrite : 1, 88 key_id : 8, 89 checksum_tso_disable_for_frag : 1, 90 reserved_1a : 7, 91 tx_notify_no_htc_override : 1, 92 ampdu_flag : 1; 93 uint32_t base_pn_63_48 : 16, 94 bqr_rsvd_9_8 : 2, 95 ul_headroom_rsvd_7_6 : 2, 96 bqrp_offset : 5, 97 bqrp_insertion_enable : 1, 98 ul_headroom_offset : 5, 99 ul_headroom_insertion_enable : 1; 100 uint32_t base_pn_95_64 : 32; 101 uint32_t base_pn_127_96 : 32; 102 uint32_t ht_control_field_bw20 : 32; 103 uint32_t ht_control_field_bw40 : 32; 104 uint32_t ht_control_field_bw80 : 32; 105 uint32_t ht_control_field_bw160 : 32; 106 uint32_t ht_control_overwrite_mask : 32; 107 uint32_t bar_ssn_overwrite_enable : 1, 108 mpdu_hdr_len_override_en : 1, 109 reserved_10b : 6, 110 ht_control_overwrite_source_for_bsrp : 4, 111 ht_control_overwrite_source_for_srp : 4, 112 reserved_10a : 2, 113 cas_insertion_enable : 1, 114 cas_offset : 5, 115 cas_control_info : 8; 116 uint32_t reserved_11a : 11, 117 mpdu_hdr_len_override_val : 9, 118 bar_ssn_offset : 12; 119 uint32_t ht_control_field_bw320 : 32; 120 uint32_t fw2sw_info : 32; 121 #endif 122 }; 123 124 125 126 127 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 128 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 129 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 130 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff 131 132 133 134 135 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 136 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 137 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 138 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 139 140 141 142 143 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 144 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 145 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 146 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 147 148 149 150 151 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 152 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 153 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 154 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 155 156 157 158 159 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 160 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 161 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 162 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 163 164 165 166 167 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 168 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 169 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 170 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 171 172 173 174 175 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 176 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 177 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 178 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 179 180 181 182 183 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 184 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 185 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 186 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 187 188 189 190 191 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 192 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 193 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 194 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 195 196 197 198 199 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 200 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 201 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 202 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 203 204 205 206 207 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 208 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 209 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 210 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 211 212 213 214 215 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 216 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 217 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 218 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 219 220 221 222 223 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 224 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 225 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 226 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 227 228 229 230 231 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 232 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 233 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 234 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 235 236 237 238 239 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 240 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 241 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 242 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e 243 244 245 246 247 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 248 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 249 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 250 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 251 252 253 254 255 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 256 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 257 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 258 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 259 260 261 262 263 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 264 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 265 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 266 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 267 268 269 270 271 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 272 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 273 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 274 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 275 276 277 278 279 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 280 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 281 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 282 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 283 284 285 286 287 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 288 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 289 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 290 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 291 292 293 294 295 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 296 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 297 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 298 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff 299 300 301 302 303 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 304 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 305 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 306 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 307 308 309 310 311 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 312 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 313 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 314 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff 315 316 317 318 319 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 320 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 321 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 322 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 323 324 325 326 327 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 328 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 329 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 330 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff 331 332 333 334 335 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 336 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 337 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 338 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 339 340 341 342 343 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 344 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 345 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 346 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff 347 348 349 350 351 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 352 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 353 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 354 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 355 356 357 358 359 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 360 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 361 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 362 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 363 364 365 366 367 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 368 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 369 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 370 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 371 372 373 374 375 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 376 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 377 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 378 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 379 380 381 382 383 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 384 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 385 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 386 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 387 388 389 390 391 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 392 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 393 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 394 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 395 396 397 398 399 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 400 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 401 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 402 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 403 404 405 406 407 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 408 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 409 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 410 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 411 412 413 414 415 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 416 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 417 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 418 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 419 420 421 422 423 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 424 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 425 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 426 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 427 428 429 430 431 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 432 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 433 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 434 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 435 436 437 438 439 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 440 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 441 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 442 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff 443 444 445 446 447 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 448 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 449 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 450 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 451 452 453 454 #endif 455