1 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 21 22 23 24 25 26 27 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 28 #define _U_SIG_EHT_SU_MU_INFO_H_ 29 #if !defined(__ASSEMBLER__) 30 #endif 31 32 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 33 34 35 struct u_sig_eht_su_mu_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t phy_version : 3, // [2:0] 38 transmit_bw : 3, // [5:3] 39 dl_ul_flag : 1, // [6:6] 40 bss_color_id : 6, // [12:7] 41 txop_duration : 7, // [19:13] 42 disregard_0a : 5, // [24:20] 43 validate_0b : 1, // [25:25] 44 reserved_0c : 6; // [31:26] 45 uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] 46 validate_1a : 1, // [2:2] 47 punctured_channel_information : 5, // [7:3] 48 validate_1b : 1, // [8:8] 49 mcs_of_eht_sig : 2, // [10:9] 50 num_eht_sig_symbols : 5, // [15:11] 51 crc : 4, // [19:16] 52 tail : 6, // [25:20] 53 dot11ax_su_extended : 1, // [26:26] 54 reserved_1d : 3, // [29:27] 55 rx_ndp : 1, // [30:30] 56 rx_integrity_check_passed : 1; // [31:31] 57 #else 58 uint32_t reserved_0c : 6, // [31:26] 59 validate_0b : 1, // [25:25] 60 disregard_0a : 5, // [24:20] 61 txop_duration : 7, // [19:13] 62 bss_color_id : 6, // [12:7] 63 dl_ul_flag : 1, // [6:6] 64 transmit_bw : 3, // [5:3] 65 phy_version : 3; // [2:0] 66 uint32_t rx_integrity_check_passed : 1, // [31:31] 67 rx_ndp : 1, // [30:30] 68 reserved_1d : 3, // [29:27] 69 dot11ax_su_extended : 1, // [26:26] 70 tail : 6, // [25:20] 71 crc : 4, // [19:16] 72 num_eht_sig_symbols : 5, // [15:11] 73 mcs_of_eht_sig : 2, // [10:9] 74 validate_1b : 1, // [8:8] 75 punctured_channel_information : 5, // [7:3] 76 validate_1a : 1, // [2:2] 77 eht_ppdu_sig_cmn_type : 2; // [1:0] 78 #endif 79 }; 80 81 82 83 84 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 85 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 86 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 87 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 88 89 90 91 92 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 93 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 94 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 95 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 96 97 98 99 100 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 101 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 102 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 103 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 104 105 106 107 108 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 109 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 110 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 111 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 112 113 114 115 116 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 117 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 118 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 119 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 120 121 122 123 124 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 125 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 126 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 127 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 128 129 130 131 132 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 133 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 134 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 135 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 136 137 138 139 140 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 141 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 142 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 143 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 144 145 146 147 148 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 149 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 150 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 151 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 152 153 154 155 156 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 157 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 158 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 159 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 160 161 162 163 164 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 165 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 166 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 167 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 168 169 170 171 172 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 173 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 174 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 175 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 176 177 178 179 180 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 181 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 182 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 183 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 184 185 186 187 188 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 189 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 190 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 191 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 192 193 194 195 196 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 197 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 198 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 199 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 200 201 202 203 204 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 205 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 206 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 207 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 208 209 210 211 212 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 213 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 214 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 215 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 216 217 218 219 220 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 221 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 222 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 223 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 224 225 226 227 228 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 229 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 230 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 231 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 232 233 234 235 236 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 237 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 238 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 239 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 240 241 242 243 244 #endif 245