xref: /wlan-driver/fw-api/hw/qcn9224/v1/vht_sig_b_su20_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
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25 
26 
27 #ifndef _VHT_SIG_B_SU20_INFO_H_
28 #define _VHT_SIG_B_SU20_INFO_H_
29 #if !defined(__ASSEMBLER__)
30 #endif
31 
32 #define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
33 
34 
35 struct vht_sig_b_su20_info {
36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
37              uint32_t length                                                  : 17, // [16:0]
38                       vhtb_reserved                                           :  3, // [19:17]
39                       tail                                                    :  6, // [25:20]
40                       reserved                                                :  5, // [30:26]
41                       rx_ndp                                                  :  1; // [31:31]
42 #else
43              uint32_t rx_ndp                                                  :  1, // [31:31]
44                       reserved                                                :  5, // [30:26]
45                       tail                                                    :  6, // [25:20]
46                       vhtb_reserved                                           :  3, // [19:17]
47                       length                                                  : 17; // [16:0]
48 #endif
49 };
50 
51 
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53 
54 #define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
55 #define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
56 #define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
57 #define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
58 
59 
60 
61 
62 #define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
63 #define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
64 #define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
65 #define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
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69 
70 #define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
71 #define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
72 #define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
73 #define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
74 
75 
76 
77 
78 #define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
79 #define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
80 #define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
81 #define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
82 
83 
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85 
86 #define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
87 #define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
88 #define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
89 #define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
90 
91 
92 
93 
94 #endif
95