xref: /wlan-driver/fw-api/hw/qcn9224/v2/he_sig_a_mu_ul_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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17 
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19 
20 
21 
22 
23 
24 
25 
26 #ifndef _HE_SIG_A_MU_UL_INFO_H_
27 #define _HE_SIG_A_MU_UL_INFO_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
32 
33 
34 struct he_sig_a_mu_ul_info {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t format_indication                                       :  1,
37                       bss_color_id                                            :  6,
38                       spatial_reuse                                           : 16,
39                       reserved_0a                                             :  1,
40                       transmit_bw                                             :  2,
41                       reserved_0b                                             :  6;
42              uint32_t txop_duration                                           :  7,
43                       reserved_1a                                             :  9,
44                       crc                                                     :  4,
45                       tail                                                    :  6,
46                       reserved_1b                                             :  5,
47                       rx_integrity_check_passed                               :  1;
48 #else
49              uint32_t reserved_0b                                             :  6,
50                       transmit_bw                                             :  2,
51                       reserved_0a                                             :  1,
52                       spatial_reuse                                           : 16,
53                       bss_color_id                                            :  6,
54                       format_indication                                       :  1;
55              uint32_t rx_integrity_check_passed                               :  1,
56                       reserved_1b                                             :  5,
57                       tail                                                    :  6,
58                       crc                                                     :  4,
59                       reserved_1a                                             :  9,
60                       txop_duration                                           :  7;
61 #endif
62 };
63 
64 
65 
66 
67 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
68 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
69 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
70 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
71 
72 
73 
74 
75 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
76 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
77 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
78 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
79 
80 
81 
82 
83 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
84 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
85 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
86 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
87 
88 
89 
90 
91 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
92 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
93 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
94 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
95 
96 
97 
98 
99 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
100 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
101 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
102 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
103 
104 
105 
106 
107 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
108 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
109 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
110 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
111 
112 
113 
114 
115 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
116 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
117 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
118 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
119 
120 
121 
122 
123 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
124 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
125 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
126 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
127 
128 
129 
130 
131 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
132 #define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
133 #define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
134 #define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
135 
136 
137 
138 
139 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
140 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
141 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
142 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
143 
144 
145 
146 
147 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
148 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
149 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
150 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
151 
152 
153 
154 
155 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
156 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
157 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
158 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
159 
160 
161 
162 #endif
163